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KR950027909A - Method for manufacturing charge storage electrode of capacitor - Google Patents

Method for manufacturing charge storage electrode of capacitor Download PDF

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Publication number
KR950027909A
KR950027909A KR1019940005702A KR19940005702A KR950027909A KR 950027909 A KR950027909 A KR 950027909A KR 1019940005702 A KR1019940005702 A KR 1019940005702A KR 19940005702 A KR19940005702 A KR 19940005702A KR 950027909 A KR950027909 A KR 950027909A
Authority
KR
South Korea
Prior art keywords
dope
charge storage
amorphous silicon
undoped
storage electrode
Prior art date
Application number
KR1019940005702A
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Korean (ko)
Inventor
우상호
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019940005702A priority Critical patent/KR950027909A/en
Publication of KR950027909A publication Critical patent/KR950027909A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 캐패시터의 전하저장전극을 제조하는 방법에 관한 것으로, 도프 산화막(Doped Oxide)과 언도프 산화막을 순차적으로 적층한 후 이들의 습식 식각 선택비를 이용하여 핀형 산화막 구조를 이룬다음 활성화된 도프반구형 폴리실리콘을 증착 및 스페이서 식각하고, 활성화 되지 않은 도프 비정질 실리콘막을 증착하여 스페이서 식각으로 측벽을 실린더 구조로 형성하고, 산화막 습식식각 공정으로 상기 핀 구조를 이룬 산화막을 제거한 후 다시 폴리 습식식각 공정으로 반구형 폴리실리콘을 제거하여 내부가 표면 음각된 핀을 갖는 전하저장전극을 형성하고 유효표면적을 증대시키므로써 제한된 면적에서 고축적용량을 얻을 수 있는 캐패시터의 전하저장전극을 제조하는 방법에 관해 기술된다.The present invention relates to a method of manufacturing a charge storage electrode of a capacitor, and sequentially stacks a dope oxide layer and an undoped oxide layer, and then forms a fin-type oxide structure using their wet etching selectivity, and then activates the dope. Hemispherical polysilicon is deposited and spacer etched, and an undoped dope amorphous silicon film is deposited to form a sidewall in a cylinder structure by spacer etching, and an oxide wet etching process removes the oxide film forming the fin structure, and then back into a poly wet etching process. Disclosed is a method of manufacturing a charge storage electrode of a capacitor capable of obtaining a high storage capacity in a limited area by removing a hemispherical polysilicon to form a charge storage electrode having a surface engraved pin and increasing an effective surface area.

Description

캐패시터의 전하저장전극을 제조방법Method of manufacturing a charge storage electrode of a capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1E도는 본 발명에 의한 캐패시터의 전하저장전극을 제조하는 단계를 도시한 단면도.1A to 1E are cross-sectional views illustrating steps of manufacturing a charge storage electrode of a capacitor according to the present invention.

Claims (5)

유효표면적을 증대시키기 위한 캐패시터의 전하저장전극 제조방법에 있어서, 실리콘 기판(1)상에 트랜지스터 및 비트라인을 구성하고, 전체 상부에 층간 절연막을 형성한 후 전하저장전극 콘택홀(8)을 형성한 상태에서, 상기 콘택홀(8) 내에 제1도프 비정질 실리콘막(9)을 채우고, 전체구조 상부에 언도프 비정질 실리콘막(10)을 형성하는 단계와, 상기 단계로부터 제1도프 산화막(11A), 제1언도프 산화막(12A), 제2도프 산화막(11B) 및 제2언도프 산화막(12B)을 순차적으로 교대로 형성한 후 전하저장전극 내부를 설정하는 소정의 마스크를 사용하여 상기 산화막(11A, 11B, 12A, 12B)을 패턴화하는 단계와, 상기 단계로부터 도프와 언도프 산화막의 선택 식각특성을갖는 습식식각 공정으로 상기 제1 및 제2도프 산화막(11A, 11B)을 소정깊이 식각하여 핀 구조의 산화막을 형성하고 전체구조 상부에 불순물을 활성화시킨 도프 반구형 폴리실리콘(13)을 형성하는 단계와, 상기 단계로부터 폴리스페이서 식각공정으로 상기 활성화된 도프반구형 폴리실리콘(13)과 하부의 언도프 비정질 실리콘막(10)을 식각하는 단계와 상기 단계로부터 제2도프 비정질 실리콘막 또는 언도프 비정질 실리콘막(14)으로 상기 식각된 도프 반구형 폴리실리콘(13) 및 비정질 실리콘막(14) 측벽에 스페이서를 형성하는 단계와, 상기단계로부터 제2도프 비정질 실리콘막 또는 언도프 비정질 실리콘막(14) 스페이서로 둘러싸인 핀구조 산화막(11A, 11B, 12A, 12B)을 산화막 습식식각공정으로 완전히 제거하고, 폴리습식식각용액으로 활성화된 도프 반구형 폴리실리콘(13)을 제거하여 내부가 표면 음각된 핀을 갖는 실린더형 전하저장전극(20)을 완성하는 단계로 이루어지는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.In the method of manufacturing a charge storage electrode of a capacitor for increasing the effective surface area, a transistor and a bit line are formed on a silicon substrate 1, an interlayer insulating film is formed over the entire surface, and then the charge storage electrode contact hole 8 is formed. In this state, the first dope amorphous silicon film 9 is filled in the contact hole 8, and the undoped amorphous silicon film 10 is formed on the entire structure, and the first dope oxide film 11A is formed from the above step. ), The first undoped oxide film 12A, the second dope oxide film 11B, and the second undoped oxide film 12B are sequentially formed, and then the oxide film is formed using a predetermined mask for setting the inside of the charge storage electrode. Patterning (11A, 11B, 12A, 12B), and a wet etching process having a selective etching characteristic of the dope and undoped oxide film from the step, the first and second dope oxide film (11A, 11B) to a predetermined depth Etch to form oxide of fin structure And forming a doped hemispherical polysilicon 13 in which impurities are activated on the entire structure, and activating the doped hemispherical polysilicon 13 and a lower undoped amorphous silicon film 10 by a polyphase etching process. ) And forming a spacer on sidewalls of the dope hemispherical polysilicon 13 and the amorphous silicon film 14 from the step into the second dope amorphous silicon film or the undoped amorphous silicon film 14. From the above step, the fin structure oxide films 11A, 11B, 12A, and 12B surrounded by the second dope amorphous silicon film or the undoped amorphous silicon film 14 spacer are completely removed by the oxide wet etching process, and activated with a polywet etching solution. Removing the doped hemispherical polysilicon 13 to complete the cylindrical charge storage electrode 20 having a pinned surface inside. Method for manufacturing a charge storage electrode of a capacitor, characterized in that the loss. 제1항에 있어서, 상기 제1 및 2도프 산화막(11A, 11B)은 BPSG, PSG이며, 상기 제1 및 2언도프 산화막(12A, 12B)은 MTO, HTO인 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The charge storage of a capacitor according to claim 1, wherein the first and second dope oxide films 11A and 11B are BPSG and PSG, and the first and second undoped oxide films 12A and 12B are MTO and HTO. Electrode manufacturing method. 제1항에 있어서, 상기 제2도프 비정질 실리콘막 또는 언도프 비정질 실리콘막(14)은 550℃이하의 온도하에서 증착하여 불순물이 활성하되지 않도록 형성하는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the second dope amorphous silicon film or the undoped amorphous silicon film 14 is deposited under a temperature of 550 ° C. or less so that impurities are not activated. . 제1항에 있어서, 상기 폴리습식식각용액은 HNO2: CH3COOH : HF : DI 또는 HNO2: HF : DI로 이루어지는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of claim 1, wherein the poly wet etching solution comprises HNO 2 : CH 3 COOH: HF: DI or HNO 2 : HF: DI. 제1항에 있어서, 상기 도프 및 언도프 산화막을 교대로 2개층 이상 적층하여 다층의 핀 구조 산화막을 형성하여 내부가 다층 핀을 갖는 것을 특징으로 하는 캐패시터의 전하저장전극 제조방법.The method of manufacturing a charge storage electrode of a capacitor according to claim 1, wherein two or more layers of the dope and the undoped oxide film are alternately stacked to form a multilayer fin structure oxide film, and the interior has multilayer fins. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005702A 1994-03-22 1994-03-22 Method for manufacturing charge storage electrode of capacitor KR950027909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940005702A KR950027909A (en) 1994-03-22 1994-03-22 Method for manufacturing charge storage electrode of capacitor

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KR1019940005702A KR950027909A (en) 1994-03-22 1994-03-22 Method for manufacturing charge storage electrode of capacitor

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KR950027909A true KR950027909A (en) 1995-10-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11149780B2 (en) 2013-09-23 2021-10-19 The Boeing Company Method of covering a portion of a fastener protruding from a surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11149780B2 (en) 2013-09-23 2021-10-19 The Boeing Company Method of covering a portion of a fastener protruding from a surface

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