KR950009422B1 - Data serial transmission device using commer-free code - Google Patents

Abstract

a first ROM for comma-precoding input data according to a control signal of 171.H; a serial converting part for converting an output of the first ROM into a serial output; a line driving part for providing the output signal of the serial converting part to a receiver; a pulse forming part for pulse-forming the output signal of the line driving part; a shift registering part for changing and outputting a signal of the pulse forming part; a second ROM for comma-precoding a signal of the shift registering part; and a PLL controlling part for receiving a signal from the second ROM and the pulse forming part, making a PLL control signal, and detecting error from the signal. Thereby, in present invention, signals of 2.69MHz and 37.66MHz are outputted to the shift registering part, the second ROM, and the PLL controlling part.

Description

Data serial transmission device using kerma-precode

1 is a circuit block diagram of a serial transmission device.

2 is a circuit block diagram using clock recovery.

3 is an NRZ code signal waveform.

4 is a schematic diagram of an NRZI code signal waveform and a generator.

5 is a two-phase mark coded waveform diagram.

6 is a product coded waveform diagram of Miller and Miller.

7 is a circuit block diagram of a serial transmission device of the present invention.

* Explanation of symbols for main parts of the drawings

11: ROM 12: Serial Converter

13: Line driver 14: Pulse shaping part

15: shift register section 16: ROM

17: PLL control unit 18: PLL unit

The present invention relates to a signal serial transmission apparatus, and more particularly, to a data serial transmission apparatus using a kerma-precode capable of self-synchronization without a separate data marker and lowering a frequency of a PLL (Phase Locked Loop) control signal. It is about.

1 shows a circuit block diagram of a serial transmission apparatus for explaining the conventional technology.

The output data of the serial encoder 2 and the serial encoder 2 which converts the parallel data inputted from the transmitter sub-processor 1 into the transmitter sub-processor 1 for processing the video data and other necessary data in series. A line driver 3 for transmitting a digital signal on the terminated signal line, a serial decoder 4 for converting serial data output from the line driver 3 in parallel, and output data of the serial decoder 4 And a subprocessor 5 for processing in a receiver.

2 is a circuit block diagram for clock recovery, and includes a delay unit 6 which receives serial data and delays it to produce edge information, and outputs an input signal and an output signal of the delay unit 6. An edge pulse generator 7 for producing edge information, a phase detector 8 for comparing the phase of the input data with a reference clock, and a signal voltage input from the phase detector 8 are controlled to oscillate to output a serial clock signal. And a data recovery section 10 for recovering data by outputting the outputs of the delay section 6 and the voltage controlled oscillation section 9 and outputting the reclocked data.

Referring to the operation of the first and second degrees having the configuration as described above is as follows.

FIG. 1 receives the video data and other necessary information from the coprocessor 1, processes them, and outputs them. The data is serially converted by the serial encoder 2 and output.

The line configurator 3 receiving this signal outputs a digital signal to the line, changes this signal in parallel in the output decoder 4, and then inputs the receiver coprocessor 5 to output data.

And the most important aspect in serial data transmission is to make the PLL (Pulse Locked Loop) work well by making edge information through channel coding to facilitate this with clock recovery.

This function is performed by the serial encoder (2).

Well-known channel coding methods include Non Return to Zero (NRZ), Non Return to Zero Inverse (NRZI), Bi-phase Mark (Manchester code), and Miller coding techniques.

FIG. 3 is a waveform of a non-return to zero (NRZ) serial data waveform and a data clock. The serial waveform is output from the serial transmission circuit of FIG. 1 and input to FIG. 2. The data clock waveform is shown in FIG. It is a digital data waveform output from the clock recovery circuit of FIG.

4 shows an NRZI encoding circuit and a waveform diagram. The encoding circuit includes an EXOR gate 21 for inputting the NRZ output waveform of FIG. 3, and a flip-flop for inputting the output of the EXOR gate 21 and a data clock signal. NRZI (Non-Return to Zero Inverse) is called and output waveform.

5 shows waveforms of two-phase mark encoding, and shows waveforms of signals outputted with an inverted phase from an input signal.

6 shows the encoded output waveforms of Miller and Miller Square.

As described above, the channel coding technique of the related art does not have an error detection function, and when the PLL control is implemented at the same frequency as the day transmission rate (Rate) during PLL (Phase Locked Loop) control, it becomes difficult to implement the PLL.

In addition, data marker information is required to convert serial data into parallel data, and several bits of data are required to obtain such information.

In other words, if the data is 10 bits, some additional bits are required to obtain additional data marker information other than 10 bits.

The present invention has been made to solve the problems of the prior art, and by using the kerma-precode to control the PLL in units of words (not bits), self-synchronization is possible without a separate data marker. The purpose is to reduce the frequency of the control signal.

Referring to the accompanying drawings, an embodiment of the present invention for achieving the above object is as follows.

7 is a circuit block diagram of a serial transmission apparatus for explaining the present invention, in which an input data of 10 bits and a clock signal of 171H (2.69 MHz) are shown.

That is, the ROM 11 for kerma-precoding, which converts 10 bits of data into 14 bits of data using the clock signal 171H (2.69 MHz), and converts the signal and the clock signal of the ROM 11 into serial data. A serial converter 12, a line driver 13 for outputting serial data output from the serial converter 12 to a receiver, and a pulse shaping unit 14 for pulse shaping the serial data output from the line driver 13 ), A shift register section 15 for converting serial data of the pulse shaping section 14 into parallel data, and a ROM for comma-precoding the output signal of the shift register section 15 (16484 x 14 bits). (16), a PLL stir section (17) for detecting errors and edges of the signal output from the ROM (16), and a clock having a frequency of 2.69 MHz and 37.66 MHz in response to a signal from the PLL control section (17). (15) and a PLL (2.69 MHz) which is applied to the PLL control unit 17 and a clock of 2.69 MHz is applied to the ROM 16. 18).

The operation of the data serial transmission device having such a configuration is as follows.

The 10-bit input data is controlled by clock 171H and input to ROM (1024 x 14 bits) 11 for kerma-precoding.

The 14-bit data output from the ROM 11 is converted into serial data by the serial converter 12 and transmitted to the receiver via the line driver 13.

At this time, the serial converter 12 receives 171H (2.69MHz) and 171H × 14 (37.66MHz) clocks from the PLL to generate serial data.

The signal converted in series from the above is transmitted using a coaxial cable when transmitted to the receiver. The signal input from the transmitter is pulse-formed by the pulse shaping unit 14, and one signal is input to the PLL control unit 17 to produce a PLL control signal, and the other signal is input to the shift register 15 to be converted into a parallel signal form and output. .

At this time, the serial signal input to the shift register 15 uses a clock of 2.69 MHz in order to convert it into a parallel signal (data) using a clock of 37.66 MHz.

The signal converted into a parallel signal from the shift register 15 and outputted is input to the ROM (16384 x 14 bits) 16 for comma-precoding, and comma-precoded by a clock of 2.69 kHz PLL.

The PLL controller 17, which receives the signal output from the ROM 16 and the pulse shaping signal, generates a PLL control signal, detects an error, and outputs a signal. The PLL controller 18, which receives the signal from the PLL controller 17, It outputs PLL control signals of 37.66MHz and 2.69MHz.

Thus, the error probability of the camera-precode in the serial transmission device is as follows.

If X = n is an error code of n bits and the error is not detectable, then P is the probability that an error occurs at a certain position, P is the number of bits of a word to be transmitted serially, and m is the parallel data input. The number of bits in one word of

P (X = n) = Becomes

So if P = 0.5 (P = 0.0001)

Average of P (X = n) = E [P (X = n)]

= 4.45e-3 (6.16e-5)

Maximum P (X = n) = 1.31e-2, n = 6 time (8.63e-4, n = 1)

Minimum of P (X = n) = 3.81e-6, n = 14hours (6.24e-44, n = 14)

P (X) = = 0.0623 (8.63 (8.63e-4)

The error probability when using single parity check coding is as follows.

P (X) =

If P = 0.5 then P (X) = 0.4999

If P = 0.001 P (X) = 1.38e-2

The chart below compares the error probabilities of one parity check code in the Cameron-Precode.

As shown in the table below, using Cameron-precode can significantly reduce the probability of error occurrence P (X).

In any communication system, maintenance of code asynchronous is very important.

In this way, you can have a special code symbol (one camemer) at the end of each codeword.

In order to effectively maintain word synchronization for this coder, a very small dictionary size B (n, k) can be defined as follows.

B (n, k)

μ (d) is the Mobis function As follows.

d / k: d divided by k divided by d

1 if d = 1

μ (d) = [0 of d is the square root

(-1) the product of ^r if d is the rth number

For B (2, 3)

if d = 1 (2 ³ ) (2 ³ -2) = 2

X when d = 2

if d = 3 (-1) 2 ^3/3 ∴B (2, 3) = 2

For B (2, 4) (d) 2 ^{4 / d}

if d = 1 (1.2 ⁴ ) (2 ⁴ -2 ² )

if d = 2 (1-1). ^{2 2} (16-4)

X = 3 if d = 3

If d = 4, X ∴B (2, 4) = 3

For B (2, 5) (d) 2 ^{5 / d}

if d = 1 (2 ⁵ -2 ¹ )

X when d = 2 (32-2)

X = 6 if d = 3

If d = 4, X ∴ B (2, 5) = 6

if d = 5 (-1) 2 ¹

For B (2, 6) (d) 2 ^{6 / d}

if d = 1 (1) 2 ⁶ (2 ⁶ -2 ³ -2 ² +2)

if d = 2 (1) 2 ³ (64-8-4 + 2)

if d = 3 (1) 2 ² = 9

If d = 4, X ∴ B (2, 6) = 9

X when d = 5

if d = 6 (-1) ² 2 ¹

For B (2, 7)

if d = 1 (1) 2 ⁷ (2 ⁷ -2)

X when d = 2 (128-2)

if d = 7 (1-) 2 = 18

∴B (2, 7) = 18

For B (2, 8) (d) 2 ^{8) d}

if d = 1 (1) 28 (2 ⁸ -2 ⁴ )

if d = 2 (-1) ¹ 2 ⁴ = (256-16)

X = 30 when d = 3

X when d = 4

X when d = 5

X when d = 6

X when d = 7

If d = 8 X 8 B (2, 8) = 30

For B (2, 9) (d) 2 ^{9 / d}

if d = 1 1 · ²⁹ (2 ⁹ -2 ³ ) = (512-8)

if d = 3 (-1) ¹ 2 ³ ∴B (2, 9) = 56

For B (2, 4) (d) 2 ^{14 / d}

if d = 1 1, 2 ¹⁰

if d = 2 (-1) 2 ⁵

if d = 5 (-1) 2 ²

if d = 10 (-1) 2 ²

∴ (2 ¹⁰ -2 ⁵ -2 ² +2)

(1024-32-4 + 2)

= 99 ∴B (2, 11) = 99

For B (2, 11) (d) 2 ¹¹ /

if d = 1 (1) 2 ¹¹ (2 ¹¹ -2)

if d = 11 (-1) 2 = 186

∴B (2, 11) = 186

For B (2, 12) (d) 2 ^{12 / d}

if d = 1 (1) 2 ¹² (2 ¹² -2 ⁶ -2 ⁴ +2 ² )

if d = 2 (-1) 2 ⁶ (4096-64-16 + 14)

if d = 3 (-1) 2 ⁸ = 335

if d = 6 (-1) ² 2 ² ∴B (2, 12) = 335

For B (2, 13) (d) 2 ^{13 / d}

if d = 1 (1) 2 ¹³ (2 ¹³ -2) = (8192-2)

if d = 13 -1) 2 = 630 ∴B (2, 13) = 630

For B (2, 14) (d) 2 ^{14 / d}

if d = 1 2 ¹⁴ (2 ¹⁴ -2 ⁷ -2 ² +2)

if d = 2 (-1) 2 ⁷ (16384-128-4 + 2)

if d = 7 (-1) 2 ²

if d = 14 (-1) ² 2 B (2, 4) = 1161

The maximum number of comma-free code words for 14 bits is 1161.

This is summarized in the table below.

In another embodiment of the present invention, it can be used for transmitting signals in all digital systems.

In other words, it can be used between HDVCR (High Definition VCR) and HDTV receiver from the receiver side, and can be used between D3 VTR and HDTV transmitter from the transmitter side.In case of serial transmission of signal from all digital systems such as HDTV transmitter to receiver Applicable.

As described above, the present invention has an error detection function and does not require a separate data marker when an important element is self-synchronizing during serial transmission, and hardware for configuring an apparatus is simple.

In addition, the frequency of the PLL control signal can be lowered compared to other channel coding, and edge insertion for PLL control is easy.

Claims (2)

A ROM 11 for commer-precoding input data according to a control signal of 171H (2.69 MHz), a serial converter 12 for converting the output signal of the ROM 11 in series, and the serial converter ( A line driver 13 for outputting the output signal of 12) to the receiver, a pulse shaping unit 14 for pulse shaping the output signal of the line driver 13, and a signal from the pulse shaping unit 14 in parallel PLL control based on the shift register section 15 for outputting the alternating output, the ROM 16 for kerma-precoding the signal of the shift register section 15, and the signals from the ROM 16 and the pulse shaping section 14; A PLL controller 17 for generating a signal and detecting an error, and a signal of 2.69 MHz and 37.66 MHz by receiving a signal from the PLOL controller 17 to produce a shift register unit 15, a ROM 16, and a PLL controller 17; Serial data transmission apparatus using a kerma-free code, characterized in that the output to. The apparatus of claim 1, wherein clock signals of 171H x 14 (37.66MHz) and 171H (2.69MHz) are applied to the serial converter (12).