KR940010431B1 - Direct level compensation circuit of adc - Google Patents

Abstract

The device compensates the error that occurs due to the change of DC level of an input analog signal. This device consists of a clamp unit which helps an input analog signal to have a constant DC level, an analog/digital conversion unit which converts an analog signal to a digital signal, a synchronizing separation unit which keeps the synchronized signal apart from the analog signal, a latch unit which temporarily restores the digital signal from the analog/digital unit, a comparator which determines the level of the compensation of the DC level, a DC level corrector.

Description

DC / DC level correction circuit of analog / digital converter

1 is a device diagram showing a general analog / digital converter.

2A, 2B and 1B are detailed circuit diagrams of a conventional DC level correction circuit in the apparatus diagram of FIG.

3A to 3C are waveform diagrams showing waveforms of respective parts in the circuit diagram of FIG.

4A and 4B are waveform diagrams showing input signals for explaining the DC level correction circuit of the analog / digital conversion device according to the present invention and corresponding digital code values during digital conversion;

5 is a block diagram according to an embodiment of a DC level correction circuit of an analog / digital conversion device according to the present invention.

6A to 6F are waveform diagrams showing waveforms of respective parts in the block diagram of FIG.

7 is a logic table for an operation mode of an up-down counter according to an output signal of a latch.

8 is an addressing diagram according to an area of a memory.

9A to 9F are waveform diagrams at each terminal of the up-down counter.

Disabling control timing diagram of 10a to 10d or up-down counter.

* Explanation of symbols for main parts of the drawings

11 amplification means 21 filter means

31 clamp means 41 analog / digital conversion means

51: digital signal processing means 61: synchronous separation means

71: clock generating means 72: multi-vibrator

81: latch means 91: memory means

101: comparison means 111: up-down counter

121: control means 131: enable signal generating means

EOR1: Exclusive OR gate AND1,2: AND gate

OR1: OR gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter in a digital signal processing system, and more particularly, to a DC level correction circuit of an analog / digital converter for compensating for an error caused by a change in the DC level of an applied analog signal.

In general, a digital signal processing system uses an analog / digital converter to convert an applied analog signal into a corresponding digital code to process the signal.

However, due to the uneven performance of the components constituting the analog / digital converter, the characteristic change due to the change of ambient temperature, and the aging over time, the analog / digital conversion characteristic is not stable and the overall characteristics of the system are reduced. Since the DC level of the analog signal is changed due to the instability of the clamp circuit among the components of the digital converter, an error occurs in the converted digital signal.

Accordingly, in order to solve the above problem, in the analog / digital converting apparatus shown in FIG. 1, it is conventionally disclosed in FIGS. 2A and 2B as disclosed in Japanese Patent Application Laid-Open No. 4-84569. As described above, the DC level correction circuit was configured to solve the problems caused by the instability of the clamp circuit.

In the case of configuring the DC level correction circuit in the analog manner as shown in FIG. 2A, when the analog signal of FIG. 3A is applied to the first amplifier AMP1, the signal value at time t0 is sampled by the sample & hold means 140. The sample & hold means of FIG. 3C is supplied to the sample & hold means 140, and the first comparator COM1 compares the output signal of the sample & hold means 140 with the clamp set voltage which is a reference signal. The output signal of COM1 is applied to the first amplifier AMP1 and amplified together with the applied analog signal to output an analog signal maintained at a constant DC level as shown in FIG. 3B. In this case, there is a problem that the sample & hold means 140 is complicated and expensive to be configured to have high speed and high precision performance.

When the DC level correction circuit is constructed in a digital manner as shown in FIG. 2B, the sample & hold means 140 of FIG. 2A is latched to 80, and the analog / digital conversion of the sample value at time t0 is performed. The digital signal is replaced with a digital value to generate an error compared to the reference value, and then converted into an analog signal and supplied to the second amplifier AMP2. In this case, the circuit is easily implemented and operates at high speed and high accuracy, but since an error value is applied to the second amplifier AMP2 through the digital / analog conversion 0 means 100, a high precision analog / digital conversion circuit must be used. There was a problem that the error of the digital conversion circuit itself can not be removed.

Accordingly, an object of the present invention is to determine the degree of DC level compensation by using a comparison means to control the operation mode of the counter by using a comparison means to solve the conventional problems as described above, the analog applied by using the memory means addressed by the counter The present invention provides a DC level correction circuit of an analog / digital converter for minimizing an error in a digital signal due to a change in the DC level of a signal.

In order to achieve the above object, the present invention provides a clamp means for maintaining the applied analog signal to a predetermined DC level, analog / digital conversion means for converting the analog signal output from the clamp means into a digital signal, A DC level correction circuit of an analog / digital conversion device having digital signal processing means for signal processing a digital signal converted from the analog signal; Synchronization separation means for separating the synchronization signal from the analog signal; Latch means for temporarily storing a digital signal output from the analog / digital conversion means by a clock signal generated by the synchronous separation means and a system clock; Comparison means for comparing the signal value output from the latch means with a predetermined reference signal value to determine the degree of compensation of the DC level; Memory means for storing correction data for the DC level of the digital code converted by the analog / digital conversion means, and outputting the output signal of the analog / digital conversion means as a read address of a first predetermined area; And address generating means for generating a read address of a second predetermined area of the data among the data stored in the memory means in accordance with a clock signal applied to the means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4A and 4B are waveform diagrams showing input waveforms and digital code values during digital conversion for explaining the DC level correction circuit of the analog / digital converter according to the present invention. FIG. 4B is a waveform diagram showing a digital code when the analog signal of FIG. 4A is converted into a digital signal.

5 is a block diagram according to an embodiment of a DC level correction circuit of an analog / digital conversion device according to the present invention.

The block diagram shown in FIG. 5 includes amplifying means 11 for amplifying an applied analog signal, filter means 21 for limiting a frequency band of the analog signal output from the amplifying means 11, and , Clamp means 31 for keeping the analog signal output from the filter means 21 at a constant DC level, and analog / digital conversion means 41 for converting the analog signal output from the clamp means 31 into a digital signal. ), And latch means 81 for temporarily storing the digital signal output from the analog / digital conversion means 41, and comparison means for comparing the digital signal value output from the latch means 81 with a predetermined reference signal value. 101, up-down with the latch means 81 by the synchronous separation means 61 for separating the synchronous signal from the applied analog signal, and the synchronous signal and the system clock signal output from the synchronous separation means 61; Count Clock generating means 71 for generating a clock for controlling the generator 111, a signal output from the synchronization separating means 61, an RCO signal of the up-down counter 111, and an output signal of the comparing means 101; The enable signal generating means 131 for generating the enable signal by means of the enable signal and the signal output from the enable signal generating means 131 is output from the terminal A of the enable terminal (EN), the comparison means 101 The signal is output from the up / down terminal (U / D), the clock generating means 71, the up-down counter 111 and the up-down counter 111 connected to the clock terminal CLK. Memory means 91 for storing the control means 121, a signal output from the up-down counter 111 and a signal output from the analog / digital conversion means 41, and an output from the memory means 91. And digital signal processing means (51) for signal processing.

In addition, the clock generating means 71 outputs a signal from the multi-vibrator 72 and a signal output from the multi-vibrator 72 and the synchronous separation means 61 as a signal output from the synchronous separation means 61. The first exclusive OR gate EOR1 for performing the exclusive OR logic on the signal output from the signal and the signal output from the synchronous separation means 61, and the system clock signal and the signal output from the first exclusive OR gate EOR1. The enable signal generating means 131 is outputted from the RCO terminal of the up-down counter 111 and the synchronization signal output from the synchronization separating means 61. A second AND gate AND2 for performing an AND logic on the signal to be output, and a signal for performing OR logic on the signal output from the B terminal of the comparing means 101 and the signal output from the second AND gate AND2. It consists of 1 OR gate OR1.

6A to 6F are waveform diagrams showing waveforms of respective parts in the block diagram of FIG. 5, FIG. 6A is a waveform diagram showing an analog signal to be applied, and FIG. 6B is a waveform diagram showing a synchronization signal separated from the analog signal of FIG. FIG. 6C is a waveform diagram showing a synchronization signal output from the multivibrator 72. FIG. 6D is a waveform diagram performing exclusive OR logic on the signal of FIG. 6B and the signal of FIG. 6C, and FIG. 6E is a system. FIG. 6F is a waveform diagram illustrating a clock signal. FIG. 6F is a waveform diagram of AND logic of the signal of FIG. 6E and the signal of FIG. 6E.

7 is a logic table for the operation mode of the up-down counter 111 according to the output signal of the latch means 81. In the comparison means 101, the output signal value of the latch means 81 is smaller than the reference signal value. In this case, the up-down counter 111 counts down, and when the output signal value of the latch means 81 is equal to the reference signal value, the up-down counter 111 is disabled, and the output of the latch means 81 is output. If the signal value is greater than the reference signal value, the up-down counter 111 counts up.

8 is an address designation diagram according to the area of the memory means 91, where the area of the memory is divided into 16 from 0 to 15. As shown in FIG.

9a to 9f are waveform diagrams showing waveforms of the respective terminals in the up-down counter 111. FIG. 9a is a waveform diagram for the least significant bit (QA) output, and FIG. 9b is a waveform diagram for the QB output. 9c is a waveform diagram of the QC output, FIG. 9d is a waveform diagram of the most significant bit (QD) output, and FIG. 9e is a waveform diagram of the signal output from the RCO terminal of the up-down counter 111. FIG. This is a waveform diagram of a signal output from the EN terminal of the up-down counter 111.

10A to 10D are timing diagrams for controlling the enable terminal of the up-down counter 111 using the RCO output and the synchronization signal of the up-down counter 111. FIG. 10b is a waveform diagram of the signal output from the RCO terminal of the up-down counter 111, and 10c is a waveform diagram of the output of the second AND gate AND2. FIG. 10D is a waveform diagram of the output of the tenth R gate OR1 when the output of the comparing means 101 is '0'.

The operation of the present invention will then be described in detail with reference to FIGS. 4, 5, 6, 7, 8, 9 and 10. FIG.

The amplifying means 11 amplifies to about 2Vp-p as shown in FIG. 4b when an analog signal of 1Vp-p is applied as in FIG. 4a.

The filter means 21 obtains a band necessary for analog / digital conversion from the analog signal amplified by the amplifying means 11 and filters to remove noise.

The clamp means 31 is for causing the signal output from the filter means 21 to have a DC level equal to the fourth degree when the analog / digital converting means 41 described later operates in the range of 0V to -2V. That is, the analog signal is in the black level and the white level is in the range of 0V to -2V, and the digital code value of the black level, which is the darkest level of the screen, corresponds to 16 ( _10H ), and the white level, which is the brightest level of the screen. The digital code value of corresponds to 235 (EB _H ).

The analog / digital converting means 41 converts the analog signal output from the clamp means 31 into a digital signal so as to output digital codes of 16 ( _10H ) to 235 (EB _H ) in accordance with the clock signal. At this time, when the clamping means 31 is unstable, each level of the signal as shown in FIG. 4B fluctuates up or down so that the corresponding digital code value is changed. That is, for example, the black level should be converted into 16 (10 _H ), but may be converted into 15 (OF _H ) or 17 (11 _H ) to generate an error.

The synchronizing separation means 61 is for controlling the up-down counter 111 to be described later according to every horizontal synchronizing signal outputted by separating the synchronizing signal from the applied analog signal as shown in FIG. 6b.

The clock generating means 71 includes a multivibrator 72 for widening the width of the synchronous signal output from the synchronous separation means 61, as shown in FIG. 6C, and a synchronous signal and the multivibrator 72 output from the synchronous separation means 61. The first exclusive OR gate EOR1 for outputting the same signal as the 6th degree by performing the exclusive OR logic on the signal outputted from the), the signal output from the first exclusive OR gate EOR1 and the system clock signal. As the first AND gate AND1 for performing the AND logic to output the same signal as the fifth level, the clock signal for controlling the latch 81 and the up-down counter 111 described later is generated.

The latch means 81 is for latching the digital signal output from the analog / digital converting means 41 by using the signal output from the first AND gate AND1 as the latch signal. That is, the converted black level digital code is latched as many times as the number of clocks in FIG. 6f.

The comparison means 101 is for comparing the digital code value latched by the latch means 81 with the reference signal value. In the case of checking whether the converted black level is 16 ( _10H ), the operation relationship of the comparison means 101 is the same as that of the seventh degree. That is, when the output value of the latch means 81 is smaller than the reference signal value, the up-down counter 111 connected to the next stage is controlled in the down count mode so that the output of the up-down counter 111 decreases according to the clock. If the output value of the latch means 81 is larger than the reference signal value, the up-down counter 111 is controlled in the up count mode so that the output of the up-down counter 111 increases with the clock. If the output value of (81) is equal to or larger than the reference signal value, the digital code value of the converted black level is the reference signal value, that is, 16 ( _10H ), so that the state of the up-down counter 111 is maintained without being operated. Enable it.

The memory means 91 is assigned an upper address by the output signal of the up-down counter 111 and the lower address is designated by the output signal of the analog / digital conversion means 41. An example of the digital code storage of the memory means 91 is the same as that of the eighth figure, where the area of the memory means 91 is divided into 16 of 0 to 15, and the digital code in a steady state is stored in the middle region 7. The areas 8 to 15 are areas used when the DC level of the analog signal applied to the analog / digital converting means 41 rises above the normal level so that the analog / digital converted digital code value is large. In this case, the area used to increase the difference in DC level is the area 15. The regions 6 to 0 are conversely used when the DC level of the analog signal applied to the analog / digital converting means 41 is lower than the normal level so that the analog / digital converted digital code value is smaller. Here, the larger the difference between the DC levels is, the more the area to be used becomes the area 0 side.

Referring to the address of each region of FIG. 8, the upper 4 bits designate each region and the lower 8 bits designate 256 addresses in one region. Accordingly, the analog / digital converting means 41 specifies 256 addresses to output the stored digital codes, and the output of the up-down counter 111 designates one region. That is, the compensating degree according to the difference of the DC level is determined by the comparing means 101, and the area designation accordingly is performed by the up-down counter 111. At this time, the latch means 81 latches the digital code, the compare means 101 compares the latched digital code, and the number of times that the up-down counter 111 operates is performed every line of the analog signal as shown in FIG. The number of clocks from the end of the horizontal synchronization signal until the actual analog signal is output.

The up-down counter 111 sets its initial value to 7 and the load signal is supplied from the control unit 121 when the system is first turned on as a one-shot pulse. . When the up-down counter 111 increases or decreases in the up or down direction and reaches the maximum or minimum value of the up-down counter 111, an RCO signal, which is a carry signal, is generated to generate the second AND gate AND2 and the tenth R gate. It is arranged to disable the up-down counter 111 through OR1 and the timing is the same as the tenth degree. In the example shown in FIG. 10, when the up-down counter 111 increases in the up direction and reaches a maximum value, the up-down counter is disabled until the next synchronization signal is generated, and the synchronization signal is This is the case after enabling.

As described above, in the DC level correction circuit of the analog / digital converter according to the present invention, the DC level compensation degree is determined using a comparison means to control the operation mode of the counter, and the correction data for the memory means addressed by the counter. By reading and processing the digital signal, there is an advantage that the DC signal of the analog signal applied to the analog / digital conversion unit is correctly corrected and high-speed processing is possible. In addition, the circuit is easy to implement, and in the analog type circuit, the present invention does not require adjustment and can be realized at low cost, compared to using a variable means such as a resistor.

Claims (4)

Clamp means for keeping the applied analog signal at a predetermined straightness level, analog / digital conversion means for converting the analog signal output from the clamp means into a digital signal, and a digital signal converted from the analog signal A DC level correction circuit of an analog / digital conversion device having digital signal processing means for processing, comprising: Synchronization separation means for separating the synchronization signal from the analog signal; Latch means for temporarily storing a digital signal output from the analog / digital conversion means by a clock signal generated by the synchronous separation means and a system clock; Comparison means for comparing the signal value output from the latch means with a predetermined reference signal value to determine the degree of compensation of the DC level; Memory means for storing correction data for the DC level of the digital code converted by the analog / digital conversion means, and outputting the output signal of the analog / digital conversion means as a read address of a first predetermined area; A DC level of the analog / digital converting apparatus, comprising: address generating means for generating a read address of a second predetermined area of the data among the data stored in the memory means in accordance with a clock signal applied to the means; Correction circuit. The method of claim 1, further comprising: clock generation means for generating a clock signal for controlling the latch means and the address generation means by a signal output from the synchronization separation means and a system clock signal; DC level correction circuit of digital converter. 3. The DC level correction circuit as set forth in claim 2, wherein said address generating means comprises a counter. 4. The analog / digital converting apparatus according to claim 3, wherein the counter is enabled by an enable signal generating means composed of a plurality of logic gates as a signal input from the synchronous separation means and the comparison means. DC level correction circuit.