KR940010203B1 - Tv pointer processor of digital synchronous transmission system - Google Patents

Abstract

The system provides TU pointer processor which is used to generate, interpret and execute TU1 pointer of low-speed multiprocessor in the synchronous multiplexer of digital synchronous transmission system. The processor consists of a pointer generator (100) for producing pointer value and pointer word and detecting the phase of VC1 offset signal, a BLC controller (230) for controlling bitleaking and outputting data clock to improve jitter efficiency, a pointer interpreter (200) for deciding and sending pointer status to CPU.

Description

TU Pointer Handler in Digital Synchronous Transmission System

1 is a structural diagram of a TU frame.

2 is a structural diagram of a pointer word.

3 is a TU multiplexing scheme.

4 is a block diagram of a TU pointer processor according to the present invention.

5 is a timing diagram for the present invention.

6 is an application example of the present invention.

7 is a block diagram of a pointer generator of FIG.

8 is a block diagram of a pointer value generator / monitor of FIG.

9 is a block diagram of a BLC controller of FIG.

10 is a block diagram of a pointer analyzer of FIG.

* Explanation of symbols for the main parts of the drawings

100: pointer generator 110: transmission timing generator

120: TU data generator 130: P / S converter

200: pointer interpreter 210: reception timing generator

220: frame offset generator 230: BLC controller

240: S / P converter 300: loopback controller

310: register circuit 320: CPU interface

The present invention relates to a TU pointer processor that realizes generation, interpretation of a pointer, and processing of a Tributary Unit-1 (TU1) pointer among low speed multiplexing units applied to a synchronous multiplexer of a digital synchronous transmission system.

In synchronous signal transmission, the DS1 signal is once formed as a VC1 (Virtual Container-1) signal and then multiplexed into a TUG2 signal with a TU1 pointer. In this case, the TU1 pointer designates the position of the first byte (V5) of the VC1 payload data in the TU1 frame. That is, since the VC1 frame offset information is included, the VC1 data can be flexibly arranged and synchronized in the TU1 frame using the TU1 pointer.

An object of the present invention is a TU11 pointer to VC11 data containing a 1.544 Mb / s DS1 signal and a corresponding path overhead (POH), or a VC12 containing a 2.048 Mb / s DS1 signal and a corresponding path overhead (POH). It provides a TU pointer interpreter for generating, interpreting and processing TU12 pointers to data.

In order to achieve the above object, the present invention provides an 8-bit data, 5-bit address, chip select signal, and read / write signal from a central processing unit (CPU) in a TU pointer processor of a digital synchronous transmission system. CPU interface means for receiving and decoding to supply control information, reporting status information to the CPU, and generating and releasing an interrupt request signal when an alarm condition occurs, and is connected to the CPU interface means to store control information by receiving information from the CPU interface means. Register means for supplying to the necessary parts and sending the state information collected from each part to the CPU interface means, receiving an 8KHz frame signal and a 12.096 MHz transmit TUG clock from the outside, and being connected to the register means to receive a TU mode control signal. Transmission timing generating means for receiving and forming and supplying an associated transmission timing clock; It is connected to the jitter means and the transmission timing generating means to generate a 10-bit pointer value from the transmission VC1 frame offset signal and the timing clock, and receives the control signal from the register means to generate 4 bits of NDF and 2 bits of SS bit. Generate a 16-bit pointer word to monitor the phase of the VC1 frame offset signal, and detect an increase or decrease in the transmission pointer adjustment state, and invert the odd 5-bits of the pointer value during fine adjustment and the even value of the pointer value during sub-adjustment. Pointer generation means for inverting 5 bits, and connected to the register means, the transmission timing generation means and the pointer generation means to receive control signals from the register means for 8-bit parallel VC1 data and 16-bit pointer words. TU data forming means for inserting at the position to form TU data, wherein P / S conversion means connected to transmission timing generating means and TU data forming means for converting 8-bit parallel TU data into serial TUG data according to the TUG timing clock, and connected to the P / S conversion means to transmit TUG data and receive TUG. Loopback control means capable of receiving data and looping back data; reception timing generating means connected to the register means to receive an 8KHz frame clock and a 12.096MHz reception clock and a control signal to form a necessary reception timing clock, the loopback control means and reception S / P conversion means connected to the timing generating means for converting the received TUG data into 8-bit parallel TU data according to the received TU timing clock signal, and 8 bit connected to the S / P conversion means, the register means and the receiving timing generating means. The pointer is interpreted using the received timing clock signal from the parallel TU data and used on the pointers such as AIS and LOP. A pointer analyzing means for generating a pointer adjustment state and an interpreting pointer value, and transmitting a status signal to said register means, from said interpreted pointer value and receiving timing clock signal connected to said pointer analyzing means and receiving timing generating means; Frame offset generation means for generating frame offset, and pointer adjustment occurs when the frame adjustment signal is delayed by one clock in the case of positive adjustment and by one clock in case of negative adjustment, and pointer adjustment is connected to the pointer analysis means, the reception timing generating means, and the register means. Bit-leaking control that receives the status signal from the pointer analysis means and uses the pointer clock and timing clock signals to improve jitter performance by distributing the change in the byte unit to the change in the bit unit when the pointer adjustment state occurs by itself or according to the control signal. Outputs the resulting data clock Which it is characterized in that it comprises a control means BLC.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a structural diagram of a TU frame, FIG. 2 is a structural diagram of a pointer word PW, and FIG. 3 is a TU multiplexing diagram.

The frames of the multiframed TU11 and TU12 have the structure as shown in FIG. 1, B0 to B103 represent VC11 data and B0 to B139 represent VC12 data, respectively, and the overhead for the TU pointer is V1 to V4. Bytes.

The V1 and V2 bytes are used as pointer words PW, and V3 bytes are reserved for pointer adjustment, and V4 bytes are reserved. If the pointer adjustment occurs, the V3 byte is filled with the VC1 data in the case of sub-adjustment, and the V3 byte is left empty and the data immediately after the V3 byte (B26, B35) is discarded.

As shown in FIG. 2, the pointer word PW has a structure consisting of a 4-bit NDF (New Data Flag) bit, a 2-bit Current Service State (SS) bit, and a 10-bit pointer value PV.

The principle in which TU11 and TU12 data are multiplexed into a TUG21 signal is shown in FIG.

4 is a configuration diagram of the TU pointer processor according to the present invention, and as shown in the drawing, the pointer generator 100, the transmission timing generator 110, the TU data generator 120, the P / S converter 130, and the pointer interpreter ( 200, the reception timing generator 210, the frame offset generator 220, the BLC controller 230, the S / P converter 240, the loopback controller 300, the register circuit 310, and the CPU interface 320. Shows equipping.

The operation of the TU pointer processor configured as described above will be described with reference to FIGS. 4 and 5.

The pointer generator 100 receives a 2KHz VC1 frame offset signal 2 from the outside and pointers according to a pointer clock 14 of 280KHz (for TU12) or 208KHz (for TU11) formed in the transmission timing generator 110. A value PV is generated, and an NDF bit and an SS bit are generated according to the control signal 17 of the register to form and output a 16-bit pointer word 13.

If the phase change occurs by continuously monitoring the timing of the VC1 frame offset, if the change is one clock ahead, the phase of the VC1 data frame is faster than that of the TU1 frame, and thus the positive pointer adjustment is required. Inverting the odd 5 bits, and the change is 1 clock behind, since the phase of the TU1 data frame is slower than that of the TU1 frame, sub-point adjustment is required. In this case, the even 5 bits of the pointer value PV are inverted.

In order to diagnose the function of the pointer generator 100, a dual 10-bit PV generation / monitoring unit, which is an internal main circuit, is compared to monitor two circuit states by comparing two states, and the result is transferred to a register through a state signal 17. Pass it to the CPU via the CPU interface 320 as an alarm.

The transmission timing generator 110 receives an 8 KHz frame signal 3 and a 12.096 MHz transmit TUG clock 4 from which an overhead (V1-V4) is omitted from the 12.538 MHz clock, and then to the register circuit 301 described later. 280KHz (for TU12) or 208KHz (for TU11) Pointer Clock (14), TU Data Clock (15), TU Data Serial Clock with V1-V4 byte part, which is pointer overhead, received from TU mode control signal (16) Generates and outputs a 864 KHz transmit TUG clock (5), 288 KHz (for TU12) or 216 KHz (for TU11) transmit TU clock (6).

The externally input 8-bit parallel VC1 data 1 is a TU data clock output from the transmission timing generator 110 at the TU data generator 120 together with a pointer word (PW) 13 formed at the pointer generator 100. It is formed of TU11 or TU12 data by (15) and output as 8-bit parallel data 18. If necessary, the contents of the pointer word PW may be controlled by the control signal 19 of the register circuit 310.

TU parallel data 18 output from the TU data generator 120 having a multiplexer is input to the P / S converter 130 and output from the transmission timing generator 110. Is converted into a serial signal 20 at a speed of 12.096 Mb / s and output.

The serially changed signal 20 is output as output data 25 through the loopback controller 300. The serial signal 20 entering the loopback controller 300 may receive the control signal 24 of the register circuit 310 and loop back to the received data 27. At this time, all the output data 25 is inserted and outputted by "1". In addition, the input data 26 can be looped back to the output data 25 by the control signal 24 of the register circuit 310. In this case, all of the received data 27 inserts "1".

The input data 26 of 12.096 Mb / s rate input from the outside becomes the received data 27 of the S / P converter 240 through the loopback controller 300. The S / P converter 240 outputs 12.096 Mb / s received data 27 as 864 Kb / s8 bit parallel TU data 7 according to the received clock 28 supplied from the reception timing generator 210.

The reception timing generator 210 receives an 8 MHz frame clock 34 and a 12.096 MHz reception clock 35 from the outside, and receives a reception pointer word clock 31, a reception pointer clock 32, and an 8 KHz reception pointer timing clock for BLC. 11) and frame timing clock 33, receive 864KHz TUG clock 37, receive 288KHz or 216KHz clock 38.

In the pointer analysis 200, a pointer word is extracted from the TU data 7 output from the S / P converter 240 to detect states of NDF bits, SS bits, and PV. Alarm indication signal (AIS) with 3 "consecutive 1" states, Loss of Pointer (LOP) state with 8 or more frames of invalid state pointer value, and 3 with normal pointer value (PV) A pointer state such as a frame consecutive NORM (normal) state is determined, and the result is transmitted to the CPU through the register circuit 310. In particular, the AIS and LOP states are treated as alarms and output directly to external signals (8, 9).

When the pointer adjustment state is detected as a result of analyzing the pointer word PW, the adjustment state signal 30 is transmitted to the frame offset generator 220 and the BLC controller 230. In addition, the pointer value (PV) 29 determined as a normal value is transmitted to the frame offset generator 220. All pointer states detected and determined by the pointer interpreter 200 are supplied to the register circuit 310 as a status signal 23, which can be read by the CPU if necessary through the CPU interface circuit 320. .

The frame offset generator 220 receives the normal pointer value PV extracted by the pointer analyzer 200 and receives the frame offset timing signal 10 of the VC1 by the pointer clock 32 received by the reception timing generator 210. Extract and print In the pointer analyzer 200, when the pointer analysis results in pointer adjustment, the pointer analyzer 200 receives the adjustment signal 30 and reflects it to the frame offset timing signal 10. In this case, in the case of positive adjustment, the phase of the frame offset timing signal 10 is delayed by one clock, and in the case of subordination, the phase of the frame offset timing signal 10 is advanced by one clock.

When pointer adjustment occurs, the frame timing clock 33 of the reception timing generator 210 adjusts the increment or decrement by one byte. Since the clock change in units of 1 byte increases the amount of jitter in the received data, which degrades the performance, it is necessary to disperse the change in units of 1 bit or less (1/8 bit) for a certain period.

To this end, the BLC controller 230 is a 2KHz frame timing clock 33 and an 8KHz reception pointer timing clock 11 and a pointer adjustment signal 30 from the pointer analyzer 200 input from the reception timing generator 210. And bit-leaking control (BLC) according to the control signal 36 inputted from the register circuit 310, resulting in a timing clock of 4.480 MHz (for TU12) or 3.328 MHz (for TU11). ) The BLC controller 230 generates a 17.92 MHz (TU12) or 13.312 MHz (TU11) clock in synchronization with the 8 KHz reception pointer timing clock 11 input from the reception timing generator 210 using a PLL. It is used for performance. The pointer 12 may occur and the clock 12 processed by the BLC controller 230 may be used as a read clock when the received VC1 data is extracted.

The signal 22 exchanged with the external CPU through the CPU interface circuit 320 is composed of 8-bit parallel data, 6-bit address signal, chip select signal, R / W (Read / Write) signal, and interrupt request signal. Using this, it creates internal register selection signal required by address decoder, makes interrupt request signal to deliver alarm signal such as AIS and LOP to CPU, and separates input and output data for signal transfer between CPU data bus and register. Supply.

The register circuit 310 supplies the control signal of the CPU to the internal circuit through the signal 21 connection with the CPU interface circuit 320 and supplies the state of the internal circuit and the pointer analysis state to the CPU. For this purpose, control registers, status registers, and interrupt registers are provided.

The control register stores the control data of the CPU and supplies it to the necessary circuit part. That is, the TU mode decision such as TU11 / TU12 and the control signal 17 for NDF set are supplied to the pointer generator 100, and the contents of the transmission pointer word 13 output from the pointer generator 100 are controlled. The control signal 19 is supplied to the TU former 120, and the control signal 40 for transmission and reception timing control is supplied to the transmission timing generator 110 and the reception timing generator 210. The control signal 36 for the BLC controller operation and the control signal 24 for the loopback control are supplied to the BLC controller 230 and the loopback controller 300.

The status register receives the state 17 of the internal circuit and the pointer interpretation state 23 from the pointer generator 100 and the pointer interpreter 200 so that the CPU can read them through the CPU interface circuit 320 if necessary. do. In addition, an interrupt request signal is issued to the alarm generator CPU and the CPU can access the relevant register to read the status, and at the same time, the interrupt request signal is released.

6 is an application state diagram of the present invention, 400 denotes a TU pointer processor, 410 denotes a TUG21 MUX (Multiplexer), 420 denotes a transmit FIFO (First In First Out), 430 denotes a receive FIFO, and 440 denotes a TUG21 Demultiplexer (DMUX). .

An example of the operation of the TU pointer processor according to the present invention is shown in FIG. 6, and the detailed operation thereof is as follows.

Three transmit VC12 data are written by each transmit FIFO 420 and read by a 288 KHz data clock 6 coming from the TU pointer processor 400. The read data is multiplexed into the TUG21 data (1) by the 864KHz transmit TUG clock (5) received from the TU pointer processor (400) in each transmit FIFO in the TUG21 MUX (410) and input to the TUG pointer processor (400). do. In addition, not only the VC12 data but also the 2KHz VC12 frame signal 2 is read from the transmission FIFO, which is directly input to the TU pointer processor 400.

In the above reverse process, the 864Kb / s TUG21 output data 7 and the 864KHz TUG21 clock 37 outputted from the TU pointer processor 400 are demultiplexed into three VC12 data in the TUG21 MUX 440 and receive FIFO ( 430 writes the demultiplexed VC12 data and the frame signal 10 to the 288 KHz receive clock 28 received from the TU pointer processor 400 and receives the VC12 data received by the read clock 12 received from the VC pointer processor 400. Is read and printed.

7 is a configuration diagram of the pointer generator 100 of FIG. 4, and FIG. 8 is a configuration diagram of the pointer value generator / monitor 610 of FIG. 7, and in FIG. 7, 610 is a pointer value generator / monitor 620. Is a flag generator, 630 is a pointer byte 1 insertion unit, 640 is a pointer byte 2 insertion unit, 650 is a pointer word transfer circuit, 660 is a 10-bit counter, 670 is an effective range monitoring unit, 680, 690 is a latch circuit, 700 Denotes a bit inversion unit, and 710 denotes a PV comparator.

The pointer generator 100 has been patented (patent application 90-22788) by the same applicant, and as shown in FIG. 7, the sub clock signal CK2, the count start timing signal ST1, and the subframe offset are shown. A timing signal ST2 is input and connected to a pointer value generator / monitor 610 for outputting a pointer value and a monitoring signal, the pointer value generator / monitor 610, and an offset timing signal ST2 to control and control the signal. The flag generator 620 for generating a 4-bit flag by the timing signal, and the pointer byte 1 inserting unit 630 for receiving the flag and SS data and the pointer value and inserting the flag according to the pointer byte 1 timing signal PT1. ), The pointer byte 2 inserting unit 640 for inserting the pointer value according to the pointer byte 2 timing signal PT2, the pointer byte 1 and the pointer byte 2 as the pointer word are transmitted in accordance with the main clock signal CK1, and the alarm display. My The pointer word transmitter 650 transmits a signal to the pointer word upon receiving the word signal.

As illustrated in FIG. 8, the pointer value generating / monitoring unit 610 includes a 10-bit counter 660 and a 10-bit counter 660 to which a sub clock signal CK2 and a count start timing signal ST1 are input. The effective range monitoring means 670 for judging whether the output value is in the effective range and outputting the monitoring output signal 1, and a latch circuit for storing the output value of the 10-bit counter 660 by the subframe offset timing signal ST2 ( 680, a pointer value for comparing the output values of the latch circuit 680 and the latch circuits 680 and 690 to store the output value of the latch circuit 680 by the subframe offset timing signal ST2 and outputting the output value as the supervisory output signal 2. And a bit inverting unit 700 connected to the comparator 710, an output terminal of the latch circuit 680, and an output terminal of the pointer value comparator 710 to invert bits to output a pointer value.

9 is a block diagram of the BLC controller 230. As shown in the drawing, a bit leaking interval generator 810, a delay unit 820, a bit leaking interval selector 830, and a bit leaking interval counter 840 are shown. ), A bit-leak request signal counter 850, a stuffing and burst detector 860, and a main counter 870.

The BLC controller 230 has been patented by the applicant (patent application 91-19365), and in the drawing, the bit leaking interval generator 810 is composed of a counter and a logic circuit to generate an interval to be bit leaked. It performs the function. That is, the frame clock (clock V3 at TU1) is continuously counted until a stuffing request is generated.

Since the coefficient must be pulled or pushed 64 times in 1 / 8-bit increments using the same period divided by 64, the up-counting coefficient until the stuffing request occurs using the frame clock. The maximum measuring interval is 2 ²⁰ × 500㎲ee. The output value of the counter is reset every time stuffing occurs and the count value obtained by the bit leaking interval generator 810 is supplied to the bit leaking interval selector 830.

The bit leaking interval selector 830 determines the bit leaking interval from the value calculated by the bit leaking interval generator 810 or the pointer stuffing request frequency to select one of all values in software, and determines the external (CPU I / F) It consists of a simple logic circuit that selects and outputs an input according to the selection signal.

The bit leaking interval counter 840 receives the bit leaking interval value from the bit leaking interval selector 830 and counts the bit leaking request signal. It consists of a counter and a logic circuit whose operation is performed by counting start and end signals of the stuffing and burst detector 860. If a stuffing request does not occur, the bit leaking interval counter 840 does not operate. However, when stuffing is requested, the bit leaking interval counter value is received from the bit leaking interval selector 830 and temporarily stored, and provided by the delay unit 820. The down coefficient is started by the delay clock synchronized with the delay clock synchronized with the frame clock. When this count value is " 0 ", a bit leaking request signal is generated, and the stored bit leaking interval count value is read and counted again. The bit leaking interval counter 840 continues to count until the end signal comes from the stuffing and burst detector 860. The stuffing and burst detector 860 has a function of generating counting start and end signals, +/- signal signals, and detecting homogeneous and heterogeneous bursts.

The bit leaking request signal counter 850 completes bit leaking by inputting the burst information and the bit leaking request signal output from the stuffing and burst detection circuit 860 and the bit leaking interval counter 840. Detecting and outputting the leaking completion signal and the carry signal (Cn + 1) to the stuffing and burst detection circuit 860.

The main counter 870 generates a clock divided by 3-5 using a bit leaking request signal and a +/- code signal, and receives a BLC clock (17.920 MHz for TU12 and TU11). 13.312MHz) outputs 4 division clocks when there is no bit leaking request signal.

However, if there is a bit leaking request signal, the division ratio is determined according to the +/- sign supplied from the stuffing and burst detection circuit 860, and when a + sign signal is generated, a clock divided by 5 is output to push 1 bit. When bit-leaking is performed, and -signal signal is input, bit-leaking is performed to pull 1/8 bit by performing three-division according to the leaking request signal. The main counter 870 is composed of a D-type flip-flop and a logic circuit.

10 is a configuration diagram of the pointer analyzer 200 of FIG. 4, wherein the pointer analyzer includes a pointer state detector 910, a pointer state comparator 920, and a pointer state determiner 930 as shown in FIG. 9. , The pointer adjustment determining unit 940, the alarm generating unit 950, and the sub-signal start position generating unit 960 are provided.

The pointer state detection unit 910 detects whether an NDF has occurred in the input pointer, whether the shape of the acknowledgment sub-signal of the SS is satisfied, whether the pointer value of 10 bits is within the allowable range, and whether the AIS state is present.

The pointer state comparison unit 920 receives a pointer according to the pointer latch clock, compares the pointer for two frames, and compares whether the I or D bits are inverted and whether the same pointer is input for three frames.

The pointer state determination unit 930 is classified into a state of a current pointer, that is, a normal state, an abnormal state, and an NDF generation state according to a result detected / compared by the pointer state detection unit 910 and the pointer state comparison unit 920, To judge.

Here, the normal state is when the NDF (New Data Flag), SS (Current Service State), and PV (Point Value) are all normal. The NDF generation state is when the NDF is set and the SS and PV are normal. The abnormal state is neither a normal state, an NDF occurrence state, a pointer adjustment state (PJESET), or an AIS occurrence state.

In other words,

Steady state = NDFNORM * SSNORM * PVNORM

NDF Occurrence Status = NDFSET * SSNORM * PVNORM

Abnormal State = Pointer Adjustment Status

to be.

The pointer adjustment determining unit 940 determines whether pointer adjustment has occurred according to the results of the pointer latch clock, the pointer state comparison unit 920, and the pointer state detection unit 910, and when there is pointer adjustment, a corresponding increase or decrease adjustment signal. Occurs.

The pointer increase occurs when the NDF and SS are normal, the I (Increment) bit is inverted but the D (Decrement) bit is not inverted, and the NDF or the pointer adjustment operation has not occurred during the previous three frames. In addition, pointer reduction occurs when the NDF and SS are normal, the D bit is inverted, but the I bit is not inverted, and no NDF or pointer adjustment operation occurs during the previous three frames.

The alarm generator 950 receives the output of the pointer latch clock, the pointer state detector 910, the pointer state comparator 920, and the pointer state determiner 930, and receives an alarm indication signal (AIS) and a LOS (Loss). Of Signal) state is determined and information is issued.

The sub-signal start position generator 960 generates and outputs a clock signal indicating a start position of a sub-signal from a received pointer value by inputting an input pointer, a pointer latch clock, and an output value of the pointer adjustment decision unit 940. do.

Accordingly, the present invention configured and operated as described above allows the VC1 data phase within the TU frame by receiving the offset and the data clock according to the VC11 or VC12 data, generating a pointer, and inserting the TU frame into the TU pointer word position. By extracting and interpreting a TU11 or TU12 pointer from the VCG21 data, the state of the pointer and the VC1 frame offset timing can be known and the position of the VC1 data can be confirmed therefrom. In particular, when pointer adjustment occurs in the receiving pointer, there is an application effect to improve the jitter performance of the data clock used for extracting the received data by distributing the change in the byte unit by the bit. There is an application effect that can be transmitted.

Claims (4)

In the TU pointer processor of the digital synchronous transmission system; Receives and decodes 8-bit data, 5-bit address, chip select signal, and R / W (Read / Write) signal from CPU (Central Processing Unit), supplies control information 21, reports status information to CPU, and generates alarm state. CPU interface means 320 for generating and releasing an interrupt request signal, connected to the CPU interface means 320, receives information 21 from the CPU interface means 320, stores control information, and supplies it to the required portion. Register means 310 for sending the state information collected in the portion to the CPU interface means 320, an 8KHz frame signal 3 and a 12.096 MHz transmit TUG clock 4 are received from the outside, and the register means 310 is received. Transmission timing generating means 110, the register means 310, and transmission timing generating means which are connected to receive the TU mode control signal 40 to form and supply the related transmission timing clocks 5, 6, 14, 15, and 16; (110 4 bits NDF and 2 bits SS are generated by generating a 10-bit pointer value from the transmission VC1 frame offset signal 2 and the timing clock 14 and receiving the control signal 17 from the register means 310. Generates a 16-bit pointer word 13 to monitor the phase of the VC1 frame offset signal 2 to detect a change in the increase or decrease as a transmission pointer adjustment state. 8-bit parallel VC1 connected to the pointer generating means 100, the register means 310, the transmission timing generating means 110, and the pointer generating means 100 for inverting bits and inverting even five bits of the pointer value during sub-adjustment. TU data type in which the data 1 and the 16-bit pointer word are inserted under the control of the control signal 19 from the register means 310 at the timing clock signal 15 to form the TU data 18. Means 120, connected to the transmit timing generating means 110 and the TU data forming means 120 to convert 8-bit parallel TU data 18 into serial TUG data 20 according to the TUG timing clock 16. A loopback control means 300 connected to the P / S converting means 130 and the P / S converting means 130 so as to receive the transmit TUG data 25 and the receive TUG data 26 and loop back the data; Receive timing generating means connected to the register means 310 to receive the 8 KHz frame clock 34, the 12.096 MHz receive clock 35, and the control signal 40 to form the necessary receive timing clocks 28, 31, 32, and 33. S / P connected to the loopback control means 300 and the reception timing generating means 210 to convert the received data 27 into 8-bit parallel TU data 7 according to the received clock signal 28. 8-bit parallel T connected to the conversion means 240, the S / P conversion means 240, the register means 310, and the reception timing generating means 210. The pointer is interpreted using the received timing clock signal 31 from the U data 7 to generate the pointer states such as the AIS 8 and the LOP 9, the pointer adjustment state 30, and the analysis pointer value 29. And a pointer value 29 which is connected to the pointer analyzing means 200 for transmitting the status signal 23 to the register means 310, the pointer analyzing means 200, and the reception timing generating means 210. A frame offset generating means 220 which generates a VC1 frame offset 10 from the reception timing clock signal 32 and delays the frame offset signal 10 by one clock in the case of positive adjustment and one clock in the negative case when the pointer adjustment occurs. And a 8KHz receiving pointer timing clock 11 connected to the pointer analyzing means 200, the receiving timing generating means 210, and the register means 310 to receive a pointer adjustment state signal 30 from the pointer analyzing means 200. Using Frame Timing Clock 33 BLC control that outputs the result data clock 12 after performing bit-leaking control to improve jitter performance by distributing the change in bytes by the change in bits in the pointer adjustment state according to the control signal 36 or the control signal 36. Means (230) comprising means (230). The pointer generating means (100) according to claim 1, wherein the pointer generating means (100) receives a sub clock signal (CK2), a counter start timing signal (ST1), and a subframe offset timing signal (ST2), and outputs a pointer value and a monitoring signal. Frag generation means 620, which is connected to the generation / monitoring means 610, the pointer value generation / monitoring means 610, and the offset timing signal ST2 and generates a 4-bit flag by the control signal and the control timing signal. ), A pointer byte insertion means 630 for receiving a flag, SS data and a pointer value and inserting the pointer value according to the pointer byte 1 timing signal PT1, and a pointer for inserting the pointer value according to the pointer byte 2 timing signal PT2. A pointer for transmitting the signal to the pointer word when the byte 2 inserting means 640, the pointer byte 1, and the pointer byte 2 are used as the pointer word, and are transmitted in accordance with the main clock signal CK1. TU pointer processor comprising: a word-transmitting means 650. 2. The apparatus of claim 1, wherein the BLC control means (230) is connected to the bit leaking interval generating means (810) and the bit leaking interval generating means (810) for generating a price to be bit leaked by receiving a frame clock. Bit leaking interval selecting means 830 for determining a bit leaking interval, delay means 820 for receiving a frame clock as an input and generating a delay clock synchronized with the frame clock, and the bit leaking interval selecting means 830. And a bit leaking interval counting means 840 connected to the delay means 820 to receive and count a bit leaking interval value and a delay clock to generate a bit leaking request signal, and burst information and bit leaking interval counting means ( Bit-leaking request signal counting means 850 for detecting the completion of bit-leaking by inputting the bit-leaking request signal output from 840 and outputting the leaking completion signal and the open signal (Cn + 1), and stuffing information. Receiving the input, the number of bit leaking interval Supplying the counting start and end signals to the stage 840 to control the bit leaking interval means 840, detect heterogeneous and homogeneous bursts, and output burst information to the bit leaking request signal counting means 850, Stuffing and burst detection means 860 for outputting a +/- code signal, and connected to the stuffing and burst detection means 860 and the bit leaking interval counting means 840 using an upper clock, A main counting means 870 for receiving a +/- code signal provided from the burst detecting means 860 and a bit leaking request signal provided from the bit leaking interval counting means 840 and outputting a divided clock; TU pointer processor, characterized in that. The method of claim 1, wherein the pointer analyzing means 200 determines whether the NDF is generated from the input pointer, whether the shape of the accommodating signal of the SS is satisfied, whether the pointer value of 10 bits is within the allowable range, and whether the AIS state is present. Pointer state detection means for detecting a (910), the pointer is received according to the pointer latch clock to compare the pointer for two frames and the pointer state comparison to compare the inversion of the I or D bit and the input of the same pointer for three frames A pointer state determination means 930 for determining a state of a current pointer based on a result detected / compare by the means 920, the pointer state detection means 910, and the pointer state comparison means 920; The pointer state comparison means 920 and the pointer state determination means 930 determine whether pointer adjustment has occurred, and when the pointer adjustment is made, Control input means 940, the pointer latch clock and the output of the pointer state detection means 910, pointer state comparison means 920 and pointer state determination means 930, and receives the Alarm Indication Signal (AIS) and LOS The alarm generating means 950 for determining the state of the Loss of Signal and informing the information, and the input value of the pointer and the pointer latch clock and the pointer adjustment determining means 940 as inputs are used to determine the sub-signal in the received pointer value. And a sub-signal start position generating means (960) for generating and outputting a clock signal indicating a start position.