KR940002301B1 - Manufacturing method of gate oxide film - Google Patents
Manufacturing method of gate oxide film Download PDFInfo
- Publication number
- KR940002301B1 KR940002301B1 KR1019910013077A KR910013077A KR940002301B1 KR 940002301 B1 KR940002301 B1 KR 940002301B1 KR 1019910013077 A KR1019910013077 A KR 1019910013077A KR 910013077 A KR910013077 A KR 910013077A KR 940002301 B1 KR940002301 B1 KR 940002301B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- temperature
- gas
- deposition
- wafer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000008021 deposition Effects 0.000 claims abstract description 28
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 238000011065 in-situ storage Methods 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 17
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 abstract 1
- 238000001816 cooling Methods 0.000 abstract 1
- 238000002360 preparation method Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
제1도는 본발명의 제1실시예에 의해 게이트 산화막을 형성하는 공정단계를 도시한 도면.1 shows a process step of forming a gate oxide film according to a first embodiment of the present invention.
제2도는 본발명의 제2실시예에 의해 게이트 산화막을 형성하는 단계를 도시한 도면.2 is a diagram showing a step of forming a gate oxide film according to a second embodiment of the present invention.
제3도는 본발명의 제3실시예에 의해 게이트 산화막을 형성하는 단계를 도시한 도면.3 is a diagram showing a step of forming a gate oxide film according to the third embodiment of the present invention.
본발명은 고집적 반도체 소자의 게이트 산화막 제조방법에 관한 것으로, 특히 DRAM, SRAM, LOGIC등 MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor) 구조에서 필수적으로 요구되는 게이트 산화막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a gate oxide film of a highly integrated semiconductor device, and more particularly, to a method of manufacturing a gate oxide film which is essentially required in a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure such as DRAM, SRAM, and LOGIC.
현재 일반적인 게이트 산화막 제조공정은 열산화로(Furnace)에서 대기압 상태에서 약 850∼920℃ 정도의 온도에서 제조되고 있다. 소자가 고집적화됨에 따라, 게이트 산화막의 두께도 초박막화 되고 있다(∼100Å), 따라서 일반적으로 열산화로에서 성장된 열산화막은 정확한 두께 조절이 어렵고, 핀홀(pin hole)이나 입자등에 의한 산화막 파괴로 인해 소자의 수율(yield)를 저하시키고 소자 특성상 요구되는 산화막의 특성등이 저하되는 문제점을 갖고 있다. 이러한 문제점를 해결하기 위해 최근 저압화학 증착로에서 형성되는 증착산화막을 사용하는 적층산화막 제조공정이 많이 연구되고 있다.Currently, a general gate oxide film manufacturing process is manufactured at a temperature of about 850 to 920 ° C. at atmospheric pressure in a thermal oxidation furnace. As the device is highly integrated, the thickness of the gate oxide film is also ultra thin (~ 100 kPa). Therefore, the thermal oxide film grown in the thermal oxidation furnace is generally difficult to accurately control the thickness of the gate oxide film, and the oxide film is destroyed by pin holes or particles. As a result, the yield of the device is lowered, and the characteristics of the oxide film required for the device properties are deteriorated. In order to solve this problem, a multilayer oxide film manufacturing process using a deposition oxide film formed in a low pressure chemical vapor deposition furnace has been studied in recent years.
그러나 소자가 초고집적화됨에 따라 더 이상 열산화막 제조공정이 사용되지 못하여, 자연산화막을 그대로 이용하는 적층산화막이 사용될 전망이다. 이때 자연산화막의 특성을 향상시킬 수 있는 방법이 없으며, 적층산화막 공정이 적어도 2개 이상의 열산화로가 사용되므로 웨이퍼 이동시 대기중 노출되어 계면특성 저하가 특히 우려된다. 또한, 최근에는 소자 특성개선을 위해 게이트 전극을 P+로 도핑(불순물주입)하는데 이때 사용되는 불순물(특시 붕소, B)이 하부의 게이트 산화막으로 확산되어 게이트 산화막 특성을 크게 저하시키게 되는 단점이 있다.However, as the device is ultra-highly integrated, a thermal oxide manufacturing process is no longer used, and thus, a stacked oxide film using a natural oxide film is expected to be used. At this time, there is no method to improve the characteristics of the natural oxide film, and since the at least two thermal oxidation furnaces are used in the stacked oxide film process, exposure to the air during wafer movement is particularly concerned about deterioration of interfacial properties. In addition, in recent years, the gate electrode is doped (impurity implantation) with P + to improve device characteristics. Impurities (such as boron (B)) used at this time are diffused into the lower gate oxide layer, which greatly reduces the gate oxide layer characteristics.
따라서, 본발명은 종래의 문제점을 해결하기 위하여 증착산화막 공정에 인-시투 열처리(In-Situ Anneal) 공정을 추가하여 다층게이트 산화막의 특성을 향상시킨 게이트 산화막 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a gate oxide film manufacturing method which improves the characteristics of a multilayer gate oxide film by adding an in-situ annealing process to a deposition oxide film process in order to solve the conventional problems.
본발명은 열산화막 또는 자연산화막상부에 증착산화막을 형성하는데 대기중 노출에 의한 계면특성악화 및 자연산화막 특성불량을 방지하기 위하여 저압화학 기상 증착로에서 증착산화막 형성전에 N2O 또는 NH3가스를 사용하여 열처리 함으로써 열산화막 혹은 자연산화막의 특성을 개선시키고, 게이트 산화막 상부에 게이트전극에 P형 불순물을 임플란트할때 게이트 산화막에 불순물이 침투되는 것을 방지하기 위하여 증착산화막 형성후 N2O 또는 NH3가스를 사용한 열처리 공정으로 게이트 산화막(SiO)을 질화시킴(Nitridation)으로써 상부의 게이트전극에서 하부의 게이트 산화막에 불순물 침투를 방지하여 게이트 산화막 특성을 향상시킨다.The present invention forms a deposited oxide film on a thermal oxide film or a natural oxide film. In order to prevent deterioration of interface characteristics and natural oxide film defects caused by exposure to air, N 2 O or NH 3 gas is formed before the deposition oxide film is formed in a low pressure chemical vapor deposition furnace. Heat treatment using N 2 O or NH 3 after the deposition oxide film is formed to improve the characteristics of the thermal oxide film or the natural oxide film and to prevent impurities from penetrating the gate oxide film when P-type impurities are implanted into the gate electrode on the gate oxide film. By nitriding the gate oxide layer (SiO) by a heat treatment process using gas, impurity penetration is prevented from the upper gate electrode to the lower gate oxide layer, thereby improving the gate oxide layer characteristics.
본발명에 의하면 대기압에 기판이 노출될때 성장하는 자연산화막이 성장된 웨이퍼를 예정된 온도의 고온용 저압화학 증착로에 보트인시키고 증착로의 온도를 850∼950℃로 상승시키는 단계와, 상기 자연산화막 상부에 증착산화막을 예정된 두께 형성하되, SiH2Cl2와 N2O 가스, 700mtorr 이하의 압력 및 850∼950℃의 온도조건에서 형성하는 단계와, 상기의 850∼950℃의 온도에서 N2O 또는 NH3가스를 유입시키고 상기 증착산화막을 예정된 시간 인-시투열처리를 진행하는 단계와, 증착로 온도를 예정된 온도로 하강시켜서 웨이퍼를 보트아웃트시키는 단계로 이루어지는 것을 특징으로 한다.According to the present invention, a step in which a wafer on which a natural oxide film growing when the substrate is exposed to atmospheric pressure is grown is boated into a high temperature low pressure chemical vapor deposition furnace at a predetermined temperature, and the temperature of the deposition furnace is raised to 850 to 950 ° C., and the natural oxide film A predetermined thickness of the deposited oxide film is formed thereon, and the SiH 2 Cl 2 and N 2 O gas are formed under a pressure of 700 mtorr and a temperature of 850 to 950 ° C., and the N 2 O at the temperature of 850 to 950 ° C. Or introducing NH 3 gas and subjecting the deposited oxide film to a predetermined time in-situ heat treatment, and lowering the temperature to a predetermined temperature by deposition to boat out the wafer.
이하, 첨부된 도면을 참고하여 상세히 설명하면 다음과 같다.Hereinafter, with reference to the accompanying drawings in detail as follows.
제1도는 본발명의 제1실시예에 의해 게이트 산화막 제조단계를 도시한 도면으로서, 열산화로에서 열산화막을 형성한다음, 열산화막이 형성된 웨이퍼를 고온용 저압화학 증착로에 장착(loading)한다. 이때 장착온도는 일반적으로 750℃이나, 이는 입자 및 장비운용등을 고려 임의로 조정가능하다. 웨이퍼장착이 끝나면 이를 열처리시 필요한 온도까지(850℃∼950℃)까지 열산화막 보호용 N2개스를 흘려주면서 온도를 상승시킨후(4∼6℃/min) N2가스를 차단하고, N2O 가스 또는 NH3가스를 유입시켜 예를들어 30분 정도 인-시투 열처리 한다. 이때 기형성된 열산화막의 불완전한 결합(dangling bond) 또는 결함위치(Defect sites)등이 N2O 또는 NH3가스와 반응하여 보다 안정된 열산화막 성질을 갖게되며, 이러한 인-시투 열처리를 거친 산화막을 질화산화막(Nitrided SiO2)이라고 부른다.(이때 주지할 것은 열처리 온도와 시간은 소자 특성을 고려해서 정해지는데, 질화산화막의 특성은 온도가 높을수록, 시간이 길수록 향상될 것이다.) 열처리가 끝나면 모든 가스유입을 막고, 펌프를 동작(Pump-down)시켜 고온용 저압화학증착로의 압력을 진공(≤10mtorr)으로 만든후 누설체크하고, 열산화막 상부에 일반적인 저압화학증착 방법에 의해 증착산화막을 형성하는데 열산화막과 증착산화막의 두께가 200Å 이하로 형성한다. 여기서 증착산화막 형성방법을 예를들면 SiH2Cl2와 N2O 가스를 반응시켜 약 800∼950℃ 사이의 온도에서 형성시키거나, SiH4가스와 N2O 가스를 반응시켜 750℃∼850℃ 온도에서 증착산화막을 형성할 수 있다. 도시한 제1도에서는 SiH2Cl2가스와 N2O 가스를 사용한 경우만을 나타내었다. 그리고, 증착산화막에 N2가스를 유입하면서 온도하강 및 저압화학 증착로의 압력을 대기압으로 하는 백필 단계를 거쳐, 웨이퍼를 보트 아웃트 시킴으로써 열산화막과 증착산화막으로된 게이트 산화막의 특성을 개선시키는 공정단계이다.1 is a view illustrating a gate oxide film manufacturing step according to a first embodiment of the present invention, in which a thermal oxide film is formed in a thermal oxidation furnace, and then a wafer on which the thermal oxide film is formed is loaded into a low pressure chemical vapor deposition furnace for a high temperature. do. At this time, the mounting temperature is generally 750 ° C, but it can be arbitrarily adjusted in consideration of particle and equipment operation. After the wafer is installed, the temperature is raised (4 ~ 6 ℃ / min) while flowing N 2 gas for protecting the thermal oxide film to the temperature (850 ℃ ~ 950 ℃) required for heat treatment, and then the N 2 gas is blocked and N 2 O In-situ heat treatment, for example, for 30 minutes, by introducing gas or NH 3 gas. At this time, incomplete bonds or defect sites of the pre-formed thermal oxide film react with N 2 O or NH 3 gas to have more stable thermal oxide properties, and nitriding the oxide film through the in-situ heat treatment. It is called an oxide film (Nitrided SiO 2 ). (Note that the heat treatment temperature and time are determined in consideration of device characteristics. The characteristics of the oxide nitride film will be improved at higher temperatures and longer times.) It prevents the inflow, pumps down to make the pressure of high temperature low pressure chemical vaporization furnace into vacuum (≤10 mtorr) and then leak checks, and forms a deposited oxide film by the general low pressure chemical vapor deposition method on the thermal oxide film. The thickness of the thermally oxidized film and the deposited oxide film is 200 kPa or less. Here, the deposition oxide film forming method may be, for example, reacted with SiH 2 Cl 2 and N 2 O gas to be formed at a temperature of about 800 to 950 ° C., or by reacting SiH 4 gas with N 2 O gas to 750 ° C. to 850 ° C. The deposition oxide film may be formed at a temperature. In FIG. 1, only SiH 2 Cl 2 gas and N 2 O gas are used. The process of improving the characteristics of the thermal oxide film and the gate oxide film of the deposited oxide film by boating out the wafer through the backfill step of reducing the temperature and the pressure of low pressure chemical vapor deposition to atmospheric pressure while introducing N 2 gas into the deposited oxide film. Step.
제2도는 본발명의 제2실시예에 의해 게이트 산화막 제조단계를 도시한 도면으로서, 웨이퍼 상부의 액티브영역이 대기중에 노출되면 자연산화막이 예를들어 50Å 정도 성장된다. 이와같이 자연산화막이 성장된 웨이퍼를 고온용 저압화학 증착로에 장착하고, (이 장착할때의 증착로의 온도는 750℃이다) 펌프를 동작시켜 증착로의 압력을 진공상태로 예를들어 20mtorr 이하로 하고 누설체크를 한다. 또한 온도를 상승시켜 850∼950℃의 온도로 유지한다음, 자연산화막 상부에 증착산화막을 형성하는데 이 방법은 상기 제1실시예와 같은 방법이므로 중복설명은 피하기로 한다. 그리고 증착로의 압력을 대기압으로, 온도는 증착산화막 증착시 온도 상태에서 N2O 또는 NH3가스를 유입시켜 상기 증착산화막을 인-시투 열처리하고, 증착로의 온도를 하강시킨다음(예를들어 750℃) 웨이퍼를 보투아웃트시켰다. 이와같이 자연산화막 및 증착산화막을 형성한다음, 본발명에 의한 인-시투 열처리를 하게되면 증착산화막이 질화-산화막이 형성됨으로서 상부의 게이트전극의 P형 불순물이 하부의 게이트 산화막에 침투되는 것을 방지할 수 있는 효과가 있다.2 is a view illustrating a gate oxide film fabrication step according to a second embodiment of the present invention. When the active region on the wafer is exposed to the air, a native oxide film is grown by, for example, about 50 microseconds. In this way, the wafer on which the natural oxide film is grown is mounted in a low temperature chemical vapor deposition furnace for high temperature (the deposition furnace temperature is 750 ° C.), and the pump is operated so that the pressure of the vapor deposition furnace is vacuumed, for example, 20 mtorr or less. Leak check In addition, the temperature is raised and maintained at a temperature of 850 to 950 ° C., and then a deposition oxide film is formed on the natural oxide film. This method is the same as the first embodiment, and thus redundant description will be avoided. Then, the pressure of the deposition furnace is atmospheric pressure, and the temperature is introduced into the N 2 O or NH 3 gas at a temperature state during deposition of the deposition oxide film, thereby in-situ heat-treating the deposition oxide film, and lowering the temperature of the deposition furnace (for example, 750 ° C.) The wafer was bottled out. As such, after forming the natural oxide film and the deposited oxide film, in-situ heat treatment according to the present invention forms a nitride oxide film to prevent the P-type impurities of the upper gate electrode from penetrating into the lower gate oxide film. It can be effective.
제3도는 본발명의 제3실시예에 의해 게이트 산화막 제조단계를 도시한 도면으로서, 상기의 제2실시예와 같은 방법으로 자연산화막을 형성한다음, 자연산화막 상부에 증착산화막을 형성할때 SiH와 NO 가스를 사용하기 위하여 고온 저압화학 증착로의 온도를 1차로 750∼850℃까지 상승시킨다음, 자연산화막 상부에 증착산화막을 증착하되 자연산화막과 증착산화막의 두께가 200Å 이하로 형성하고 2차로 상기 증착산화막을 인-시투 열처리하기 위하여 850∼950℃로 온도를 상승시키고, N20 또는 NH3가스에서 예정된 시간 예를 들어 30분 정도 인-시투 열처리를 실시한후 온도를 하강시켜 웨이퍼를 보트 아웃트시키는 것이다. 즉 제3도는 증착산화막을 형성하는 가스를 SiH4와 N2O 가스를 이용하는 것인데 이러한 가스 대신에 Si(C2H5O)가스를 이용하여 700℃ 온도에서 TEOS(Tetra Ethyle Ortho Silicate)를 이용한 산화막을 증착할 수도 있다.3 is a view showing a gate oxide film fabrication step according to a third embodiment of the present invention. When a natural oxide film is formed in the same manner as in the second embodiment, SiH is formed when the deposited oxide film is formed on the natural oxide film. In order to use and NO gas, the temperature of the high temperature low pressure chemical vapor deposition furnace is first increased to 750 to 850 ° C., and then the deposition oxide film is deposited on the upper part of the natural oxide film, but the thickness of the natural oxide film and the deposited oxide film is 200Å or less, and To in-situ heat-treat the deposited oxide film, the temperature is raised to 850 to 950 ° C, the in-situ heat treatment is performed in N 2 O or NH 3 gas for a predetermined time, for example, about 30 minutes, and the temperature is lowered to boat the wafer. It is to be out. In other words, in FIG. 3, SiH 4 and N 2 O gas are used as the gas for forming the deposited oxide film. Instead of such gas, Si (C 2 H 5 O) gas is used, and TEOS (Tetra Ethyle Ortho Silicate) is used at 700 ° C. An oxide film can also be deposited.
상기와 같이 본발명은 고온저압화학 기상증착로에서 이미 형성된 열산화막을 N2O 또는 NH3등의 가스에서 열처리하거나 자연산화막 상부에 증착산화막을 형성한 다음 N2O 또는 NH3가스에서 열처리 함으로서 게이트 산화막 특성을 개선할 수 있다. 즉 유전체 강도 증가, 브레이크 다운에 대한 전체전하량의 증가 및 소자특성 저하를 방지할 수 있다.As described above, the present invention heat-treats a thermal oxide film that is already formed in a high-temperature low-pressure chemical vapor deposition furnace with a gas such as N 2 O or NH 3 , or forms a deposited oxide film on top of a natural oxide film, and then heats it with N 2 O or NH 3 gas. The gate oxide film characteristics can be improved. In other words, it is possible to prevent an increase in dielectric strength, an increase in total charge amount to breakdown, and a decrease in device characteristics.
또한 본발명은 고온저압화학 기상증착로에서 인-시투 열처리를 실시함으로서 공정의 단순화를 통한 경제적 효과를 기대할 수 있다.In addition, the present invention can be expected to economic effects through the simplification of the process by performing in-situ heat treatment in a high temperature low pressure chemical vapor deposition furnace.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910013077A KR940002301B1 (en) | 1991-07-30 | 1991-07-30 | Manufacturing method of gate oxide film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910013077A KR940002301B1 (en) | 1991-07-30 | 1991-07-30 | Manufacturing method of gate oxide film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930003327A KR930003327A (en) | 1993-02-24 |
| KR940002301B1 true KR940002301B1 (en) | 1994-03-21 |
Family
ID=19317986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910013077A KR940002301B1 (en) | 1991-07-30 | 1991-07-30 | Manufacturing method of gate oxide film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940002301B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100332129B1 (en) * | 1995-12-29 | 2002-11-07 | 주식회사 하이닉스반도체 | Method for forming oxide layer in semiconductor device |
-
1991
- 1991-07-30 KR KR1019910013077A patent/KR940002301B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930003327A (en) | 1993-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7569502B2 (en) | Method of forming a silicon oxynitride layer | |
| US9576804B2 (en) | System and method for mitigating oxide growth in a gate dielectric | |
| US6596576B2 (en) | Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4 | |
| US6228779B1 (en) | Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology | |
| US20070169696A1 (en) | Two-step post nitridation annealing for lower eot plasma nitrided gate dielectrics | |
| KR20080113088A (en) | Silicon oxynitride gate dielectric formation using multiple annealing steps | |
| JPH07326622A (en) | Method of maintaining flaw-less region in silicon substrate and its flat structure | |
| US8263501B2 (en) | Silicon dioxide film fabricating process | |
| US20050274948A1 (en) | Semiconductor device and method for manufacturing therefor | |
| US5637528A (en) | Semiconductor device manufacturing method including dry oxidation | |
| US6803330B2 (en) | Method for growing ultra thin nitrided oxide | |
| US6417570B1 (en) | Layered dielectric film structure suitable for gate dielectric application in sub-0.25 μm technologies | |
| US7306985B2 (en) | Method for manufacturing semiconductor device including heat treating with a flash lamp | |
| US6368984B1 (en) | Insulating film and method of forming the same | |
| KR940002301B1 (en) | Manufacturing method of gate oxide film | |
| US6268298B1 (en) | Method of manufacturing semiconductor device | |
| KR100444918B1 (en) | Method of manufacturing semiconductor device | |
| KR100294697B1 (en) | Method for forming conductivity line of semiconductor device | |
| KR100495921B1 (en) | Method of fabrication semiconductor device for remove stress | |
| US6316335B1 (en) | Method for fabricating semiconductor device | |
| JPH07335876A (en) | Method of forming gate insulating film | |
| KR0137550B1 (en) | Formation method of gate oxide | |
| JP3808814B2 (en) | Manufacturing method of semiconductor device | |
| KR0171936B1 (en) | Method of manufacturing transistor in semiconductor device | |
| KR100219486B1 (en) | Method of fabrication oxide film and device of the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100224 Year of fee payment: 17 |
|
| LAPS | Lapse due to unpaid annual fee |