KR940001590B1 - Method and device for shortening memory access time in reading and writing - Google Patents

Abstract

The device includes memories (11,12,13,14) for improving the access time of the block reading and writing, a control signal line (30) for controlling the read and write signal and access signal, an address bus (29) for allocating memories (11,12,13,14) address, a control means (31) for driving the buffer and memory control signals, and buffer means (15,16,17,18) for latching the data by the buffer control signal. The performance of the system is improved by the block reading and writing action in the cache-process system.

Description

Device and Method for Reducing Memory Access Time in Block Read and Write

1 is a configuration diagram of a memory device using a conventional dynamic ram.

2 is a block diagram of a memory access time reduction apparatus according to the present invention.

3 is a block diagram of a controller according to the present invention.

4A and 4B are a flowchart of a method for shortening a memory access time according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 2, 11, 12, 13, 14: memory 3, 4: buffer

5, 31: controller 6, 7: memory select signal line

8, 19: data bus 9, 30: control signal line

10, 29: address bus 15, 16, 17, 18: bidirectional latch and buffer

20, 21, 22, 23: bidirectional latch and buffer control signal line

24, 25, 26, 27: memory control signal line

28: control bus 32: latch

33: comparator 34, 35, 36, 37: control signal generator

The present invention relates to an apparatus and method for fast access to a block write or block read in a memory in a computer or processor system having a block transfer function.

In general, block write and block read access contiguous address areas, so memory is arranged in parallel by the number of block transfer words, and block write and block read are performed with only one memory write and read for high-speed access. It can be realized.

Recently, in order to maximize the performance of microprocessors, the development of microprocessor technology has resulted in the emergence of a large number of processors with a built-in cache. When a processor reads data, it first refers to the cache. If there is no data to read in the cache, the processor reads data from external memory and writes data to the cache at the same time.

In general, a processor with a cache has a block transfer function that reads several consecutive words from external memory and writes them to the cache when the desired data is not in the cache to maximize performance. Is done. In the case of a system using a high performance processor, an external cache is used to improve the performance. If a miss occurs in the external cache, the block transfer function is used to continuously read the memory contents of several words to read the cache contents. By changing, the hit rate of the cache is raised. In such a system, much of the memory reference is made by block transmission, so that the improvement of the block transfer speed directly affects the performance of the entire system.

The number of block transfer words is 2 ⁿ words and is the same as the length of one line of the cache, so most of the block transmission words are composed of 4 to 64 words. The block transfer method can be divided into a method of indicating the address where the address bus reads and writes blocks during block transfer, and maintains the first address of block read and block write during block read and block write. In this case, the memory controller must have an address generator.

Block read and block write performs the same operation as reading and writing in general word unit, and access time compared to word unit access by accessing page mode when using dynamic RAM as memory. You can divide by about half.

The former method has the same access time as word read and write even in block transfer. The latter method accesses page mode access using the feature that block reads and writes access adjacent or contiguous address areas. It can be shortened, but only when dynamic memory is used.

1 is a configuration diagram of a memory device using a conventional dynamic RAM, 1 and 2 are memories, 3 and 4 are buffers, 5 is a controller, 6 and 7 are memory select signal lines, 8 is a data bus, and 9 is a control signal line. And 10 denote address buses, respectively.

In the case of using dynamic RAM as memory, conventional memory devices for saving the dynamic RAS precharge time are generally called interleaved, and the dynamic RAM is accessed again after being accessed. In order to access again after accessing, the user must wait for RAS precharge time. Therefore, memory 0 (1) and memory 1 (2) are composed of two sets as shown in FIG. When access is made for the selection signal on the line 6, when the odd casting is accessed, the memory 1 (2) is accessed by the selection signal on the selection signal line 7. The memory select signal opens the corresponding buffers 3 and 4 which connect the system's data bus 8 to the data bus of the memory being accessed.

Since a significant portion of memory accesses in the processor system access addresses continuously, most of the time accesses alternately between memory 0 and memory 1, eliminating the need to wait for RAS precharge time, enabling fast access. In particular, the read and write blocks alternately access the odd addresses, so that the two memories (1, 2) are accessed alternately, which enables faster access compared to the non-page mode method.

However, the conventional memory device has a problem in that the average time for reading or writing the memory cannot be faster than the memory access time.

In order to solve the above problems, the present invention reads and stores the contents of one block as well as the entire word in a word unit read and write, and stores the contents of the buffer on the bus in the next cycle. It is an object of the present invention to provide an apparatus and method for reducing memory access time for reading and writing data.

In order to achieve the above object, the present invention provides a memory access time shortening device for fast access when a block write or block read is performed on a plurality of memories arranged in parallel, including a data bus, a read and write signal, A control signal line to which an access signal, a block read signal, and a write signal are transmitted, an address bus connected to the plurality of memories, an address bus for transmitting an address for allocating the memory, and a control signal line and an address bus and a plurality of memories Control means for receiving a signal transmitted from the control signal line and the address bus and generating a buffer control signal and a memory selection signal, and data connected in both directions by a buffer control signal of the control means connected to the control means, the memory and the data bus; It consists of a plurality of bidirectional latch and buffer means capable of latching, as described above A first step of reading the memory at the same time and storing the data in the bidirectional latch and buffer means when the block read is the first cycle using the configured device, and simultaneously opening the bidirectional latch and buffer at the corresponding address to transfer the latched data to the data bus; A second step of opening the bidirectional latch and buffer of the corresponding address if the block read is not the first cycle, and transferring the data stored in the first cycle to the bus; and transferring the data to the corresponding bidirectional latch and buffer if the block write is the last cycle. A third step of storing and simultaneously performing a write operation of the entire memory; and a fourth step of storing data in a bidirectional latch-and-buffer at a corresponding address if the block write is not the last cycle.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram of a memory access time reducing apparatus according to the present invention, 11 to 14 are memories, 15 to 18 are bidirectional latches and buffers, 19 are data buses, and 20 to 23 are bidirectional latches and buffer control signal lines. 27 denotes a memory control signal line, 28 denotes a darebus, 29 denotes an address bus, 30 denotes a control signal line, and 31 denotes a controller.

The memory time access shortening apparatus according to the present invention comprises four sets (11, 12, 13, 14) of memory as shown in FIG. 2, and the data buses of the memories 11, 12, 13, and 14 are respectively Are connected to the system's data bus 19 via bidirectional latch and buffers 15, 16, 17 and 18.

The bidirectional latch and buffer 15, 16, 17, and 18 may latch data in both directions by the control signals of the control signal lines 20, 21, 22, and 23, respectively, and operate in the bidirectional buffer or high impedance state. 74F543 is used as a preferred embodiment. The memory is arranged in parallel by the number of block transfer words.

The controller 31 receives the read and write signals, the access signal, the block read signal and the write signal, and the address bus 29 included in the control signal line 30 to the buffer control signal lines 20, 21, 22, and 23. Generates a control signal and a selection signal address on each memory control signal line 24, 25, 26, 27, so that if the value of the address bus 29 maintains the address of the first cycle during block read and block write, Real addresses are created to control the corresponding memory and latch and buffer 15 to 18. If the least significant two bits of the address bus of the memory are 00, memory 0 (11) is allocated, memory 12 (01), memory 2 (13) if 10, memory 3 (14) if 11 is allocated.

In case of reading and writing in word unit, the address storage latch inside the controller 31 is operated so that the address except for the lower two bits among the addresses to read and write (log2n bit when the number of memory arranged in parallel is n) Save). That is, when reading in units of words starts, the address stored in the latch is first compared with the address applied to the address bus. If the same, the data is already read from the memory and stored in the bidirectional latch and buffer (15, 16, 17, 18). Therefore, the contents of the bidirectional latch and buffer 15 to 18 indicated by the address bus of the lower two bits (the address bus of the lower log2n bits when the number of memory arranged in parallel is n) are loaded on the data bus 19. If the address stored in the latch in the controller 31 and the address applied to the address bus 29 are different from each other, the entire memory 11 to 14 arranged in parallel are simultaneously read and the data is stored in the corresponding bidirectional latch and buffer 15 to 18. At the same time, the bidirectional latch and buffer 15 to 18 of the corresponding address to be read are opened to load data to the data bus 19 and store the address in a latch in the controller 31.

In word-based writing, data is stored in the bidirectional latch and buffer 15 to 18 of the corresponding address and the write completion signal RDY * is given to the processor to terminate the write cycle. The memory of the addresses to which writes are to be performed in the memories 11 to 14 allows the write operation to be performed and the remaining memories to perform the read operation at the same time and simultaneously stores the address in a latch in the controller 31. This may be performed by differently applying only the read / write signals R / W of the memory to the controller 31 and the control signals. The bidirectional latch and buffers 15 to 18 connected to the memory for performing the read operation then store the data read from the memory.

When the above operation is performed, a block of data corresponding to an address stored in the latch in the controller 31 is stored in the bidirectional latch and buffers 15, 16, 17, and 18 so that the area to be read in the next read operation is stored. In this area, since data can be read from the bidirectional latch and buffers 15 to 18 without a memory read operation, fast data access is possible. In general, the processor is characterized in that the memory areas that are continuously accessed are in contiguous or contiguous areas. Thus, a method of reading and storing a block of data in a buffer during word-based access reduces the overall memory access time of the processor.

3 is a configuration diagram of the controller 31 according to the present invention, which shows the configuration of the controller 31 for controlling the memory access time reduction apparatus having four sets of memories.

In the figure, 32 is a latch, 33 is a comparator, and 34, 35, 36 and 37 are control signal generators, respectively.

As shown in FIG. 3, the controller 31 according to the present invention excludes the address strobe signal which becomes a logic level " 0 " and the lower two bits of the address bus 29 when a valid signal is loaded on the address bus 29 as shown in FIG. A latch 32 for storing an address bus except the lower 2 bits at a rising edge of the address strobe signal as an input of an address bus, and connected to the latch 32 and the address bus except the lower 2 bits. And a comparator 33 for comparing whether an address stored in the latch 32 and an address on the address bus are the same value, and a programmable array logic (PAL), and the address strobe signal, read / write signal, and block transfer. The lower two bits of the address bus 29, an address strobe signal, a read / write signal, a block connected to a control signal line 30, a comparator 33, and an address bus 29 for transmitting a signal and an access completion signal; Transmit signals Outputs an access completion signal, a bidirectional latch and buffer control signal through the bidirectional latch and buffer control signal lines 20, 21, 22, and 23, and a memory control signal transmitted through the control bus 28; Control signal generators 34, 35, 36, and 37 arranged in parallel by the number of?.

The lower two bits of the address bus 29 input to the control signal generators 34, 35, 36, and 37 are set by the log2n bits (n is the number of memories) and represent a case where the number of memories is four.

The comparator 33 compares an address of a previous memory access cycle with an address to be accessed in the current cycle to determine whether data to be accessed is stored in the latch 32 to control the generator 34, 35, 36. , 37).

The control signal generators 34, 35, 36, and 37 are a combination of input signals: 1) a write operation incomplete state before a word unit write cycle, 2) a write operation complete state in a write cycle before a word unit write state, and 3) a block write operation. Non-last cycle state, 4) Last cycle state in block write, 5) Data to be read in word-read read is in bidirectional latch and buffer, 6) Data to read in word-read read is written in bidirectional latch and buffer No state, 7) first cycle state in block read, and 8) bidirectional latch and buffer control signal, memory control signal, access completion signal to determine the non-first cycle state in block read and perform the following eight operations accordingly. Outputs

1) Wait for the output of the previous cycle to complete.

2) The data loaded on the data bus 19 is written to the corresponding address memory, and the remaining memory reads the data, stores the data in the bidirectional latch and buffer, and outputs an access completion signal.

3) It stores the data carried on the data bus 19 as a bidirectional latch of the corresponding address and outputs an access completion signal.

4) The data stored in the data bus 19 is stored in the bidirectional latch and buffer of the corresponding address, and the data stored in each of the bidirectional latch and buffers 15, 16, 17, and 18 are written in all memories, and at the same time, the access completion signal Outputs

5) Data stored in the bidirectional latch and buffer of the corresponding address is loaded on the data bus 19 and an access completion signal is output.

6), 7) Read the data of all memories and store in the bidirectional latch and buffer (15, 16, 17, 18) and simultaneously open the bidirectional latch and buffer of the corresponding week to load data to the data bus 19 and complete the access. Signal output.

8) Data stored in the bidirectional latch and buffer of the corresponding address is loaded on the data bus 19 and an access completion signal is output.

4 is a flowchart of a method for shortening a memory access time according to the present invention, and FIG. 4A shows a block read and FIG. 4B shows a block write.

In the case of a block read, the controller 31 searches for the first cycle of the block read (40), and if it is the first cycle, reads the memory 11, 12, 13, and 14 arranged in parallel by the number of block read words at once. 15, 16, 17, 18), at the same time open the latch (15, 16, 17, 18) of the address and put the latched data on the data bus (60), if not the first cycle Open the latch on the memory to load the data already stored in the first cycle on the data bus (60).

In the case of block write, it is searched whether it is the last cycle of block write (70), if it is not the last cycle, the data is stored in the latch of the corresponding address and the cycle is terminated (80). The write operation of the entire memory is performed to write the data stored in the previous cycle into the memory at once (100).

The present invention configured and operated as described above has an application effect of improving the performance of a system by shortening the memory access time of a high performance system in which a cache update is performed by block read and block write in a processor system having a cache.

Claims (7)

A memory access time shortening device for fast access at the time of writing or reading a block to a plurality of memories (11, 12, 13, 14) arranged in parallel; Connected to a data bus 19 through which data is transmitted, a control signal line 30 through which read and write signals, an access signal, a block read signal, and a write signal are transmitted, and the plurality of memories 11, 12, 13, and 14. The address bus 29, the control signal line 30, the address bus 29, and the plurality of memories 11, 12, 13, 14, to which an address for allocation of the memory 11, 12, 13, 14 is transmitted. Control means 31 for receiving a signal transmitted from the control signal line 30 and the address bus 29 and generating a buffer control signal and a memory control signal, and the control means 31 and the memory 11 , 12, 13, 14 and a plurality of bidirectional latch and buffer means 15, 16, 17, 18 connected to the data bus 19 to latch data in both directions by the buffer control signal of the control means 31. Memory access time reduction device, characterized in that consisting of. 2. The apparatus of claim 1, wherein the memory (11, 12, 13, 14) is arranged in parallel by the number of words of the block read. The method of claim 1, wherein the bidirectional latch and buffer means (15, 16, 17, 18) is shortened the memory access time, characterized in that arranged in parallel with the number of the memory (11, 12, 13, 14) Device. 2. The control circuit of claim 1, wherein the control means (31) is connected to the control signal line (30) and the address bus (29) so that the address strobe signal of the control signal line (30) and the lower of the address bus (29). A latch 32 for storing an address bit excluding the lower specific bit in the rising edge of the address strobe signal by inputting an address bus excluding a specific bit, and connected to the address bus 29 and the latch 32 Comparing means 33 for comparing the address stored in the latch 32 and the address contained in the address bus 29, and connected to the control signal line 30 and the comparison means 33 and the address bus 29 A plurality of control signal generating means 34 for generating a buffer control signal and a memory control signal to the control signal of the control signal line 30 and the specific bit of the address bus 29 and the output of the comparison means 33. , 35, 36, 37) characterized in that the memory Reduce access time. 5. The memory access time shortening according to claim 4, wherein the control signal generating means (34, 35, 36, 37) is arranged in parallel with the number of the memories (11, 12, 13, 14). Device. 5. The apparatus of claim 4, wherein the lower specific bits of the address bus (29) are set by the number of the memories (11, 12, 13, 14). Connected to the data bus 19 through which data is transmitted, the control signal line 30 through which read and write signals, access signals, block read signals, and write signals are transmitted, and the plurality of memories 11, 12, 13, and 14. The address bus 29, the control signal line 30, the address bus 29, and the plurality of memories 11, 12, 13, 14, to which an address for allocation of the memory 11, 12, 13, 14 is transmitted. Control means 31 for receiving a signal transmitted from the control signal line 30 and the address bus 29 and generating a buffer control signal and a memory selection signal, and the control means 31 and the memory 11 12, 13, 14 and a plurality of bidirectional latch and buffer means 15, 16, 17, connected to the data bus 19 to latch data in both directions by the buffer control signal of the control means 31, 18) A method for shortening a memory access time of a device, comprising: 18); If the block read is the first cycle, the memory is read at the same time and stored in the bidirectional latch and buffer means 15, 16, 17 and 18, and at the same time, the bidirectional latch and buffers 15, 16, 17 and 18 of the corresponding address are opened and latched. In the first step of transferring data to the data bus 19, if the block read is not the first cycle, the bidirectional latch and buffer 15, 16, 17 and 18 of the corresponding address are opened to store the data stored in the first cycle. A second step of transferring the data to the data bus 19, and if the block write is the last cycle, the data is stored in the corresponding bidirectional latch and buffer 15, 16, 17, 18 and simultaneously the entire memory 11, 12, 13 A third step of performing a write operation of step 14, and a fourth step of storing data in the bidirectional latch and buffers 15, 16, 17, and 18 at the corresponding address if the block write is not the last cycle. Characterized by Reduced memory access time.