KR940001492B1 - Data clearing method of video camera and clearing circuit therefor - Google Patents

Abstract

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Description

Data erasing method and circuit in video camera

1 is a conventional circuit diagram.

2 is a circuit diagram according to the present invention.

3 is a detailed circuit diagram of the address generator 50 of FIG.

4 is a flow chart according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for erasing digital still data in a video camera, and more particularly, to a data erasing method and circuit in a video camera capable of erasing data recorded on an IC card according to a desired section by setting a predetermined section.

In general, an analog video signal, which is input from a CCD from a video camera, is converted into digital data by an A / D converter and recorded in a buffer memory. The amount of data stored in the buffer memory is about one frame. The data of the buffer memory recorded about one frame is erased when the power is turned off, and must be recorded on the recording medium. For example, in the case of recording the data on the IC card, unnecessary data, that is, need not be preserved or even data recorded wrongly taken, has consumed a lot of IC cards and it is uneconomical.

In order to solve this problem, conventionally, an unnecessary signal is processed into a black, white, or unspecified screen using an analog signal input through a CCD.

Referring to FIG. 1, the conventional technology will be described in detail. When one frame of digital video data is recorded in the buffer memory 10, the address generator 50 generated by the address generator 50 under the control of the microcomputer 30 ( The data is written to the IC card unit 40 in accordance with the output address data of 50). As described above, the contents inside the IC card unit 40 cannot be erased by the IC card unit 40 alone, and once the predetermined area of the buffer memory 10 is erased, the remaining data is deleted from the IC card. The recording is made in the section 40. The concept of erasing is to convert to specific data or to record other image data by the control of the microcomputer 40 for the part to be erased. In this case, there is no problem, but when erasing a predetermined portion of the data already recorded on the IC card to be used in the IC card unit 40, the data of the IC card is first transferred to the buffer memory 10 and the microcomputer 30 is transferred. After erasing under the control of the " control " That is, when erasing, it is necessary to move to the buffer memory 10 and to process it.

Accordingly, it is an object of the present invention to provide a method and apparatus for directly erasing the contents data of an IC card without setting up a section in which data recorded on the IC card is to be deleted without moving the buffer memory.

According to the present invention for performing the above object, a first process of checking whether the delete mode is executed, a second process of setting a section to be deleted when the delete mode is performed in the first process, and a deleting of the setting section to be deleted from the second process Characterized in that the third process is executed according to the key input.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram according to the present invention. The data is made by grounding the IC card unit 40, the buffer memory 10 storing digital data for one frame, and the output data of the buffer memory 10. A multiplexer 20 for selecting a key, an erase section setting switch SW1 and SW2 for selecting a section (total or specified) to be erased from the IC card unit 40, and an erase mode execution for specifying an erase mode selection and execution. The multiplexer 20 selects and erases data for the IC card unit 40 according to selection of setting switches SW3 and SW4 and the erasing section setting and mode execution setting switches SW1-SW4. The microcomputer 30 generating a control signal according to the area and execution to be performed, and address data for designating the erasing area setting and recording / reproducing of the IC card unit 40 according to the control signal generated by the microcomputer 30. An address generator that generates 50).

FIG. 3 is a specific circuit diagram of the address generator 50 of FIG. 1, which includes a first address generator 21 for counting a specific time signal from the microcomputer 30 to generate a specific section setting address signal, and the microcomputer 30. FIG. The second address generator 22 which counts the entire section signal from the second section and generates the entire section setting address signal, and the first and second address generators 21 and 22 according to the output control signal of the microcomputer 30. It consists of a multiplexer 23 which selects a specific and total section setting address which occurs at < RTI ID = 0.0 >

4 is a flow chart according to the present invention, a first process of generating a selection control signal by checking a deletion mode, a second process of generating a section setting signal to be deleted by receiving the selection control signal of the first process, The third step of generating a delete execution control signal after confirming whether or not the actual execution is performed according to whether the section of step 1 is set or not is performed.

Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4. First, the configuration relationship will be clearly described. The data line of the buffer memory 10 may be divided into multiplexers 20. Terminal B, the B terminal of the multiplexer 20 is connected to the ground. The control terminal C1 of the multiplexer 20 is connected to the microcomputer 30 and the output of the multiplexer 20 is a data line of the IC card unit 40.

The address line of the next IC card portion 40 is connected to the line coming out of the address generator 50. The control terminal C2 of the address generator 50 is connected to the port P8 of the microcomputer 30. Then, the write enable signal of the IC card 40 ( ) Is connected to the port P3 of the microcomputer 30. In addition, the control terminal C2 of the multiplexer 20 is connected to the port P1 of the microcomputer 30, and the microcomputer 30 inputs SW3, SW4 (SW3: delete mode key, SW4: delete execution key). .

3 is a section to be deleted by the address generator circuit for the internal road of the address generator 50 of FIG. It is a selection circuit that decides whether to delete the entire IC card unit 40 contents or only a specific section according to setting the deletion section. This control connects the control terminal C2 of the multiplexer 23 to the port P8 of the microcomputer 30 and connects the multiplexer 23. Is connected to the first address generator 21 which is a specific section setting address generator, and B is connected to the second address generator 22 which is a full section address generator. Therefore, when the port P8 is "L", the specific section address is used as the address of the IC card section 40, and when the port P8 is "H", the entire section address is the address of the IC card section 40. Used as an address.

When deleting, it is executed based on the processing flow of the microcomputer 30. First, when a key input is detected from the deleting mode switch SW3, the microcomputer 30 checks that the microcom 30 is in the deleting mode in step 4a and checks the port P1. The multiplexer 20 is controlled by making the first control signal "H". Therefore, since the connection of the multiplexer 20 to B is the ground "GND", the output of the multiplexer 20 is all "0".

If the erase mode is not performed in the process (4a), the port P1 becomes the second control signal L in the microcomputer 30, and thus the output of the multiplexer 20 is the output of the buffer memory 10. When the delete mode switch SW3 is detected and the next delete execution key SW4 is turned on, that is, when the specific section key SW2 is detected in step 4c as a key input, the microcomputer 30 detects a specific section and detects the port P8. ) Is output as "L", and if the whole section key (SW1) is detected, the entire section is detected and the port P8 is output as "H". That is, the setting according to the specific and the whole section is executed in the process (4d, 4e). Therefore, since the port P8 is "L" in the specific section, the multiplexer 23 generates the specific section address from the first address generator 23 and outputs it to the IC card unit 40, and the port P8 in the entire section. Since this is "H", the multiplexer 23 generates the entire section address from the second address generator 22 and outputs it to the IC card section 40. When the next delete execution key (SW4) is detected, the microcomputer 30 receives the signal to execute the deletion and outputs the port P8 to "L" to enable the write enable of the IC card unit 40 ( ) Is active when "L", so that the data (mode "0") output from the multiplexer 20 is written to the address generated by the multiplexer 21 in the IC card unit 40.

If the delete execution key SW4 does not enter the delete execution key SW4, the microcomputer 30 outputs the port P3 to " H ", so that the IC card unit 40 is not written. → H) Since the Ø data (deleting data) output from the multiplexer 20 is not written, the contents of the IC card portion 40 are not erased.

Briefly describing the contents of the present invention, when it is desired to delete the contents of the IC card unit 40, first, the delete mode key SW3 is inputted, the section is set as the whole and specific section keys SW1 and SW2, and the next delete operation is executed. If the key (SW4) is keyed in, the section set by the entire section and the specific section (SW1, SW2) becomes data as "0", so all the data in the corresponding section becomes "0" so that it is erased. Will be.

As described above, there is an advantage that the data already recorded in the IC card portion can be freely deleted according to a desired section without any troublesome operation.

Claims (3)

A method of erasing still data of a video camera, the method comprising: a first process of checking a deletion mode and generating a selection control signal; a second process of receiving a selection control signal of the first process and generating a deletion section setting signal; And a third process of generating a delete execution control signal after confirming whether or not the actual execution is performed according to whether a section is set in one step. In the still data erasing circuit of the video camera, the IC card unit 40, the buffer memory 10 storing digital data for one frame, and the data produced by grounding the output data of the buffer memory 10 are grounded. A multiplexer 20 for selecting a function, an erase period setting switch (SW1, SW2) for selecting a section (total or specified) for erasing the IC card unit 40, and an erase mode for specifying an erase mode selection and execution. The multiplexer 20 selects and erases data for the IC card unit 40 according to selection of setting switches SW3 and SW4 and the erasing section setting and mode execution setting switches SW1-SW4. The microcomputer 30 generating a control signal according to the area and execution to be performed, and address data for designating the erasing area setting and recording / reproducing of the IC card unit 40 according to the control signal generated by the microcomputer 30. Uh raise In the video camera, it characterized by consisting of a less generator 50, the data erase circuit. The first address generator 21 and the microcomputer 30, wherein the address generator 50 counts a specific time signal from the microcomputer 30 and generates a specific section setting address signal. The second address generator 22 which counts the entire section signal and generates the entire section setting address signal, and the first and second address generators 21 and 22 generated according to the output control signal of the microcomputer 30. And a multiplexer (23) which selects a specific and total section setting address and applies it to the IC card section (40).