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KR930012122B1 - Method of fabricating a capacitor for semiconductor memory device - Google Patents

Method of fabricating a capacitor for semiconductor memory device Download PDF

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Publication number
KR930012122B1
KR930012122B1 KR1019910011937A KR910011937A KR930012122B1 KR 930012122 B1 KR930012122 B1 KR 930012122B1 KR 1019910011937 A KR1019910011937 A KR 1019910011937A KR 910011937 A KR910011937 A KR 910011937A KR 930012122 B1 KR930012122 B1 KR 930012122B1
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KR
South Korea
Prior art keywords
capacitor
polysilicon
node
node polysilicon
memory device
Prior art date
Application number
KR1019910011937A
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Korean (ko)
Other versions
KR930003382A (en
Inventor
금은섭
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019910011937A priority Critical patent/KR930012122B1/en
Publication of KR930003382A publication Critical patent/KR930003382A/en
Application granted granted Critical
Publication of KR930012122B1 publication Critical patent/KR930012122B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

The capacitor of semiconductor device is prepared by coating and selectively etching 1st node polysilicon on a substrate having gates; coating 1st dielectric film and 1st plate polysilicon, etching them to remain at the narrower area than 1st node polysilicon, to expose the ends of 1st node polysilicon and to form the lower layer capacitor; coating an insulating film on the whole area, etching it to expose the part of 1st node polysilicon ends and to isolate the lower capacitor; coating 2nd node polysilicon to connect with 1st node, and selectively etching to remain as capacitor area; coating 2nd node polysilicon with 2nd dielectric film and 2nd plate polysilicon in order to form the upper capacitor.

Description

반도체 메모리 소자의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

제1a-e도는 본 발명의 1실시예에 따른 반도체 메모리 소자의 커패시터 제조공정단면도이다.1A to 1E are cross-sectional views of a capacitor manufacturing process of a semiconductor memory device according to an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 빈도체 기판 2 : 필드 산화막DESCRIPTION OF SYMBOLS 1: Frequency substrate 2 Field oxide film

3 : 게이트 4 : 제1노드 폴리실리콘3: gate 4: first node polysilicon

5 : 제2유전체막 6 : 제1플레이트 폴리실리콘5: second dielectric film 6: first plate polysilicon

7 : 절연막 8 : 제2노드 실리콘7 insulating film 8 second node silicon

9 : 제2유전체막 10 : 제2플레이트 폴리실리콘9: second dielectric film 10: second plate polysilicon

본 발명은 반도체 소자에 관한 것으로, 특히 커패시터의 용량증가를 도모하여 고집적화에 적용할 수 있도록 한 반도체 메모리 소자의 커패시터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor memory device, which can be applied to high integration by increasing the capacity of a capacitor.

현재, 반도체 소자의 계속적인 고집적화 추세에 따라 좁아지는 면적에 필요한 용량의 커패시터를 얻기 위한 활발한 연구가 진행중에 있다. 본 발명은 이와 같은 연구중의 하나로써, 본 발명의 목적은 절연막을 이용하여 상층 및 하층 커패시터를 형성시킨 더블 스택구조를 갖는 반도체 메모리 소자의 커패시터 제조방법을 제공하는 것이다.At present, active researches are underway to obtain a capacitor having a capacity required for a narrowing area according to the continuous trend of high integration of semiconductor devices. The present invention is one of such studies, and an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor memory device having a double stack structure in which upper and lower capacitors are formed using an insulating film.

이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.

제1도(a)-(e)는 본 발명의 1실시예에 따른 반도체 메모리 소자의 커패시터 제조공정단면도로서, 우선 제1도(a)에 도시한 바와 같이 게이트(3)가 형성된 반도체 기판(1)상에 커패시터 형성을 위하여 전면에 제1노드 폴리실리콘(4)을 도포하고 소정의 부분으로 제한하여 패턴을 형성한 후, 제1도(b)와 같이 전면에 제1유전체막(5), 제1플레이트 폴리실리콘(6)을 차례로 도포하고 제1노드 폴리실리콘(4)보다 좁은 범위로 제한해서 남도록 식각한다. 참조번호 2는 필드산화막을 나타낸다.1A to 1E are cross-sectional views of a capacitor manufacturing process of a semiconductor memory device according to an exemplary embodiment of the present invention. First, as shown in FIG. 1) The first node polysilicon 4 is coated on the entire surface to form a capacitor on the front surface, and the pattern is limited to a predetermined portion, and then the first dielectric film 5 is formed on the front surface as shown in FIG. The first plate polysilicon 6 is applied sequentially and then etched so as to remain limited to a narrower range than the first node polysilicon 4. Reference numeral 2 denotes a field oxide film.

그후, 제1도(c)에 도시한 바와 같이 전면에 절연막(7)을 도포하고 제1유전막(5)과 제1플레이트 폴리실리콘(6)은 덮으면서 제1노드 폴리실리콘(4)의 양단의 일정부분이 노출되도록 식각한 후, 제1도(d)와 같이 전면에 제2노드 폴리실리콘(8)을 도포하여 제1노드 폴리실리콘(4)과 연결시키고 커패시터 영역으로 제한해서 남도록 식각한 다음, 제1도(e)와 같이 제2노드 폴리실리콘(8)상에 제2유전체막(9), 제2플레니트 폴리실리콘(10)을 도포하면 본 발명에 따른 반도체 메모리 소자의 커패시터를 얻을 수 있게 된다.Thereafter, as shown in FIG. 1C, an insulating film 7 is coated on the entire surface, and both ends of the first node polysilicon 4 are covered while covering the first dielectric film 5 and the first plate polysilicon 6. After etching to expose a portion of the second, as shown in Figure 1 (d) is applied to the second node polysilicon (8) in front of the connection to the first node polysilicon (4), and limited to the capacitor region and left Next, as shown in FIG. 1E, when the second dielectric film 9 and the second planar polysilicon 10 are coated on the second node polysilicon 8, the capacitor of the semiconductor memory device according to the present invention is applied. You can get it.

이상 설명한 바와 같이, 본 발명에 따르면 하층 커패시터와 상층커패시터 사이에 절연막을 형성시킨 더블 스택 구조의 커패시터를 형성시킴으로 인하여 고집적화에 요구되는 용량의 커패시터를 얻을 수 있는 효과가 있다.As described above, according to the present invention, a capacitor having a double stack structure in which an insulating film is formed between the lower capacitor and the upper capacitor has an effect of obtaining a capacitor having a capacity required for high integration.

Claims (1)

게이트가 형성된 반도체 기판상의 전면에 제1노드 폴리실리콘을 도포하고 소정 부분으로 제한해서 남기는 공정과, 전면에 제1유전체막, 제1플레이트 폴리실리콘을 도포하고 상기 제1노드 폴리실리콘의 양단이 노출되도록 상기 제1노드 폴리실리콘보다 좁은 범위로 제한해서 남겨서 하층 커패시터를 형성하는 공정과, 전면에 절연막을 도포하고 상기 제1노드 폴리실리콘 양단의 상기 노출부분의 일부가 노출되도록 식각하여 하층 커패시터를 절연시키는 공정과, 전면에 제2노드 폴리실리콘을 도포하여 상기 제1노드 폴리실리콘과 연결시키고 커패시터 영역으로 제한해서 남도록 식각하는 공정과, 상기 제2노드 폴리실리콘상에 제2유전체막, 제2플레이트 폴리실리콘을 차례로 도포하여 상층 커패시터를 형성시키는 공정으로 이루어진 반도체 메모리 소자의 커패시터 제조방법.Applying the first node polysilicon to the entire surface of the semiconductor substrate on which the gate is formed and restricting it to a predetermined portion; Forming a lower layer capacitor by limiting it to a narrower range than the first node polysilicon so as to insulate the lower layer capacitor by applying an insulating film to the entire surface and etching a portion of the exposed portion of both ends of the first node polysilicon to expose the lower layer capacitor. Forming a second node polysilicon on the entire surface thereof, connecting the first node polysilicon to the first node polysilicon, and limiting the capacitor region to the capacitor region; A semiconductor memory device comprising a process of forming polysilicon by sequentially applying polysilicon Capacitor manufacturing method.
KR1019910011937A 1991-07-13 1991-07-13 Method of fabricating a capacitor for semiconductor memory device KR930012122B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011937A KR930012122B1 (en) 1991-07-13 1991-07-13 Method of fabricating a capacitor for semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011937A KR930012122B1 (en) 1991-07-13 1991-07-13 Method of fabricating a capacitor for semiconductor memory device

Publications (2)

Publication Number Publication Date
KR930003382A KR930003382A (en) 1993-02-24
KR930012122B1 true KR930012122B1 (en) 1993-12-24

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KR1019910011937A KR930012122B1 (en) 1991-07-13 1991-07-13 Method of fabricating a capacitor for semiconductor memory device

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KR930003382A (en) 1993-02-24

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