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KR930011299A - Thin Film Transistor Manufacturing Method - Google Patents

Thin Film Transistor Manufacturing Method Download PDF

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Publication number
KR930011299A
KR930011299A KR1019910020852A KR910020852A KR930011299A KR 930011299 A KR930011299 A KR 930011299A KR 1019910020852 A KR1019910020852 A KR 1019910020852A KR 910020852 A KR910020852 A KR 910020852A KR 930011299 A KR930011299 A KR 930011299A
Authority
KR
South Korea
Prior art keywords
amorphous semiconductor
thin film
insulating film
source
film transistor
Prior art date
Application number
KR1019910020852A
Other languages
Korean (ko)
Other versions
KR940007458B1 (en
Inventor
강경철
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019910020852A priority Critical patent/KR940007458B1/en
Publication of KR930011299A publication Critical patent/KR930011299A/en
Application granted granted Critical
Publication of KR940007458B1 publication Critical patent/KR940007458B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 양질의 액정표시를 실현할 수 있는 박막 트랜지스터 제조방법에 관한 것으로, 기판(1)상에 게이트(2) 형성후게이트 절연막(3)과 비정질 반도체(4) 및 n비정질 반도체(5)를 적층 패터닝하는 단계, 게이트 절연막(3)상의 n비정질 반도체(5) 및 비정질 반도체(4)의 불필요한 부분을 제거후 화소전극(7) 형성단계, 배리어 금속(6)을 증착하고 소오스/드레인용 전극(8)을 도프후 사진 시각법으로 소오스/드레인용 전극(8)과 배리어 금슥(6) 및 n비정질 반도체(5)의 불필요한 부분을 식각하는 단계로 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor capable of realizing high quality liquid crystal display. The gate insulating film 3 and the amorphous semiconductor 4 and the n amorphous semiconductor 5 are formed after the gate 2 is formed on the substrate 1. Stack patterning, removing the unnecessary portions of the n-amorphous semiconductor 5 and the amorphous semiconductor 4 on the gate insulating film 3, and then forming the pixel electrode 7, depositing the barrier metal 6, and depositing a source / drain electrode. After dope (8), an unnecessary portion of the source / drain electrode 8, the barrier metallization 6, and the n amorphous semiconductor 5 is etched by a photographic visual method.

Description

박막 트랜지스터 제조방법Thin Film Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 박막 트랜지스터의 공정 단면도.2 is a process cross-sectional view of the thin film transistor of the present invention.

Claims (1)

기판(1)상에 게이트(2)를 형성하고 게이트 절연막(3)과 비정질 반도체(4) 및 n비정필 반도체(5)를 차례로 적층하여 패터닝하는 단계와, 게이트 절연막(3)상의 n비정질 반도체(5) 및 비정질 반도체(4)의 불필요한 부분을 사진 식각법에 의해 제거하고 화소전극(7)을 형성하는 단계와, 배리어금속(6)을 증착하고 소오스/드레인용 전극(8)을 도프한후 사진 식각법으로 소오스/드레인용 전극(8)과 배리어 금속(6) 및 n비정질 반도체(5)의 불필요한 부분을 식각하는 단계로 제조함을 특징으로 하는 박막 트랜지스터 제조방법.Forming a gate 2 on the substrate 1, stacking and patterning the gate insulating film 3, the amorphous semiconductor 4, and the n amorphous semiconductor 5 in sequence, and the n amorphous semiconductor on the gate insulating film 3 (5) and removing unnecessary portions of the amorphous semiconductor 4 by photolithography to form the pixel electrode 7, depositing the barrier metal 6 and doping the source / drain electrode 8 And etching unnecessary portions of the source / drain electrode (8), the barrier metal (6), and the n amorphous semiconductor (5) by a photolithography method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020852A 1991-11-21 1991-11-21 Manufacturing method of thin film transistor KR940007458B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910020852A KR940007458B1 (en) 1991-11-21 1991-11-21 Manufacturing method of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910020852A KR940007458B1 (en) 1991-11-21 1991-11-21 Manufacturing method of thin film transistor

Publications (2)

Publication Number Publication Date
KR930011299A true KR930011299A (en) 1993-06-24
KR940007458B1 KR940007458B1 (en) 1994-08-18

Family

ID=19323253

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910020852A KR940007458B1 (en) 1991-11-21 1991-11-21 Manufacturing method of thin film transistor

Country Status (1)

Country Link
KR (1) KR940007458B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498864B1 (en) * 2001-07-13 2005-07-04 르 라보레또레 쎄르비에르 New benzenesulphonamide compounds, a process for their preparation and pharmaceutical compositions containing them

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498864B1 (en) * 2001-07-13 2005-07-04 르 라보레또레 쎄르비에르 New benzenesulphonamide compounds, a process for their preparation and pharmaceutical compositions containing them

Also Published As

Publication number Publication date
KR940007458B1 (en) 1994-08-18

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