KR930006226B1

KR930006226B1 - Digital monostable multivibrator

Info

Publication number: KR930006226B1
Application number: KR1019900011069A
Authority: KR
Inventors: 이범철; 박권철
Original assignee: 한국전기통신공사; 이해욱; 재단법인 한국전자통신연구소; 경상현
Priority date: 1990-07-20
Filing date: 1990-07-20
Publication date: 1993-07-09
Also published as: KR920003643A

Abstract

The multivibrator is retriggerable while generating the pulse related only to the external clock pulse without the influence of operational circumstances. It is composed of logical devices and operates digitally. It includes a transition detecting section for detecting the transition of input pulse, a pulse generating section for generating the pulse of which period is the same as that of external clock pulse whenever transition occurs in the clock pulse applied from the external, and a monostable controlling section for controlling the pulse generating section to generate pulses only when transition occurs.

Description

Digital Monostable Multivibrator

제1도는 본 발명의 일실시예에 대한 회로도.1 is a circuit diagram of an embodiment of the present invention.

제2도는 본 발명의 일실시예의 회로도에 대한 타이밍도.2 is a timing diagram of a circuit diagram of an embodiment of the present invention.

제3도 및 제4도는 본 발명의 다른 실시예에 대한 회로도.3 and 4 are circuit diagrams of another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

CP : 외부 클럭펄스 입력단자CP: External clock pulse input terminal

D : 멀티바이브레이터로 입력되는 펄스 입력단자D: Pulse input terminal input to multivibrator

Q : 멀티바이브레이터 출력단자 U1~U3,U31~U34,U41~U44 : D 플립플롭Q: Multivibrator output terminal U1 ~ U3, U31 ~ U34, U41 ~ U44: D flip-flop

U4,U35,U36,U46 : AND 게이트U4, U35, U36, U46: AND gate

본 발명은 디지틀적으로 동작하는 단안정 멀티바이브레이터(monostable multivibrator)에 관한 것이다.The present invention relates to a monostable multivibrator operating digitally.

종래의 단안정 멀티바이브레이터는 선형소자와 논리소자를 결합하여 외부에서 저항과 캐패시터를 달아 시정수를 맞추는 아날로그로 구성되는 회로였다. 이에 대표적인 소자가 표준화된 논리회로인 74123이다. 이단안정 멀티바이브레이터는 외부에서 저항과 캐패시터로 시정수를 맞추기 때문에 정확한 펄스 발생이 어렵고 동작 환경에 따라 발생되는 펄스폭이 달라지는 단점이 있다.The conventional monostable multivibrator is a circuit composed of an analog that combines a linear element and a logic element to adjust a time constant by attaching a resistor and a capacitor from the outside. A typical device is 74123, which is a standardized logic circuit. Since the two-stable multivibrator adjusts the time constant with a resistor and a capacitor from the outside, accurate pulse generation is difficult and the pulse width generated varies depending on the operating environment.

본 발명은 상기에 언급한 종래의 제반 문제점을 해결하기 위한 것으로 논리소자로만 구성하여 디지틀로 동작하며 동작환경에 영향이 없이 단지 외부 클럭펄스에 관계하는 펄스를 발생시키면서 리트리거링을 할 수 있는(retriggerable) 멀티바이브레이터를 만드는데 목적이 있다.The present invention is to solve the above-mentioned conventional problems, and can be retriggered by generating only a pulse related to an external clock pulse without operating the digital environment by configuring only the logic element and affecting the operating environment. The purpose is to make a multivibrator.

본 발명은 상기의 목적을 달성하기 위해 입력되는 펄스에서 천이를 검출하여 결과를 출력하는 천이 검출수단, 상기 천이 검출수단과 연결되어 입력되는 펄스에서 천이가 발생할때마다 외부에서 공급하는 클럭펄스에 관계하는 펄스를 발생시키는 펄스 발생수단, 상기 천이 검출수단의 출력과 상기 펄스 발생수단의 출력에 연결되어 입력되는 펄스에서 천이가 있을때만 펄스를 발생시키게 제어하는 단안정 제어수단으로 디지틀적으로 단안정 멀티바이브레이션을 할 수 있도록 한 것을 특징으로 하고 있다.The present invention relates to a transition detecting means for detecting a transition from an input pulse and outputting a result in order to achieve the above object, and a clock pulse supplied from the outside whenever a transition occurs in the input pulse connected to the transition detecting means. Digitally monostable multi-vibration with pulse generating means for generating a pulse, and monostable control means for generating a pulse only when there is a transition from an input pulse connected to an output of the transition detecting means and an output of the pulse generating means. It is characterized by the ability to do.

제1도에 이 회로의 동작을 상세히 설명하기 위해서 일반적인 논리소자를 사용해서 디지틀 단안정 멀티바이브레이터의 일실시예를 나타냈다.In order to explain the operation of this circuit in detail in FIG. 1, an embodiment of a digital monostable multivibrator is shown using a general logic element.

입력펄스는 D 플립플롭(U1)의 클럭펄스 입력단자(CP1)으로 입력된다. D 플립플롭(U1)의 데이터 입력단자(D1)에는 논리레벨 '1'을 입력시킨다. 따라서 입력펄스에서 천이(이하 천이는 논리레벨 '0'에서 놀리레벨 '1'로 변하는 천이)가 발생하면 D 플립플롭(U1)의 출력(Q1)은 논리레벨 '1'로 된다.The input pulse is input to the clock pulse input terminal CP1 of the D flip-flop U1. The logic level '1' is input to the data input terminal D1 of the D flip-flop U1. Therefore, when a transition occurs in the input pulse (hereinafter, the transition changes from the logic level '0' to the nolith level '1'), the output Q1 of the D flip-flop U1 becomes the logic level '1'.

외부 클럭펄스는 D 플립플롭(U2)의 클럭펄스 입력단자(CP2)와 D 플립플롭(3)의 플럭펄스 입력단자(CP3)에 각각 입력되며 D 플립플롭(U2)의 데이터 입력단자(D2)와 D 플립플롭(U2)의 데이터 입력단자(D3)에는 D 플립플롭(U1)의 출력(Q1)이 각각 입력된다. 따라서 외부 클럭펄스에서 천이가 있게 되면 D 플립플롭(U2,U3)의 출력(Q1,Q3)은 논리레벨 '1'이 된다.The external clock pulse is input to the clock pulse input terminal CP2 of the D flip-flop U2 and the flux pulse input terminal CP3 of the D flip-flop 3, respectively, and the data input terminal D2 of the D flip-flop U2. The output Q1 of the D flip-flop U1 is input to the data input terminal D3 of the D flip-flop U2. Therefore, when there is a transition in the external clock pulse, the outputs Q1 and Q3 of the D flip-flops U2 and U3 become the logic level '1'.

D 플립플롭(U1)의 출력(Q1)과 D 플립플롭(U2)의 출력(Q2)은 각각 AND 게이트(U3)에 입력된다. AND 게이트(U3)의 출력은 D 플립플롭(U1)의 리세트단자(RS1)와 D 플립플롭의 리세트단자(RS2)에 각각 연결되어 D 플립플롭(U1)의 출력(Q1)과 D 플립플롭(U2)의 출력(Q2)이 모두 논리레벨 '1'일때 D 플립플롭(U1)과, D 플립플롭(U2)을 리세트시키게 된다.The output Q1 of the D flip-flop U1 and the output Q2 of the D flip-flop U2 are respectively input to the AND gate U3. The output of the AND gate U3 is connected to the reset terminal RS1 of the D flip-flop U1 and the reset terminal RS2 of the D flip-flop, respectively, so that the output Q1 and D flip of the D flip-flop U1 are respectively. When the output Q2 of the flop U2 is all at the logic level '1', the D flip-flop U1 and the D flip-flop U2 are reset.

제2도의 디지틀 단안정 멀티바이브레이터의 타이밍도를 이용하여 디지틀 단안정 멀티바이브레이터의 동작원리를 설명한다.The operation principle of the digital monostable multivibrator will be described using the timing chart of the digital monostable multivibrator of FIG.

첫째, 디지틀 단안정 멀티바이브레이터의 펄스 입력단자에 외부 클럭펄스 입력단자로 입력되는 클럭펄스보다 주기가 긴 클럭펄스를 인가했을때 D 플립플롭(U1)의 출력(Q1)은 펄스 입력단자에 인가된 입력펄스에서 천이가 발생하면 논리레벨 '1'상태로 바뀌게 되면 이때 D 플립플롭(U2,U3)의 클럭펄스 입력단자(CP2,CP3)에 가해진 외부 클럭펄스에서 천이가 발생하면 D 플립플롭(U2,U3)의 출력(Q2,Q3)은 논리레벨 '1'이 되며 결국 AND 게이트의 출력은 두 D 플립플롭(U1,U2)을 리세트시킨다. 따라서 D 플립플롭(U3)의 출력(Q3)은 외부 클럭펄스 입력단자로 입력되는 클럭펄스의 1주기 시간간격 너비의 펄스를 발생시키게 되는데 이와 같은 동작은 디지틀 단안정 멀티바이브레이터의 펄스 입력단자에 가해진 입력펄스에서 천이가 있을때마다 반복된다.First, when a clock pulse longer than the clock pulse input to the external clock pulse input terminal is applied to the pulse input terminal of the digital monostable multivibrator, the output Q1 of the D flip-flop U1 is applied to the pulse input terminal. When a transition occurs in the input pulse, the state changes to the logic level '1'. When a transition occurs in the external clock pulses applied to the clock pulse input terminals CP2 and CP3 of the D flip-flops U2 and U3, the D flip-flop U2 The outputs Q2 and Q3 of U3 are at logic level '1' and the output of the AND gate resets the two D flip-flops U1 and U2. Accordingly, the output Q3 of the D flip-flop U3 generates a pulse of one cycle time interval width of the clock pulse input to the external clock pulse input terminal. This operation is applied to the pulse input terminal of the digital monostable multivibrator. Repeated whenever there is a transition in the input pulse.

둘째, 디지틀 단안정 멀티바이브레이터의 펄스 입력단자에 외부 클럭펄스 입력단자로 입력되는 클럭펄스보다 주기가 짧은 클럭펄스를 인가했을때 D 플립플롭(U1)의 출력(Q1)은 펄스 입력단자에 인가된 입력펄스에서 천이가 발생하면 논리레벨 '1'상태로 바뀌게 되며 때 D 플립플롭(U2,U3)의 클럭펄스 입력단자(CP2,CP3)에 가해진 외부 클럭펄스에서 천이가 발생하면 D 플립플롭(U2,U3)의 출력(Q2,Q3)은 논리레벨 '1'이 되면 결국 AND 게이트의 출력은 두 D 플립플롭(U2,U3)을 리세트시킨다. 다시 펄스 입력단자에 가해진 입력펄스에서 천이가 발생하면 D 플립플롭(U1)의 출력(Q1)은 논리레벨 '1' 상태로 바뀌게 되며 이대 D 플립플롭(U2,U3)의 클럭펄스 입력단자(CP2,CP3)에 가해진 외부 클럭펄스에서 천이가 발생하면 D 플립플롭(U3)의 출력(Q3)은 논리레벨 '1'을 유지하게 되어 단안정 바이브레이션을 하게 된다.Second, when a clock pulse whose period is shorter than the clock pulse input to the external clock pulse input terminal is applied to the pulse input terminal of the digital monostable multivibrator, the output Q1 of the D flip-flop U1 is applied to the pulse input terminal. When a transition occurs in the input pulse, the state changes to the logic level '1'. When a transition occurs in the external clock pulse applied to the clock pulse input terminals CP2 and CP3 of the D flip-flops U2 and U3, the D flip-flop U2 When the outputs Q2 and Q3 of U3 become logic level '1', the output of the AND gate eventually resets the two D flip-flops U2 and U3. When a transition occurs in the input pulse applied to the pulse input terminal again, the output Q1 of the D flip-flop U1 is changed to the logic level '1' state, and the clock pulse input terminal CP2 of the D flip-flop U2 and U3 is applied. When a transition occurs in the external clock pulse applied to the CP3, the output Q3 of the D flip-flop U3 maintains the logic level '1', thereby performing monostable vibration.

제3도는 입력되는 펄스의 양방향 천이에서 동작하는 디지틀 단안정 멀티바이브레이터에 대한 실시예인데 제2도의 회로가 입력되는 펄스의 상승 천이에서만 동작하는데 비해 제3도의 회로는 입력되는 펄스의 상승 및 하강 천이에 대해서 모두 동작하는 것만 다를뿐 제1도와 동작원리는 같다. 제3도의 실시예는 D 플립플롭(31 내지 34), AND 게이트(35,36), NOT 게이트(37), 및 OR 게이트(38)로 구성되어 있다.FIG. 3 is an embodiment of the digital monostable multivibrator operating in the bidirectional transition of the input pulse. The circuit of FIG. 3 operates only in the rising transition of the input pulse. The first principle and the operating principle are the same except that all of them operate. The embodiment of FIG. 3 consists of D flip-flops 31 to 34, AND gates 35 and 36, NOT gate 37, and OR gate 38.

제4도는 외부 클럭펄스의 반주기 펄스폭을 출력하는 디지틀 단안정 멀티바이브레이터에 대한 실시예인데 제1도의 회로가 멀티바이브레이터에서 출력되는 펄스의 폭이 외부 클럭펄스의 주기와 같은 것과는 달리 제4도의 회로는 멀티바이브레이터에서 출력되는 펄스의 폭이 외부 클럭펄스 주기의 반이라는 것만이 다를뿐 제1도와 동작원리는 같다. 제4도의 실시예는 D 플립플롭(41 내지 44), OR 게이트(45), AND 게이트(46), 및 NOT 게이트(47)로 구성되어 있다.4 is an embodiment of a digital monostable multivibrator that outputs the half-period pulse width of an external clock pulse. The circuit of FIG. 1 differs from the circuit of FIG. 1 in that the width of the pulse output from the multivibrator is equal to the period of the external clock pulse. The operation principle is the same as that of FIG. 1 except that the width of the pulse output from the multivibrator is half the period of the external clock pulse. The embodiment of Fig. 4 is composed of D flip-flops 41 to 44, OR gate 45, AND gate 46, and NOT gate 47.

본 발명은 상기와 같이 간단한 논리소자를 사용하여 디지틀 방식으로 동작하는 멀티바이브레이터로 종래의 멀티바이브레이터와 대체해서 사용할 수 있으며 다음과 같은 특유의 효과를 갖는다.The present invention is a multivibrator operating in a digital manner using a simple logic element as described above can be used in place of the conventional multivibrator and has the following unique effects.

첫째, 디지틀로 동작하기 때문에 동작 환경에 영향을 받지 않는다.First, because it operates digitally, it is not affected by the operating environment.

둘째, 간단한 논리소자로 구성되어 있고 또한 안정되게 동작하기 때문에 저속 및 고속에서 모두 사용이 가능하다.Second, since it is composed of simple logic elements and operates stably, it can be used at both low speed and high speed.

세째, 간단한 논리소자로 구성되어 있어 집적화가 가능하다.Third, since it is composed of simple logic elements, integration is possible.

네째, 같은 회로를 병렬로 여러개 구성하여 외부 클럭을 다양하게 인가하면 클럭펄스 주기감지, 동기펄스 검출 등 응용이 광범위하다.Fourth, when the same circuit is configured in parallel and variously applied to an external clock, applications such as clock pulse period detection and synchronous pulse detection are widely used.

Claims

Transition detection means for detecting a transition from an input pulse and outputting a result, and a pulse having a pulse width of a clock pulse period supplied externally whenever a transition occurs in an input pulse connected to the transition detection means. The pulse generating means generates a pulse if the transition means is generated at least once within a period of an externally supplied clock pulse from a pulse connected to the output of the transition detecting means and the output of the transition detecting means. And a monostable control means for controlling the pulse generating means so as not to generate a pulse so that the monostable multivibration can be performed digitally.

The method of claim 1, wherein the transition detecting means includes a first flip-flop, a logic level 1 is input to a data input terminal of the first flip-flop, and a pulse to be input is input to a clock pulse input terminal. The pulse generating means includes one second flip-flop, inputs the output of the first flip-flop of the transition detecting means to the data input terminal of the second flip-flop, and inputs an external clock pulse to the clock pulse input terminal. The monostable control means includes one third flip-flop and one AND gate, and inputs the output of the first flip-flop of the transition detection means to the data input terminal of the third flip-flop, and to the clock pulse input terminal. An external clock pulse is input, and the AND gate input has an output of the first flip flop of the transition detecting means and a third flip of the monostable control means. Respectively the output of each drop and to the output of the AND gate to the reset terminal and the reset terminal of the third flip-flop of the monostable control means of the first flip-flop of the shift detection means; A digital multivibrator, wherein an external clock pulse generates a pulse having a pulse width of one periodic time interval whenever an rising transition occurs in an input pulse.

The method of claim 1, wherein the transition detecting means includes a first flip-flop, a logic level 1 is input to a data input terminal of the first flip-flop, and a pulse to be input is input to a clock pulse input terminal. The pulse generating means includes two second, third flip-flops, an AND gate, an OR gate, and a NOT gate, respectively, and the output of the first flip-flop of the transition detecting means is supplied to the data input terminal of the second flip-flop. An external clock pulse to a clock pulse input terminal, an output of the first flip flop of the transition detection means to a data input terminal of the third flip-flop, and an external clock passing through the NOT gate to a clock pulse input terminal. A pulse is input and an output of the second flip flop and an output of the third flip flop are respectively input to an input of the AND gate. The output of the trap is input to the reset terminals of the second flip-flop and the third flip-flop, and the output of the second flip-flop and the output of the third flip-flop are respectively input to the OR gate input terminal. The means includes one fourth flip-flop and one AND gate, and inputs the output of the first flip-flop of the transition detecting means to the data input terminal of the fourth flip-flop, and an external clock pulse to the clock pulse input terminal. The output of the first flip flop of the transition detecting means and the output of the fourth flip flop of the monostable control means are respectively input to the AND gate input, and the output of the AND gate is connected to the first flip flop of the transition detecting means. Inputting the reset terminal and the reset terminal of the fourth flip-flop of the monostable control means, respectively; A digital multivibrator, comprising generating a pulse having a pulse width of a half cycle time interval of an external clock pulse whenever a rising transition occurs in an input pulse.

2. The system of claim 1, wherein the transition detecting means includes two first and second flip flops, one NOT gate and one OR gate, respectively, and a logic level 1 is input to a data input terminal of the first flip flop and a clock pulse is generated. An input pulse is input to an input terminal, a logic level 1 is input to a data input terminal of the second flip-flop, a pulse that is NOT gated to an input pulse of a clock pulse input terminal is input, and an input of the first, The output of the second flip-flop is input respectively, and the pulse generating means includes one third flip-flop, and the output of the OR gate of the transition detecting means is input to the data input terminal of the third flip-flop and the clock pulse is input. An external clock pulse is input to the input terminal, and the monostable control means includes one fourth flip-flop and one AND gate. The output of the OR gate of the transition detection means is input to the data input terminal of the fourth flip flop, the external clock pulse is input to the clock pulse input terminal, and the output of the first flip flop of the transition detection means is input to the AND gate input. Resetting the fourth flip-flop of the first and second flip-flops of the transition detecting means and the output of the fourth flip-flop of the mono-stable control means, respectively, and the output of the AND gate. Input to terminals respectively; A digital multivibrator, comprising: generating a pulse having a pulse width of one cycle time interval of an external clock pulse whenever a rising or falling transition occurs in an input pulse.