KR920010514B1 - Digital signal processing apparatus - Google Patents

Abstract

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Description

Digital Signal Processing Equipment

1 is a block diagram showing the configuration of a digital signal processing apparatus according to an embodiment of the present invention.

2 is a flowchart for explaining the operation of the digital signal processing apparatus of the present invention.

3 is a block diagram showing an image encoding system according to an embodiment of the present invention.

4 is an explanatory diagram showing the relationship between the processing time and the effective block rate.

5 is a functional block diagram showing a configuration of a motion compensation interframe encoding apparatus according to the present invention.

6 is a functional block diagram showing an internal configuration of a motion compensation unit.

7 is a flowchart illustrating the operation of the present invention.

8 is a diagram for explaining average value pattern calculation.

9 is a diagram illustrating detection of a motion vector using the average value pattern of the first stage.

10 is an explanatory diagram of arrangement of search motion vectors when motion vectors are detected by an average value pattern.

11 is a diagram illustrating detection of a motion vector of the second stage in a search range defined by motion vector detection of the first stage.

12 is a block diagram showing the configuration of an apparatus for implementing an image encoding transmission method according to an embodiment of the present invention.

13 is an explanatory diagram for explaining a subsample.

14 is a block diagram showing the configuration of a conventional digital signal processing apparatus.

15 is a flowchart for explaining the operation of the conventional digital signal processing apparatus.

16 is an explanatory diagram of limit processing.

17 is a block diagram showing an example of the configuration of a typical high efficiency coding algorithm.

18 is a block diagram showing a conventional image encoding system.

19 is an explanatory diagram showing the relationship between the processing time and the effective block rate.

20 is a functional block diagram showing the configuration of a conventional inter-frame encoding apparatus.

21A and 21B are explanatory diagrams of a conventional motion vector detection method.

22 is an explanatory diagram of a conventional full search type motion vector detection method.

23 is an explanatory diagram of a conventional tree search type motion vector detection method.

Fig. 24 is a block diagram showing the structure of an apparatus for implementing the conventional image encoding transmission method.

25 is an explanatory diagram for explaining an image data division operation by a conventional image encoding transmission method.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus that executes a limit process on arithmetic result data. In particular, an image encoding apparatus for processing a large amount of image signals at high speed, a motion compensation inter-frame encoding apparatus, and in particular, a calculation amount of motion compensation is reduced. A suitable motion compensation inter-frame encoding apparatus and an image encoding transmission apparatus for dividing an input image data, encoding the divided image data in parallel, and combining and transmitting the image data in parallel again.

14 shows, for example, T. Murakami et al, A DSP ARCHITECTURE FOR 64 KBPS MOTION VIDEO CODEC, INTERNATIONAL SYMPOSIUM ON CIRCUIT AND SYSTEM (ISCAS88), pp. 227-230, 1988 " is a block diagram showing a simplified configuration of a conventional digital signal processing apparatus, wherein (1) is an instruction memory for storing instructions of a micro program, and (2) is the instruction memory. A command execution control unit for reading and decoding an instruction in (1) and executing operation control such as an operation, (3) a data input bus mainly for transmitting data and control signals, and (4) a plurality of memory for storing operation data. A data memory having an input / output port of (5) is a data calculation section for performing various operations on data of up to two inputs transmitted from the data memory (4) via a data input bus (3). An address generator (7) which independently generates the addresses of the two input and one output data of the data operator 5, and (7) are data output buses that transmit the data operation result data.

Next, the operation will be described using the flowchart of FIG. In this example, the data operation section 5 executes an arbitrary two terms operation on two input data of n (n> 0 integer) bits, and then m (≤ n) for this operation result data (n bits). The case where limit processing is performed with the number of valid bits as the number of valid bits will be described.

First, the command execution control unit 2 notifies the command memory 1 of the address indicated via the address path 101, and reads the corresponding command from the command memory 1 via the data path 102. In addition, the command execution control unit 2 decodes the read command, notifies the address generation unit 6 of the control signal via the data path 104, and transmits data or the like to the data path 103 as necessary. The data is sent to the data input bus 3.

By this control signal, the address generating section 6 notifies the data memory 4 of the two input data (n bits each) required for the operation via the data path 107, and this data memory 4 corresponds to the corresponding data. 2 input data are sent to the data input bus 3 via the data path 105. The data operation unit 5 inputs the two input data sent to the data input bus 3 via the data path 106, and the predetermined two pieces of data which are instructed by the command execution control unit 2 via the data path 103. The arithmetic processing of the term is executed, and the arithmetic result data (n bits) is sent to the data output bus 7 via the data path 108. The operation result data sent to the data output bus 7 is input to the data memory 4 via the data path 109 and is given by the address generator 6 via the data path 107. It is stored in (step ST1). Next, the data operation unit 5 inputs the operation result data stored in the data memory 4 via the data path 106 again by the above-described input operation, and enters the instruction set instructed by the instruction execution control unit 2. Execute one MAX instruction (m bits of significant bits). In this MAX instruction, it is determined whether or not the operation result data exceeds the maximum value t by the instruction that outputs the larger of the result value and the maximum value that can be expressed in m bits. Next, the limit processing is executed, and the operation result data of executing the MAX instruction by the above-described output operation is stored in the data memory 4 (step ST2).

In addition, the data operation unit 5 inputs the operation result data of the MAX instruction stored in the data memory 4 via the data path 106 again by the above-described input operation, and executes the MIN instruction which is one of the instruction sets. (Mbits of significant bits) are executed. In this MIN instruction, it is determined whether the operation result data is smaller or smaller than the minimum value S by a command outputting the smaller of the operation result data and the minimum value that can be expressed by the number of effective bits m bits. The operation result data on which this MIN instruction is executed by the above-described output operation is stored in the data memory 4 (step ST3), and the processing ends.

Next, the above limit processing will be described using FIG. First, n-bit operation result data (MSB is the most significant bit and LSB is the least significant bit) is taken into account (Fig. 16A). In the case of limit processing to the effective number of m (m <n) bits, the upper (nm) bit is the same data as the MSB, and the remaining m bits are m as they are if the value of the result data is within the range that can be expressed in m bits. If the bit data exceeds the maximum value that can be expressed in m bits, the maximum value is smaller than the minimum value that can be expressed in m bits. The minimum value is m bit data (Fig. 16B).

In addition, the limit processing in which the effective number of bits is m = n has the same effect as when the limit processing is not executed.

FIG. 18 is a block diagram showing a conventional image encoding system disclosed in, for example, "Realtime Video Signal Processor Module" (ICSSP'87) Preliminary Proceedings (Dallas, April 1987, p. 1961-1964). In the drawing, reference numeral 11 denotes an input terminal to which input data is input, and 12 are connected to the input terminal 11 via an input bus, and a plurality of (M) processors for performing signal processing operations on the input data. And (13) are output terminals to which the processing results of these processors 12 are output via the output bus. Reference numeral 29 denotes screen data for one frame input from the input terminal 11, and 30 denotes small screen data obtained by region-dividing the screen data 29 for one frame.

17 is a block diagram showing a typical example of a high efficiency coding algorithm of a motion picture screen to be processed. In the drawing, reference numeral 11 denotes an input terminal, 20 denotes a motion compensator for performing motion compensation of input data on the input terminal 11, and 21 denotes data and an input terminal 11 on the motion compensator 20. (B) is a block identifier that divides the data in the interframe difference 21 into valid block data and invalid block data, and (23) is a block identifier 22. An encoder / decoder for encoding / decoding an effective block data of (24) is an interframe adder for adding decoding data in the encoder / decoder 23 and data from the motion compensator 20, (25). Is an encoding frame memory for storing data in the interframe adder 24, 26 is a front end processor including a motion compensator 20 and an interframe difference 21, 27 is an encoder / decoder ( 23) and a post-processing unit including an interframe adder 24, Reference numeral 28 denotes an output terminal on which the processed output data is output.

Next, the operation will be described. This image encoding system targets signal processing of a motion image, divides one screen data 29 into M small screen data 30, and assigns them to each processor 12. FIG. Each processor 12 spends one frame time to fetch the small screen data 30 of the area in charge.

Next, each processor 12 consumes one frame time to execute a predetermined process, and outputs the processing result to the output bus in synchronization with the other processors 12. At this time, the individually processed small screen data 30 is assembled again in units of one frame.

In the above processing method, the processing time T per frame when processing one frame into M pieces is

Tf: Processing time per frame in one processing unit

Tfn: Processing time per small screen of the nth processing unit

Is given in. In this case, even by using a relatively low speed as the processor 12 by increasing the number of divisions, high-speed image processing is possible, while the overall processing speed is determined by the processing speed of the slowest processor 12.

In the algorithm of the high-efficiency encoder of the motion picture screen to be processed as shown in FIG. 17, motion compensation by the motion compensator 20 is performed on all input data input from the input terminal 11, and inter-frame is performed. After the difference processing with the input data is executed in the difference unit 21, only the valid blocks extracted by the block identifier 22 are sent to the encoder / decoder 23 for encoding / decoding. The relationship between α and the processing time T of the small screen is

a, b: integer

B _N : Number of blocks in small screen

Is displayed.

19 shows this equation (2). In the conventional image encoding apparatus, since each processor 12 performs input and output in synchronization, it is necessary to uniformly allocate the maximum processing time to each processor 12, resulting in an empty time for an area indicated by diagonal lines in the drawing.

20 to 22 are described in, for example, the document `` Inter-frame Coding Method Using Motion Compensation and Background Prediction '' (Journal of the Institute of Electronics and Telecommunications '85 / 1 Vol.J68B No.1 p.77 ~ 84, A. Kuroda, It is explanatory drawing of the conventional motion compensation calculation method disclosed by Wanaozu and Co., Ltd. Hashimoto), and especially illustrates the whole search type | mold method.

In the figure, reference numeral 31 denotes an input signal of image data, 32 an input frame buffer for storing one input data once, and 33 a block size for motion compensation at a predetermined position in the current input frame. The current input block having L1 × L2, 34 indicates a range L1 + 2m and L2 + 2n in which a block to be subjected to matching processing with the current input block 33 in the previous input frame playback data exists. Motion vector search range.

In this case, the number of blocks to be searched for M is

The search range is in the range of -m to + m pixels in the horizontal direction and in the range of -n to + n pixels in the vertical direction.

Motion compensation is a process of obtaining a prediction signal close to the current input frame data by using a correlation between the frames of the current input frame data and the previous input frame reproduction data in the unit of a predetermined size in the inter-frame coded transmission method. It is.

Then, the block having the smallest amount of distortion between blocks due to a condition that has the highest correlation with the current input block 33 in the current input frame data, that is, the minimum absolute difference value, etc., is used to determine the motion vector of the previous input frame playback data. In the search range 34, a motion vector and a prediction signal are obtained.

In the figure, reference numeral 35 denotes a motion for obtaining a prediction signal by correlation approximation calculation between the current input block 33 of the input signal 31 and the motion vector search range 34 given as the previous input signal reproduction data. The compensator 36 is a prediction signal output from the motion compensator 35 and 37 is motion vector information output from the motion compensator 35.

Further, reference numeral 39 denotes an encoder which encodes the difference signal 38 between the input block signal 33 and the predictive signal 36 and outputs the encoded signal 40. The encoder 41 encodes by the encoder 39. The decoding unit decodes the encoded coded signal 40.

Then, 44 adds the decoded signal 42 of the decoder 41 and the predictive signal 36 of the motion compensator 35 to return to the reproduction data 43 to store this, and simultaneously compensates for the motion. The frame memory which gives the unit 35 a motion vector search range 34, 45 is a transmission buffer, and 46 is a transmission signal.

Subsequently, the operation will be described with reference to FIGS. 21 and 22. FIG.

Interblock distortion between M blocks in the motion vector search range 34 during the previous input frame playback data for a block X of size L1 × L2 at a specific position in the current input block 33 in the current input frame. Calculate the amount, calculate the relative position with respect to the position of the current input block 33 of the minimum distortion block yi that gives the minimum distortion, that is, the minimum distortion, i.e., predict the signal ymin of this block yi The signal is output as the signal 36.

In inter-frame coded transmission, the prediction signal 36 can also be generated on the receiving side of the signal.

For example, if the number of motion vectors V to be searched within the given motion vector search range 34 is M (an integer of 2 or more), the previous frame block at the position of the specific motion vector V and the current input block. If the difference absolute value sum is used as the distortion amount with

It becomes Here, the input block is

The block to be searched is

이다.

to be.

And the motion vector V is

Obtained by

In this case, the amount of calculation S1 assumes that the absolute difference value sum calculation is a machine cycle and the comparison process is b machine cycle.

It becomes

Here, for example, when a = 1 machine cycle, b = 2 machine cycles, l1 = 8, l2 = 8, m = 8, n = 8, L = 64, M = 289,

It becomes a mechanical cycle. This calculation amount S1 is a considerably large value in terms of the hardware configuration, and a high speed computing system such as pipeline processing is used in accordance with the period of the frame which is an image signal.

However, the hardware simplification is a big problem. For example, in the TV signal motion compensation inter-frame encoding device of Japanese Patent Laid-Open No. 63-181585, a tree search type motion compensation is performed to reduce the amount of computation. A method of performing an operation has been proposed.

In the tree search type motion compensation operation method, as shown in FIG. 23, the first search target block (○) having a low density is arranged at equal intervals within the motion vector search range 34, and the least distortion is given. When a block? Is detected, a second search target block? Is arranged in a narrow area centered on the block?, And a block? Giving the least distortion is detected therefrom, and the block? In the area centered on, the third search target block Δ is set to detect the block Δ that gives the minimum distortion, and finally, the block Δ that gives the minimum distortion within the motion vector search range 34 is specified. Is that.

In this case, the amount of calculation S2

It becomes Therefore, under the conditions as described above

It is a machine cycle, and this tree search type motion compensation operation method can be finished with less calculation amount than the full search type.

FIG. 24 also illustrates a conventional image code and a transmission scheme disclosed in, for example, "A Real-time Video Signal Processor Suit able for Motion Picture Coding Applications" (IEEE GLOBCOM '87, pp. 453-457, 1987). A block diagram showing the structure of an encoding apparatus is shown in Fig. 61, where input image data, 62 are arranged in parallel, and a digital signal processing processor (hereinafter referred to as DSP) that performs encoding in parallel. Reference numeral 63 denotes a data transmission controller which controls data division and transmission to each DSP 62, 64 transmission data transmitted from the data transmission controller 63 to each DSP 62, and 65 denotes the above. Processed data processed by each DSP 62.

Next, the operation will be described.

The input image data 61 of one frame is distributed to each of the DSPs 62 by the data transfer controller 63 and transmitted. The transferred data 64 is processed in each DSP 62, and then transferred to the next processing block as the processed data 65. At this time, the processing sharing area of each DSP 62 is shown in FIG. 25A. This figure is an example of dividing when the input image data 61 is divided into four of A, B, C, and D, and the parallel processing is executed in the DSP 62, respectively, and the processing is equally distributed in each of the DSP 62. FIG. do. The four areas are put together in one frame of the input image data 61.

Here, the case where the input image data 61 is encoded by the inter-frame image encoding method or the like is considered. In the inter-frame image encoding method, it is common to use a conditional pixel replenishment process that uses only a portion of a certain size whose difference between the input frame and the previous frame is the encoding target. Therefore, even if the actual effective pixel rate is different even though the number of pixels in the processing share area in each DSP 62 is the same, the amount of computation required for processing is different and the required computation amount or computation time is proportional to the effective pixel rate.

FIG. 25B is an example of distribution of the effective pixels in the case where the input image data 61 is divided into four parts A, B, C, and D, as shown in FIG. 25A, in the inter-frame coding method. The required computation time of each DSP 62 per block is the processing time of the DSP 62 with the most effective pixels. Therefore, in the above-described conventional digital signal processing apparatus, it is necessary to execute three instructions including an operation in order to execute the limit processing on the operation result data, and there is a problem that the processing efficiency decreases.

In addition, in the above-described conventional image encoding apparatus, in the process where the processing time causes a difference, it is necessary to uniformly set the allocation of processing time for each of the processors 12, even though there is room in processing capacity. Nevertheless, there have been problems such as an increase in the number of processors unnecessarily.

Further, in the conventional motion compensation calculation method described above, if the entire search with high certainty is to be executed by the motion compensation calculation, the amount of calculation increases and the hardware configuration becomes large, while the amount of calculation decreases due to tree search, etc. When the detection performance of the block is deteriorated, that is, the block at a position away from the original minimum distortion block may be selected during the matching process at the time of the first low density search, and the correlation does not reach the target minimum distortion amount. There have been problems such as an increase in cases in which no determination is made and the inefficient transmission cannot be accepted.

In the conventional image coding transmission apparatus described above, when there is a bias in the effective number of pixels within the input image data of one frame or a time variation in its distribution, this processing time is the area that requires the most processing time, that is, the DSP. Depending on the processing time, there is a problem that the processing efficiency of the entire frame is reduced, and when the coding process spans each processing area, the processing complexity between the DSPs is caused.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and to provide a digital signal processing apparatus that executes an efficient limit process.

It is a second object of the present invention to provide an image encoding apparatus capable of efficient processing in a smaller number of processors.

It is a third object of the present invention to provide a motion compensation interframe coding apparatus capable of miniaturizing hardware by reducing the amount of computation without degrading the detection performance of the least distortion block.

A fourth object of the present invention is to enable an equalization of processing time of each DSP by parallel configuration of DSPs, and at the same time to connect to a low resolution receiver and reduce the buffer capacity for receiving. To provide.

The digital signal processing apparatus according to the present invention is a limit processing unit for inputting operation result data in which an arbitrary operation is executed in the data computing unit, and executing a limit process with an arbitrary number of valid bits instructed by the instruction execution control unit in accordance with the contents of the microprogram. It is to be provided.

The digital signal processing apparatus of the present invention inputs the output of the data calculating section directly to the limit processing section, thereby enabling calculation and limit processing in one instruction.

The image encoding apparatus according to the present invention divides the encoding process into a process for which the entire pixel of the input data is a code object, a process for which only the effective block is a code object, a front end multiprocessor in charge of the former, and a rear end multiprocessor in charge of the latter. Between the buffers buffering the processing time difference before and after, and the threshold value control, the amount of encoding data generated by the front end multiprocessor is constantly limited, and the throughput of the subsequent multiprocessor is kept constant according to the data accumulation amount of the buffer. It has an output control section, has a function of adding data information to a front end multiprocessor, and has a function of decoding the data information to a rear end multiprocessor.

The image encoding apparatus according to the present invention has a threshold value of encoding in which an output control unit is executed by a front end multiprocessor by an amount of data stored in a buffer placed between a front end multiprocessor encoding an entire pixel and a rear end multiprocessor encoding only an effective block. By adjusting the number of blocks and controlling the number of effective blocks uniformly, the excessive processing burden on the subsequent multiprocessors is reduced, thereby reducing the number of processors required throughout the system.

The motion compensation inter-frame encoding apparatus according to the present invention divides a current input frame of digital image data consisting of several frames sequentially input in time series into a plurality of blocks, and changes the current input frame to each block of the image data of the current input frame. A small block having a size that can be equally divided into blocks to be coded beforehand when calculating the approximation between patterns between blocks in the input frame playback data of and detecting the motion vector and the block with the least distortion. Average value block), the average value of these average block units is obtained for one frame, and has a predetermined size centering on the position of the encoding target input data block that is the motion vector search range in the previous frame playback data. Set the motion vector search range of 1.

Then, the first search motion vector group of n (n is an integer of 1 or more) is arranged at a low density so as to be equal in the first search range, and the average value of the average value block in the block data at the position representing this motion vector is obtained. An average value distortion amount representing the pattern similarity between the average value pattern consisting of the average value pattern and the average value pattern in the input data block that is the current input block is obtained for each motion vector.

Then, a block having a minimum mean distortion amount is detected in the first search area, and a second motion having a size smaller than the first search range centering on the mean minimum distortion block having the minimum mean distortion amount. The vector search range is set as the limited search range, and the second search motion vector group is arranged at a high density within this second search range.

Also, a block closest to the input data block is detected in accordance with the minimum distortion amount using pixels, according to the second motion vector group, and the block and the motion vector which obtain this minimum distortion are used as the final prediction signal and the motion vector. It is configured to

According to the above-described configuration, the motion compensator detects, as a minimum distortion block, a block in which the search target blocks are arranged at a low density within the motion vector search range and the minimum amount of distortion between the average value patterns of these blocks is calculated in the motion vector to be calculated. Presence position of the minimum distortion block at high precision by setting the limited search range as a high density search target block centering on the minimum distortion block, detecting a motion vector among the blocks, and first comparing the amount of distortion in the average value pattern Compression can be performed, and then, by performing a high-density motion vector search within the limited area, detection of high precision is performed while suppressing the calculation amount.

The image encoding transmission apparatus according to the present invention intermittently divides the pixels constituting one frame of image data into n (integers of one or more) pixels per frame intermittently so as not to overlap each other. However, hereinafter, referred to as subsample) data, and sequentially transmitted subsample image data is inputted for one frame, and the n (one frame) subsample image data are encoded in parallel by n encoding processing units. Coded image data is created, and all of the n coded image data or only the number of n pieces of the n coded image data corresponding to the resolution are arbitrarily selected (same as optional) according to the resolution of the receiving side apparatus, and then synthesized. Sub-sample m again and send headers sequentially so that m (integer or more) coding units can be coded in parallel It will have to.

The image encoding transmission apparatus according to the present invention sequentially inputs subsample image data obtained by subsampled image data every frame for one frame, and encodes them in parallel by the encoding processing unit, so that the number of effective pixels of the subsample image data to be processed is increased. Is equalized. In addition, the encoded coded image data were synthesized in accordance with the receiving side apparatus, and at the time of transmission, they were subsampled again in accordance with the number of encoding processing units of the receiving side apparatus, and the respective headers were sequentially transmitted. Time eliminates the time gap between the receiving operation and the encoding process.

EMBODIMENT OF THE INVENTION Hereinafter, 1st Embodiment of this invention is described according to drawing.

FIG. 1 is a block diagram showing the configuration of a digital signal processing apparatus according to an embodiment of the present invention. The same or corresponding portions as those in the conventional digital signal processing apparatus (FIG. 14) are denoted by the same reference numerals, and description thereof will be omitted.

In Fig. 1, reference numeral 8 denotes a valid input of arithmetic result data output from the data computing section 5 via the data path 108, and instructed via the data path 110 in the command execution control section 2; It is a limit processing unit that limits processing by the number of bits.

Next, the operation will be described using the flowchart shown in FIG. In this example, the arithmetic processing of any two terms is executed by the data operation section 5 on two input data of n (n> 0 integer) bits, and then the arithmetic processing of any two terms is executed from this calculation result (5). After execution, a description will be given of a case where a limit process is executed in which the number of bits (an integer of n? N) of the operation result data (n bits) is the number of valid bits.

First, the command execution control unit 2 notifies the command memory 1 of the indicated address via the address path 101, decodes the corresponding command, and transmits a control signal to the address generation unit 6 via the data path 104. FIG. In addition, the data is sent to the data input bus 3 via the data path 103, and the number of valid bits is notified to the limit processing section 8 via the data path 110 as necessary.

By this control signal, the address generating section 6 notifies the data memory 4 of the two input data (n bits each) required for the operation via the data path 107, and this data memory 4 corresponds to the corresponding data. 2 input data are sent to the data input bus 3 via the data path 105. The data calculating section 5 inputs the two input data sent to the data input bus 3 via the data path 106 and the two predetermined terms indicated by the command execution control section 2 via the data path 103. The arithmetic processing is executed (step ST4), and the arithmetic result data (n bits) is directly output to the limit processing section 8 via the data path 108. The limit processing unit 8 then limits the operation result data to the effective number of bits m bits indicated by the instruction execution control unit 2 via the data path 110, and the limit processing unit data is processed into the data path 111. The data is output to the data output bus 7 via. The arithmetic result packet sent to the data output bus 7 is input to the data memory 4 via the data path 109, and is again given to the address via the data path 107 by the address generator 6 again. Are stored in step S5 (step ST5). By the above operation, operation and limit processing can be executed by one instruction.

Next, a second embodiment of the present invention will be described with reference to the drawings. In Fig. 3, reference numerals 11 and 13 denote the above-described input terminals and output terminals, and reference numeral 14 denotes an input frame memory in which input data input from the input terminal 11 is stored. 15 is a front end multiprocessor composed of several processors 12 connected to the input frame memory 14 and expandable in parallel in accordance with the throughput, and targets all pixels of the input data input from the input terminal 11. It is in charge of the encoding process, and has a function of adding valid / invalid block information and position information in a frame to block data. Similarly, 16 is a rear end multiprocessor composed of several processors 12 expandable in parallel in accordance with the throughput, and is responsible for processing only the effective block of input data input from the input terminal 11 as the encoding target. The processor 15 has a function of identifying valid blocks and reconstructing frames from valid / invalid block information and positional information added to the block data.

17 is disposed between the front end multiprocessor 15 and the back end multiprocessor 16, and stores the encoded data output from the front end multiprocessor 15, and at the same time, the multiprocessor 15 and the back end multiprocessor 16 This buffer buffers the difference in processing time. 18 is connected to the rear end multiprocessor 16 to receive encoded data, sends feedback data to the front end multiprocessor 15, adjusts the threshold value for controlling the amount of generation of the encoded data, and the front end multiprocessor 15 The number of effective blocks is changed constantly according to the amount of data stored in the buffer 17, the throughput of the subsequent multiprocessor is kept constant, and the output data is sent to the output terminal 13. Output control part. Similarly, reference numeral 19 denotes an encoded frame memory FM which stores decoded data connected to the subsequent multiprocessor 16 and is sent to the front end multiprocessor 15 during the next frame processing.

Reference numeral 171 denotes block data processed by the front end multiprocessor 15 and stored in the buffer 17, and 172 is a parameter added to each block data 171 to indicate an attribute of data.

Next, the operation will be described. In the encoding process of the present invention, in the case of dividing into a front end process before performing a conditional pixel supplementation and a post end process thereafter, the relationship between the effective block rate α and the processing time T of the front end process and the post destination is expressed by the following equation. Indicates.

Shearing

C: integer

Post-processing

A: integer

Equations (3) and (4) are shown in FIG. In the figure, the encoding process is largely divided into a front end process in which the processing time is constant and a post end process in proportion to the effective block rate α, regardless of the processing time characteristics. In the present invention, the front end process and the post end process are separately processed by the front end multiprocessor 15 and the rear end multiprocessor 16 which are expandable in parallel in accordance with respective throughputs.

In other words, the input data input from the input terminal 11 and stored in the input frame memory 14 is subjected to the front end processing such as motion compensation and conditional pixel supplement by the processing unit in the front end multiprocessor 15, and the processing result. Is output to the buffer 17. Each processor 12 constituting the front end multiprocessor 15 inputs block data from the input frame memory 14 in the order of completion of processing. Since the processing time of each processor 12 at this time varies depending on the block data, the output order to the buffer 17 does not match the scanning order of the input frame memory 14. Therefore, the data output from each processor 12 of the front end multiprocessor 15 to the buffer 17 is a data structure in which the position information indicating the position in the frame is added and the valid / invalid information and the type information of the data are also added. do.

The block data stored in the buffer 17 is subjected to post-sequence processing such as vector quantization, discrete COS conversion, and decoding by the subsequent multiprocessor 16. The encoded data is output to the output controller 18, and the decrypted data is encoded frames. Outputted to the memory 19, respectively. At this time, the process is executed only for the valid block with reference to the data additional information. Decoded data stored in the encoded frame memory 19 is sent to the front end multiprocessor 15 for use in encoding the next frame. The output controller 18 sends the feedback data to the front end multiprocessor 15 to control the threshold value for the front end process, and constantly limits the amount of encoding data generated. In addition, the output control unit 18 monitors the amount of data in the buffer 17, changes the number of effective blocks in accordance with the amount of data accumulation, and reduces the load of the rear end multiprocessor 16 by constantly limiting the throughput of the post processing.

In addition, the processing time difference T ₁ -T ₂ between the front end processing time T ₂ and the post end processing time T ₁ shown in FIG. 17), the buffering system is buffered by the front end processor 15 to realize processing performance close to the maximum processing capacity of the front end multiprocessor 15 and the rear end multiprocessor 16. FIG. As a result, the loss due to the free time for the area indicated by the oblique line in FIG. 19 can be eliminated in the entire encoding process.

Next, a third embodiment of the present invention will be described with reference to FIG.

5 is a block diagram of a motion compensation interframe encoding apparatus. In the figure, reference numeral 47 denotes pixels in the average value block in units of small blocks (average value blocks) of a predetermined size capable of equally dividing a block of size L1 x L2 used for motion compensation for one frame of a playback frame. An average value calculation circuit for obtaining the average value 48 of the block, 49, is an average value frame memory which holds the average value 48 in the average value block unit for one frame.

6 is an internal configuration diagram of the motion compensator 35. In the drawing, reference numeral 51 denotes an average value calculation circuit for calculating an average value 48 of the average value block unit within an encoding target input block. Is an input average value memory which holds each average value of the average block in this input block as a pattern.

Further, reference numeral 54 denotes an average value pattern matching circuit for performing distortion calculation between the average value pattern of the input block and the average value pattern in the average frame memory 49 and detecting the minimum distortion block. And a pixel pattern matching circuit that calculates the position of the least distortion block by calculating the inter-image distortion amount between the block and the block in the search range in the frame memory.

8 and 9 are explanatory diagrams of a first-stage motion vector detection method based on the average value pattern minimum distortion. In the drawing, reference numeral 50 denotes a search range of a reproduction frame average value pattern, and 52 denotes an average value of an input block. The pattern (57) is an average value block.

Subsequently, the operation of the present invention will be described.

The input signal 31 is encoded by the encoding unit 39 and decoded by the decoding unit 41 by the same operation as in the prior art to form the decoding reproduction data 43. The decoding reproduction data 43 is similar to the conventional one. At the same time as being stored in the frame memory 44, one frame is divided into an average value block 57 having a size of k1 x k2, and the average value of pixels can be obtained for each average block (see FIG. 5).

If the average block at this time is sized to equally divide a block of size L1 × L2 used for motion compensation, the average value of J (J = L1 × L2) / (k1 × k2) in the L1 × L2 block. This exists.

The pixel average values aj (j = 1 to J) in each average block at this time are collected and treated as one pattern A. FIG.

That is, A = {a1, a2,... aJ}.

Subsequently, in the motion vector detection method, as shown in the flowchart of FIG. 7, the minimum distortion block is searched for according to the size of the average value block by the arrangement interval of the search motion vectors (step ST11) (see FIG. 10). ).

For the input block 33, the average value pattern 52 is calculated by the average value calculating circuit 51, and the average value pattern 52 is calculated between the input block average value pattern and the average value pattern of all frames corresponding to the block of the position of the motion vector. The average distortion pattern matching circuit 54 for matching distortion calculation and minimum distortion block detection is executed (step ST12) (see Fig. 9).

The average distortion amount is represented by the following formula.

Further, the input block average value pattern A = {a1, a2,... aJ}, playback frame average value pattern Ay = {ay1, ay2,... ayJ}.

At this time, the average value pattern matching is used to calculate the average value for each input block and playback frame block, thereby making the machine cycle l1 × l2 and the J machine cycle per average pattern matching.

Therefore, in the first stage search, the required calculation amount C1 is

It becomes M1 is the number of motion vectors in the first stage.

Next, the motion detection step in the pixel pattern matching circuit 56 measures the size of m1 x n1 centering on the minimum distortion block 58 obtained by the average value pattern matching circuit 54 as shown in FIG. The defined search range 59 is set, and motion vectors to be searched with high density are arranged within this range (step ST13).

The amount of calculation C2 in the limited search range 59 is

Of comparison processing

(2m1 + 1) (2n + 1) + b

Is the sum of and.

Where l1 = 8, l2 = 8, m = 8, average block k1 = 4, k2 = 4, arithmetic cycles a = 1 (differential absolute value), b = 2 (compare) M1 = 25 and J = 4.

Therefore, the required calculation amount C1 in the first stage is about 1800.

When the limited search range is m1 = 3 and n1 = 3 in the search for the second stage, the required calculation amount C2 in the second stage is about 3200 machine cycles.

As a result, it becomes 5000 machine cycles per input block, and is about 1/4 of the calculation amount of the conventional full search.

In the above-described embodiment, an example in which the input block is divided into small blocks and a sample data pattern by the small block is used as the average value pattern based on the pixel average value in the small block is shown. The same effect can be obtained also by using the sample data pattern which took out the pixel value of a position.

Next, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 12 is a block diagram showing the configuration of an apparatus for implementing an image encoding transmission method according to the present invention, where reference numeral 66 denotes input image data and 67 denotes one frame of the image data 66. ) Is a data control unit (DMUX) for distributing to each encoding processing dedicated memory 68, an encoding processing dedicated memory for storing the subsample image data 66 provided corresponding to each encoding processing unit 69, ( 69 is an encoding processing unit for encoding the subsample image data 66 stored in the encoding processing dedicated memory 68, and 70 is all or received the encoding image data 72 encoded by the encoding processing unit 69. The coded transmission control units (MUX) and 71 which are adaptively selected and synthesized according to the resolution of the side device (not shown), and subsampled again and sequentially transmitted are subsample image data read by the coding processor 69. 66 words The response and data bus 72 denotes coded image data encoded by the encoding processor 69, and 73 denotes whether the resolution of the receiving apparatus is standard (same resolution) or subsample (1/2, 1 / The encoding mode control signal 74 indicating the resolution of 4 or more) is synthesized according to the resolution of the receiving side apparatus, and is again subsampled transmission data.

FIG. 13 is a diagram for explaining a subsample in which pixels are divided into a plurality of data intermittently so that pixels constituting one frame of image data do not overlap. In the figure, the case where four subsample image data (Figs. 13B to 13E) is generated from one frame of image data as shown in Fig. 13A is considered (1/4 subsample). As shown in FIG. 13A, when pixels of image data of one frame are classified into four types of symbols ○, ×, △, and □, subsample image data having a resolution of 1/4 as shown in the same drawings B, C, D, and E ( 1/4 subsample). For example, with reference to the same drawing b, data can be created by subtracting pixels of symbols x, Δ, and □ other than the symbol ○ from image data of one frame (the same drawing a). Becomes 1/4).

Next, the operation will be described.

The data control unit 67 sequentially inputs the image data 66 for one frame and distributes the data to the encoding processing dedicated memory 68 for transmission.

The image data stored in the encoding processing dedicated memory 68 are read and encoded by the encoding processing section 69 which are respectively arranged in parallel. The encoded coded image data 72 is output to the coded transmission control section 70 and received when all or adaptively synthesized and transmitted of the coded image data 72 according to the instruction of the encoding mode control signal 73. Subsampled again according to the number of encoding processing units owned by the side apparatus, the header is attached to the subsampled data, and is sequentially transmitted for one frame as the transmission data 74.

Here, as shown in Fig. 13, it is considered that the 1/4 subsample image data 13b, c, d, and e are inputted (the four encoding processing units 69 are provided side by side). These four subsample image data are encoded by the encoding processing unit 69 and output to the encoding transmission control unit 70. In the coded transmission control unit 70, for example, if the coded mode control signal 73 is standard (same as the resolution of the receiving side device), all four coded image data 72 are synthesized, and 1/4 sub If the sample mode (the resolution of the receiving side device is 1/4), one coded image data 72 is arbitrarily selected among 4 (it does not need to be synthesized), and the 1/2 subsample mode (the resolution of the receiving side device is 1). / 2), two coded image data 72 out of four are arbitrarily selected and synthesized. In the above embodiment, the subsample of the image data is 1/4, but the same effect can be obtained even with a 1 / 2n (n = 1, 2, 3, ...) subsample.

As described above, according to the first embodiment of the present invention, the operation result data output from the data computing unit is directly input to the limit processing unit, and the limit processing unit limits processing to any valid number of bits instructed by the instruction execution control unit. In this way, it is possible to obtain a digital signal processing apparatus capable of performing arithmetic and limit processing in one instruction and performing efficient limit processing.

According to the second embodiment of the present invention, the front end multiprocessor and the rear end multiprocessor process the encoding of all pixels and the encoding of the effective block separately, and the amount of encoding data generated by the front end multiprocessor by the threshold value control. Since the number of effective blocks is changed by the amount of data stored in the buffers buffering the buffers and the throughput of the subsequent multiprocessors is kept constant, the processing time does not need to be set to the worst value. Since the processing power of the processor can be always maximized, the number of processors required for processing can be reduced.

According to the third embodiment of the present invention, by using the average intra-block distortion value for compressing the motion vector search range, a matching error at the time of compression is prevented and a high-density motion vector is obtained only for the compressed region. Since the search is performed, the amount of computation is reduced and the apparatus can be simplified, and a motion compensation method capable of detecting a motion vector with high detection accuracy can be obtained.

According to the fourth embodiment of the present invention, the subsampled subsample image data is sequentially inputted for one frame, and each encoded processor is encoded in parallel, and the encoded image data is all or adapted to the resolution of the receiving side apparatus. By selecting and synthesizing the data, the sub-samples are sequentially re-sampled to match the number of encoding processing units of the receiving side apparatus to be transmitted, and the sequential headers are transmitted. At the same time, it is possible to reduce the receiving buffer capacity by connecting to the low resolution receiving side apparatus and eliminating the time difference between the receiving operation and the encoding process.

Claims (4)

A command memory 1 for storing instructions of a micro program, a command execution control unit 2 for reading a command from the command memory 1, decoding the same, and executing operation control such as an operation, and for transmitting data and control signals. Various operations are performed on data input bus 3, data memory 4 having several input / output ports for storing operation data, and two input data transferred from data memory 4 via data input bus 3; A data operation section 5 for executing the operation, an address generation section 6 for independently generating the addresses of the two input and one output data of the data calculation section 5, and a data output bus 7 for transferring the calculation result data of the data. In the digital signal processing apparatus comprising a), the operation result data output from the data computing section 5 is directly input via the data path 108, and the instruction execution control section 2 And a limit processing section 8 for limiting the number of valid bits indicated through the data path 110, and for outputting the result of the processed calculation results to the data output bus 7 via the data path 111. Digital signal processing device. It is responsible for the encoding process for all the pixels of the input data input from the input terminal 11, and provides a plurality of processors 12 that can be extended in parallel in accordance with the throughput, and the effective / invalid block information and the block data It is responsible for processing only the effective block of the input data input from the front end multiprocessor 15 and the input terminal 11 having the function of adding position information in the frame, and can be expanded in parallel in accordance with the throughput. A processor 12 and a frame according to a function of identifying a valid block by the valid / invalid block information added to the block data by the front end multiprocessor 15 and the position information added to the block data. A rear end multiprocessor 16 having the function of reconstructing the front end multiprocessor 15 and the rear end multiprocessor 16; ) Is connected to a buffer 17 and a subsequent multiprocessor 16 which store the encoded data output from the front end multiprocessor 15 and buffer the processing time difference between the front end multiprocessor and the rear end multiprocessor. And a threshold hold value that controls the amount of generation of the encoded data of the front end multiprocessor 15 to limit the amount of generation of the encoded data of the front end multiprocessor at the same time and to the data accumulation amount of the buffer 17. Therefore, the image encoding apparatus includes an output control unit (18) for changing the effective number of blocks to maintain a constant throughput of the rear end multiprocessor (16), and to output output data to the output terminal (13). The current input frame of digital image data consisting of several frames sequentially input in time series is divided into a plurality of blocks, and each block of the image data of the current input frame is divided into blocks of the previous input frame encoding reproduction data. A motion compensator 35 for calculating a block approximation and detecting a motion vector while calculating an approximation between the patterns between the signals, and converting the minimum distortion block obtained by the motion compensator into a prediction signal 36. In the motion compensation inter-frame encoding apparatus for performing encoding transmission processing, the playback data is divided into small blocks of a size that can equally divide the input block, and the average value of the pixels in the small block or the pixel value at a specific position. A sampling circuit 47 for extracting the sample as a sample, and at least a sample value extracted by the sampling circuit. A sample data memory 49 for storing one frame is provided, and the motion compensator obtains a sample data pattern including an average value or a specific pixel value for each small block with respect to the input block, similarly to the sampling circuit, and the motion vector. Detects a first search motion vector group at a position that is a multiple of the size of the small block centering on the same position as the input block in the playback frame data, and blocks the positions representing the motion vectors. A first search motion vector is read from the sample data memory to calculate a distortion amount representing a pattern similarity between the sample data patterns of the input block, and a first search motion vector giving a minimum distortion amount among the distortion amounts. And at a high density around the first search motion vector. Two search motion vector groups are arranged, and the distortion amount is calculated between the intra-block pixel pattern in the playback frame and the pixel pattern in the input block according to the second search motion vector group, and their distortion A motion compensation interframe encoding apparatus characterized by detecting a block giving a minimum distortion and its motion vector, and outputting them as a final prediction signal and a motion vector. In an image encoding apparatus in which n (n is an integer of 1 or more) coding units 69 for encoding image data are arranged in parallel, the image data 66 is sequentially input for one frame, and each encoding processing dedicated memory 68 Dedicated to each encoding process for inputting one frame of subsample image data, which is data obtained by subsampling the data control unit 67 and the image data 66 into n frames per frame and transmitted with a sequential header. The memory 68, the n encoding processing units 69 for encoding the input n subsample image data respectively, and the encoding processing units in which m (m is an integer of 1 or more) in parallel with each other in accordance with the resolution of the receiving side apparatus; All or optionally selected coded picture data of the n coded coded picture data are synthesized, the sample coded coded picture data is subsampled into m pieces, and the sequential header is obtained. And a picture code transmission device comprises a coding transfer controller 70 to transfer the one frame in sequence as yeoseo transmission for data (74).

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