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KR920015573A - Memory Cell Manufacturing Method - Google Patents

Memory Cell Manufacturing Method Download PDF

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Publication number
KR920015573A
KR920015573A KR1019910000895A KR910000895A KR920015573A KR 920015573 A KR920015573 A KR 920015573A KR 1019910000895 A KR1019910000895 A KR 1019910000895A KR 910000895 A KR910000895 A KR 910000895A KR 920015573 A KR920015573 A KR 920015573A
Authority
KR
South Korea
Prior art keywords
forming
polysilicon film
film
whole
gate
Prior art date
Application number
KR1019910000895A
Other languages
Korean (ko)
Other versions
KR930008074B1 (en
Inventor
김익년
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000895A priority Critical patent/KR930008074B1/en
Publication of KR920015573A publication Critical patent/KR920015573A/en
Application granted granted Critical
Publication of KR930008074B1 publication Critical patent/KR930008074B1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H01L28/91—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

메모리 셀 제조방법Memory Cell Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2 도는 본 발명의 제조공정단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

Claims (2)

기판위에 기판과 동형의 웰을 형성하고 산화막을 전체적으로 형성한 다음 포토/에치 공정을 거쳐 소정 갯수의 블럭산화막을 형성하는 단계, 트랜지스터 채널용 얇은 폴리실리콘막을 증착하고 설정된 필드영역의 블록산화막상에 증착된 것을 제거한 다음 재결정화를 위해 어닐링 시키는 단계, 두꺼운 폴리실리콘막을 증착하고 에치 공정을 거쳐 블럭산화막 측벽폴리 실리콘막을 형성한 다음 어닐링시키는 단계, 전체적으로 게이트 산화막을 형성하고 상기 블럭산화막 측벽폴리실리콘막에 이온 주입을 실기하여 소오스/드레인을 형성하는 단계, 액티브영역과 필드영역의 블럭산화막상의 게이트산화막위에 게이트 폴리실리콘막을 형성하고 전체적으로 절연산화막을 형성한 다음 포토/에치공정을 실시하여 각 영역상의 게이트사이에 콘택트를 형성하는 단계, 상기 콘택트상에 스택구조용 폴리실리콘막과 스토리지노드용 폴리실리콘막을 형성한 다음 그위에 커패시터 유전체막과 플레이트 폴리실리콘막을 형성하는 단계가 차례로 포함됨을 특징으로 하는메모리 셀 제조방법.Forming a well of the same type as the substrate on the substrate, forming an oxide film as a whole, and then forming a predetermined number of block oxide films through a photo / etch process, depositing a thin polysilicon film for the transistor channel, and depositing it on the block oxide film in the set field region. Annealed for recrystallization after removal of the residue, depositing a thick polysilicon film and etching to form a block oxide sidewall polysilicon film, followed by annealing, forming a gate oxide film as a whole, and forming ions on the block oxide sidewall polysilicon film Forming a source / drain by performing implantation; forming a gate polysilicon film on the gate oxide film on the block oxide film of the active region and the field region; forming an insulating oxide film as a whole; and performing a photo / etch process between the gates of the respective regions. Forming contacts And forming a stack structure polysilicon film and a storage node polysilicon film on the contact, and then forming a capacitor dielectric film and a plate polysilicon film thereon. 제 1 항에 있어서, 스택구조용 폴리실리콘막은 전체적으로 폴리실리콘막을 형성하고 포토/ 에치 공정을 거쳐 액티브영역과 필드영역상의 게이트 위에 증착된 일부만을 남긴 상태 임을 특징으로 하는 메모리 셀 제조방법.The method of claim 1, wherein the polysilicon film for the stack structure is a polysilicon film as a whole and leaves only a portion of the polysilicon film deposited on the gate in the active region and the field region through a photo / etch process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000895A 1991-01-19 1991-01-19 Method of fabricating for memory cell KR930008074B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000895A KR930008074B1 (en) 1991-01-19 1991-01-19 Method of fabricating for memory cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000895A KR930008074B1 (en) 1991-01-19 1991-01-19 Method of fabricating for memory cell

Publications (2)

Publication Number Publication Date
KR920015573A true KR920015573A (en) 1992-08-27
KR930008074B1 KR930008074B1 (en) 1993-08-25

Family

ID=19310068

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000895A KR930008074B1 (en) 1991-01-19 1991-01-19 Method of fabricating for memory cell

Country Status (1)

Country Link
KR (1) KR930008074B1 (en)

Also Published As

Publication number Publication date
KR930008074B1 (en) 1993-08-25

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