KR920009751B1 - Semiconductor device and its manufacturing method with field plate - Google Patents

Abstract

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Description

Semiconductor device with field plate and manufacturing method thereof

1 is a cross-sectional view of a conventional semiconductor device including a vertical MOSFET.

2 is a cross-sectional view of another conventional semiconductor device including a vertical MOSFET.

3 is a cross-sectional view according to an embodiment of the present invention.

4 is a plan view of a semiconductor device according to the present invention.

5 is a plan view partially showing a pattern of a diffusion region on a surface of a semiconductor device.

6 to 9 are cross-sectional views for explaining the steps of the semiconductor device manufacturing process.

* Explanation of symbols for the main parts of the drawings

1: N ⁺ layer 2: N ^- epitaxial layer (N ^- type train area)

3, 3A: P type base area 4: Source area (N ⁺ area)

5 gate insulating layer 6 gate electrode

7 thin oxide layer (insulating layer) 8 second insulating layer

9, 9A: P ⁺ type base area 10: junction

11 source electrode (conductive layer) 12 drain electrode

13 corner 17, 18 insulation layer

17a, 25a: thin section 17b, 25b: thick section

21: N ⁺ type silicon substrate 22: N ^- type epitaxial layer (N ^- type drain layer)

23: N ^- type drain layer 23a, 23b: P-type impurity region

23h: channel formation region 24a: N ⁺ region

25: first insulating layer 26: first conductive layer

27: second conductive layer 28: second insulating layer

31: conductive layer 34: stairs

35, 35a: region 36: semiconductor substrate

50 drain electrode 60 resist layer

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a field plate structure, and more particularly to a semiconductor device having a field plate designed to increase the breakdown voltage of an outer peripheral portion of a vertical MOSFET device, and a manufacturing method thereof.

[Traditional Technology and Problems]

In the conventional vertical MOSFET, a field plate structure has been widely used to increase the breakdown voltage between the source and the drain on the main surface side of the substrate.

FIG. 1 shows a cross-sectional view of a vertical MOSFET having a conventional fill plate structure, wherein the substrate of the MOSFET is composed of an N ⁺ layer 1 and an N ⁻ epitaxial layer 2, where the N ⁻ epitaxial layer 2 is formed. It acts as an N ⁻ type drain region, and a plurality of P type base regions 3 and 3A are selectively formed on the surface of the N ⁻ type drain region 2, and this P type base region 3A is formed around the substrate. It is very close to the edge (not shown). In addition, the P-type base region 3A and the N ⁻ -type drain region 2 form a PN junction with a junction end 10 on the surface of the epitaxial layer 2.

P + type base regions 9 and 9A are formed in each of the base regions 3 and 3A, and a high concentration N ⁺ type source region 4 is formed so as to enclose the P + type base region 9, and N ^A channel forming region 3h is formed between the type drain region 2 and the source region 4.

A gate electrode 6 is formed on the channel formation region 3h via the gate insulating layer 5, and a thin oxide layer 7 is formed from the P-type base region 3A so as to cover the junction 10. The second insulating layer 8 is formed to extend to the outside and to cover the first insulating layer 7 and the gate electrode 6. The source electrode 11 in contact with the P + type regions 9 and 9A and the N ⁺ region 4 is formed on the insulating layer 8.

In order to operate the device, a positive potential is applied to the drain electrode 12 and a negative potential is applied to the source electrode 11, and a preset positive potential is applied to the gate electrode 6 in the channel forming region 3h. As the channel is formed, a drain current flows, which is controlled by the gate potential. In this case, the drain current is cut off when the gate potential is lower than a preset voltage (eg, a threshold voltage).

On the other hand, since the depletion layer tends to easily expand into the low impurity concentration region, in the above structure, the depletion layer is mainly formed between the N ^- type drain region 2 and the P-type base region 3, 3A, thereby reducing the drain voltage. It will be burdened.

In addition, there is a problem that the electric field is concentrated in the corner portion 13 of the P-type base region 3A. As a result, the internal pressure decreases due to the electric field concentration. The field plate structure is formed by extending the source electrode 11 by the length a1 from the PN junction 10 in order to prevent the breakdown of the breakdown voltage. In addition to this, it is possible to increase the breakdown voltage between the source and drain regions.

On the other hand, it is possible to increase the internal pressure of the plate structure using the field plate structure as follows. That is, in the corner portion 13 of the PN junction, the breakdown voltage is reduced due to electric field concentration. When the field plate structure is used, the N ⁻ type drain region 2 located below the field plate is applied by applying a forward bias between the source and drain regions. The depletion layer is formed here because the carrier of the surface of the is released. In the case of the N-channel MOSFET, the positive potential is applied to the drain, and in the case of the P-channel MOSFET, the negative potential is applied to the drain. The depletion layer is formed between the N ⁻ type drain region 2 and the P type base region 3A and extends continuously, that is, the radius of curvature of the depletion layer at the corner portion 13 of the PN junction may be relaxed. Therefore, the internal pressure increases. The effect of the breakdown voltage improvement by the field plate is greatly related to the thickness of the insulating layer under the field plate and the material of the insulating layer (see IEEETRANSACTIONS, ED-26, NO.7, July, 1977 p. 1098 to 1100). ).

In the above structure, the voltage applied between the drain electrode 12 and the source electrode 11 is divided by the voltage applied to the insulating layers 7 and 8 and the voltage applied to the depletion layer under the field plate portion a1. This partial pressure ratio is inversely proportional to the capacitance, i.e., a larger voltage is applied to the smaller capacity.

As the voltage increases, the depletion layer increases, and accordingly, the radius of curvature at the curved portion of the PN junction is further alleviated, thereby preventing electric field concentration. Therefore, the capacitance of the insulating layers 7 and 8 as the dielectric layer may be made larger than that of the depletion layer using a material that is as thin as possible and has a large dielectric constant.

Therefore, when the insulating layers 7 and 8 become thin, a large voltage is applied to the field plate stage as well, so it is necessary to determine the thickness of the insulating layer that can withstand the breakdown voltage due to the field concentration at the field plate stage. Therefore, in the above structure, it is difficult to satisfy the increase in the depth of the depletion layer below the field plate and at the same time it is difficult to reduce the field accumulation at the field plate end.

FIG. 2 shows a cross-sectional view of another conventional device, in which a field plate is formed by extending the source electrode 11 from the pn junction end 10 by a length a2. 17 has a relatively thin portion 17a and a relatively thick portion 17b. Therefore, the voltage required to form the depletion layer around the junction 10 becomes relatively large and at the same time the electric field can be reduced at the edge of the conductive layer 11, thereby increasing the breakdown voltage. However, in the above structure, the insulating layers 17 and 18 are located between the conductive layer 11 and the substrate 2 serving as the field plates, so that the entire insulating layer is thickened to form a large depletion layer under the field plate. There will be no.

Unlike the above, there is a method in which a protective ring is used to increase the internal pressure. However, when the protective ring is used, a relatively large area is required around the apparatus, thereby reducing the effective area of the apparatus.

[Purpose of invention]

Invented in view of the above-described point of the present invention, a semiconductor device having an improved field plate structure capable of forming a large depletion layer around a PN junction and being manufactured without a complicated manufacturing step, and a method of manufacturing the same The purpose is to provide.

[Configuration of Invention]

According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having first and second main surfaces; A second conductive second diffusion region forming a PN junction on the first main surface of the substrate while forming a PN junction to the first main surface of the substrate, and a channel region formed between the substrate and each of the second diffusion regions. A plurality of first conductivity type first diffusion regions including; A predetermined opening corresponding to each of the first diffusion regions, a first portion of a first thickness located on the channel region, and a second thickness that is thicker than the first thickness and extends continuously from the first portion A first insulating layer having a second portion of the first insulating layer; A first conductive layer covering at least the channel region and having a first edge on a second portion of the first insulating layer; A second insulating layer covering the first insulating layer and the first conductive layer and including openings corresponding to the first diffusion regions; The second insulating layer is in contact with the first conductive layer through the opening, located on the second portion of the first insulating layer, and located further than the first edge from the PN junction between the first diffusion region and the substrate. A second conductive layer on a second heat transfer layer including a second edge to be formed; And a third conductive layer at least partially covering the second insulating layer and in contact with the second diffusion region.

In addition, a method of manufacturing a semiconductor device according to the present invention includes the steps of preparing a semiconductor substrate having first and second main surfaces; A first insulating layer having a first portion of a first thickness, a second portion of a second thickness thicker than the first thickness, and a plurality of first openings for selectively revealing the first major surface of the substrate through the first portion; Forming step; Forming a first conductive layer for a plurality of second openings each corresponding to any one of the first openings of the first insulating layer, including a first edge located on the second portion of the first insulating layer ; Introducing a first conductivity type impurity into the substrate through first and second openings to form a plurality of first conductivity type first diffusion regions each having a PN junction to the substrate; Forming a second conductive type second diffusion region in the first diffusion region leaving a predetermined space with respect to the PN junction between the first diffusion region and the substrate; A plurality of third openings corresponding to the first insulating layer and the first and second openings of the first conductive layer at least partially exposing the surface of the second diffusion region, and on the second portion of the first insulating layer Forming a first insulating layer and a first insulating layer having a fourth opening that exposes a surface of the first conductive layer; The first conductive layer on the second portion of the first insulating layer relative to the second edge located on the second portion of the first insulating layer leaving a predetermined space relative to the first edge of the first conductive layer; Forming a second conductive layer in contact; And forming a third conductive layer on the second insulating layer in contact with the second diffusion region through the third opening of the second insulating layer.

[Action]

According to the present invention configured as described above, it is possible to increase the breakdown voltage of the semiconductor device by forming a stepped field plate around the PN junction, and to form the field plate without going through a complicated manufacturing process.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing one embodiment according to the present invention, in which an N-channel vertical MOSFET device is formed in a semiconductor field device, and FIG. 4 is a portion corresponding to the region P shown in FIG. The outer area of (36) is shown.

FIG. 5 is a plan view illustrating the pattern of the diffusion region of the semiconductor device with respect to the conductive layer and the insulating layer on the surface of the semiconductor device, and the portion shown in FIG. 5 also corresponds to the region P in FIG. 3 degree corresponds to the cross section along the line XX 'of FIG.

In FIG. 3, an N ⁻ type epitaxial layer 22 is formed on an N ⁺ type silicon substrate 21, and this N ⁻ type epitaxial layer 22 is provided as an N ⁻ type drain layer. P-type impurity regions 23a and 23b are selectively formed on the surface of the N ^- type epitaxial layer 22, and these P-type impurity regions 23a and 23b are provided as P-type base regions. The PN junction between the type base region 23a and the N ⁻ type drain layer 22 ends at the junction end 40 on the surface of the N ⁻ type drain layer 22.

In addition, a P + type region 29 doped with a large amount of impurities is formed in the P type base region 23a, and the P + region 29 is partially filled by the space 23h in the N ⁻ type drain layer 22. An N ⁺ region 24a is formed in the P-type region 23a for stacking, and this N ⁺ region 24a is provided as an N ⁺ -type source region, and the region 23h is provided as a channel forming region.

On the other hand, an insulating layer 25 having a relatively thin portion 25a and a relatively thick portion 25b is formed on the surface of the N ⁻ type drain layer 25. It is composed of a stepped portion 34 defined by a thick portion 25b, and the thin portion 25a covers around the PN junction between the N ^- type drain layer 22 and the P-type base regions 23a and 23b.

A conductive layer 26 is formed on the insulating layer 25, and the conductive layer 26 acts as a gate electrode, and the gate electrode 26 is a channel forming region 23h in response to application of a predetermined voltage. ) Acts to channel the MOSFET at the surface. That is, the MOSFET is constituted by the N ⁺ type source region 24a and the channel forming region 23h and the N ⁻ type drain layer 22 in the regions 35 and 35a. In the same manner, the MOSFET is formed of the N ⁺ type source region. And a P-type base region 23b and an N ^- type drain layer 22, the gate electrode 26 being distanced from the PN junction end 40 for forming the first portion of the field plate. extends outward by (b2).

A second insulating layer 28 having predetermined openings 30 and 37 is formed on the insulating layer 25 and the conductive layer 26, and the opening 30 is formed on the thick insulating layer portion 25b. It is formed to expose the surface of the layer 26, the opening 37 is formed to partially expose the N ⁺ -type source region 24.

In addition, a second conductive layer 27 is formed on the second insulating layer 28, and the second conductive layer 27 is in contact with the first conductive layer 26 through the opening 30. The conductive layer 27 serves as a gate electrode. The gate electrode 27 has a distance b1 from the edge of the conductive layer 26 to have an edge on the thick insulating layer portion 25b and the second insulating insulating layer 28. It extends outward, and the portion extending by the distance b1 constitutes the second portion of the field plate.

The conductive layer 31 is formed on the insulating layer 28 and is in contact with the N ⁺ source region 24a and the P + region 29 through the opening 37 and serves as a source electrode. Here, the P + region 29 acts to lower the resistance between the source electrode 31 and the P-type base region 23a, and the conductive layer 50 provided as a drain electrode on the surface of the N ⁺ silicon substrate 21. ) Is formed.

As described above, the field plate has two parts, for example, the length a1 is about 40 to 70 μm, the length a2 is about 25 to 30 μm, and the relatively thin part 25a is about 1000 mm and a thick part. (25b) is about 5000 microseconds.

Since the insulating layer between the conductive layer 26 adjacent to the junction end 40 and the N ⁻ type drain region 22 is relatively thin, the capacitance in that region becomes relatively large. Therefore, a large voltage is applied to form a relatively large depletion layer on the surface of the N ⁻ type drain layer 22 around the PN junction end 40, while the insulating layer between the conductive layers 26 and 27 and the substrate 22 is applied. The thickness of the depletion layer gradually decreases from the surface of the drain layer 22 since the thickness of the electrode increases outwardly. Therefore, the radius of curvature of the depletion layer extending from the PN junction between the P-type base region 23a and the drain region 22 is alleviated to reduce the electric field contact at the PN junction corner 33.

For example, in the conventional semiconductor device, a 3.5 kW cm wafer was used to achieve 170 V as the breakdown voltage between the source and drain electrodes. However, in the semiconductor device according to the present invention, the wafer can be achieved with a wafer of 2.7 mW cm. The resistance is greatly reduced, and in the conventional device, the ON resistance of the 1 × 1 mm 2 chip is 2.67 mA, but the ON resistance in the device according to the present invention is 1.91 mA, so that the power loss is greatly reduced.

Hereinafter, manufacturing steps of the apparatus will be described in detail with reference to FIGS. 6 to 9.

First, an impurity concentration of 3 × 10 ¹⁸ atmos / ㎤ the eda N ⁺ type silicon substrate 21, including the antimony to a concentration of 2 to grow the epitaxial layer 22 including × 10 ¹⁵ atmos / ㎤ of the N ⁺ type silicon After constructing the substrate 20 having the substrate 21 and the N ⁻ type epitaxial layer 22, an oxide layer of about 5000 GPa was grown and patterned to form a relatively thick insulating layer 25b (sixth). See also)

Subsequently, an oxide layer of about 1000 mW is formed on the surface of the N ⁻ type epitaxial substrate 22, and then a polysilicon layer of about 5000 mW is deposited on the insulating layer 25a and the oxide layer and patterned to form a gate insulating layer 25a. ) And a gate electrode 26, in which an opening 36 is formed at the same time. Subsequently, boron ions are implanted into the substrate using the gate electrode 26 as a mask. The implantation is performed under an acceleration voltage of 40 keV and a dose amount of 4.0 × 10 ¹³ atmos / cm 2. At this time, annealing is performed for about 6 hours in N ₂ gas at 1100 ° C. to form P-type base regions 23a and 23b (see FIG. 7).

On the other hand, the implantation step is performed using a resist layer (not shown) as a mask to form the P + base region 29. The implantation of boron is performed at an acceleration voltage of 40 keV and a dose of 3 x 10 ¹⁵ atmos / cm2. After ion implantation, the resist layer is removed, annealing may be performed in an oxygen atmosphere for about 15 minutes.

Thereafter, in the state where the resist layer 60 having a predetermined pattern is prepared, arsenic is introduced by ion implantation with a dose of 5 x 10 ¹⁵ atmos / cm 2 by applying an acceleration voltage of 40 keV. At this time, after the resist layer 60 is removed, annealing is performed for about 20 minutes in oxygen to form the N ⁺ source regions 24a and 24b (see Fig. 8).

On the other hand, an oxide layer is formed by CVD (Chemical Vapor Deposition) method, and the opening 30 and the N ⁺ source region 24a and the P + type region 29 for exposing the polycrystalline layer 26 on the thick insulating layer 25b. The oxide layer is subjected to the patterning process in order to form the opening 37 for exposing the surface of the ().

Next, as shown in FIG. 3, an aluminum layer is deposited, and a patterning process is performed to form the gate electrode 27 and the source electrode 31. At this time, a drain electrode 50 made of Au or the like is formed on the rear surface of the substrate 21.

As described above, the relatively thin insulating layer 25a is formed in the step of forming the gate insulating layer, and since the conductive layer for the gate electrode and the source electrode is used for the field plate, the field plate is formed of two layers. There is no need for additional manufacturing steps.

Although the N-channel vertical MOSFET is used in the above embodiment, the present invention can be applied to the device of the P-channel MOSFET, and can also be used in the so-called IGBT device in which the opposite conductive region is additionally deposited on the substrate formed on the back side of the substrate. In addition to the active devices, so-called composite semiconductor devices including passive devices may also be applied.

[Effects of the Invention]

As described above, according to the present invention, the manufacturing process is almost the same as that of the conventional semiconductor device. Although the number of steps is the same, the step plate field structure can be realized.

In the structure of the semiconductor device according to the present invention, since a part of the field plate can be used as the gate electrode layer without providing a separate gate electrode layer, the effective area of the MOSFET element can be increased as compared with the conventional structure.

Claims (5)

A semiconductor substrate 20 having first and second major surfaces 22, 21; Second conductive second diffusion regions 24a and 24b forming a PN junction on the first main surface 22 of the substrate 20 while forming a PN junction to the first main surface 22 of the substrate 20. And a plurality of first conductive type first diffusion regions 23a and 23b including a channel region 23h formed between the substrate 20 and the second diffusion regions 24a and 24b. A predetermined opening corresponding to each of the first diffusion regions 23a and 23b, a first portion 25a of the first thickness located on the channel region 23h, and thicker than the first thickness; A first insulating layer 25 having a second portion 25b of a second thickness extending continuously from the first portion 25a; A first conductive layer 26 having a first edge on at least a second portion 25b of the first insulating layer 25 covering at least the channel region 23h; A second insulating layer 28 covering the first insulating layer 25 and the first conductive layer 26 and including openings corresponding to the first diffusion regions 23a and 23b; The first conductive layer 26 is connected to the first conductive layer 26 through an opening of the second insulating layer 28, and is positioned on the second portion 25b of the first insulating layer 25. 23a, 23b) and second conductive layer 27 on second insulating layer 28 including a second edge located further than the first edge from the PN junction between substrate 20; 12. A semiconductor device with a field plate, characterized in that it comprises a third conductive layer (31) which at least partially contacts said second diffusion region (24a, 24b) while covering said second insulating layer (28). The first diffusion region (23a, 23b) is further provided with a first conductive type third diffusion region 29 which is at least partially enclosed by the second diffusion region (24a, 24b). A semiconductor device having a field plate, characterized in that. Preparing a semiconductor substrate 20 having first and second major surfaces 22, 21; The first main surface 22 of the substrate 20 is selectively made through the first portion 25a of the first thickness, the second portion 25b of the second thickness thicker than the first thickness, and the first portion 25a. Forming a first insulating layer 25 having a plurality of first openings for scouring; A plurality of second openings each including a first edge on the second portion 25b of the first insulating layer 25 and corresponding to any one of the first openings of the first insulating layer 25. Forming a first conductive layer 26 with respect to the; The first conductive type is formed in the substrate 20 through the first and second openings to form a plurality of first conductive type first diffusion regions 23a and 23b each having a PN junction to the substrate 20. Introducing an impurity; Forming second conductive diffusion regions 24a and 24b in the first diffusion regions 23a and 23b leaving a predetermined space for the PN junction between the first diffusion regions 23a and 23b and the substrate 20. step ; A plurality of third openings corresponding to the first and second openings of the first insulating layer 25 and the first conductive layer 26 at least partially exposing the surfaces of the second diffusion regions 24a and 24b; The first conductive layer 26 and the first insulating layer 25 having a fourth opening that exposes the surface of the first conductive layer 26 on the second portion 25b of the first insulating layer 25. Forming a second insulating layer 27 on the substrate; The first insulating layer 25 with respect to the second edge located on the second portion 25b of the first insulating layer 25 leaving a predetermined space with respect to the first edge of the first conductive layer 26. Forming a second conductive layer (27) in contact with the first conductive layer (26) on a second portion (25b) of; Forming a third conductive layer 31 on the second insulating layer 27 in which the second insulating layer 27 is in contact with the second diffusion regions 24a and 24b through a third opening. A method of manufacturing a semiconductor device having a field plate, characterized in that. The method of manufacturing a semiconductor device with a field plate according to claim 3, wherein said first and second openings are formed simultaneously. 5. The method of manufacturing a semiconductor device with a field plate according to claim 4, further comprising the step of injecting impurities of a first conductivity type into the first diffusion regions (23a, 23b).

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