KR920007097B1 - Bus transmitter having controlled trapezoidal slew rate - Google Patents

Abstract

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Description

Bus Transmitter with Controlled Trapezoid Turnover

1 is a schematic circuit diagram of a digital data bus transmitter constructed in accordance with the present invention.

FIG. 2 illustrates signal waveforms at two points in the circuit shown in FIG. 1 useful for understanding the transmitter shown in FIG.

* Explanation of symbols for main parts of the drawings

10: transmitter 11: bus driver transistor

12 buffer circuit 13 inverter

15: P-type transistor 16: p-type pull-up transistor

17: n-type pull-down transistor 20, 21: constant current source

FIELD OF THE INVENTION The present invention generally relates to the field of electronic circuits, and more particularly to circuitry for transmitting signals over a bus in a digital data processing system.

Digital data processing systems include input / output devices such as mass storage devices, video display terminals, printers, and telecommunication devices all interconnected by one or more processors, memory, and one or more buses. It includes, a plurality of functional units (functional unit). The bus not only carries a signal representing information between the plurality of units constituting the system, but also controls a signal that controls the transmission of the original information signal.

In general, a bus is a wire set in which multiple functional units can be connected in parallel. In the case where the unit transmits a signal through a wire in the bus, the signal can be reflected when reaching the end of the bus. The reflected signal can interfere with the signal transmitted later over the bus wire, signaling the error on the bus. The main problem with signal reflection is that it can cause the transmission of the transmitted signal later. Thus, the system designer must provide sufficient delay time after one transmission before another transmission occurs to minimize similar disturbances from signal reflections.

Optionally, system designers can configure the bus or signals transmitted on it to minimize reflections. For example, certain wires include a resistor network at each end to help reduce reflections. Power for the bus can also be provided through this bus terminator network.

Incidentally, the shape of the signal waveform can be adjusted to minimize reflection and crosstalk between signals on different bus lines. In particular, the signal waveform can be relatively square so that the voltage level of the bus wire changes relatively steeply between high and low voltage levels. Such signal waveforms allow for high speed signaling, but this is also very likely to cause signal reflection and crosstalk.

On the other hand, if the signal is "trapezoidal" and the signal's voltage level is less steep between the high and low levels but still changes at a high rate, the possibility of reflection can be minimized. The transmitter generating this signal must be able to control the rate of change of voltage on the wire, or "slew rate," within the selected range. This problem is, in most systems, a widely varying capacitive load that can vary the number of widely varying units that a bus is connected to, thereby changing the turnover of signals transmitted on the bus wires. It is complex because it can generate a load) state.

Currently, transmitters capable of generating trapezoidal signal waveforms are implemented using bipolar transistor devices in combination with discrete resistors and other components whose electrical values can be controlled with high accuracy. . Most of the circuits that make up the functional unit of a digital data processing system are implemented using a MOSFET (metal-oxide-semiconductor field effect transistor) device, and the bipolar transmitter circuit is implemented separately from other components constituting the unit. It occupies a fairly large space on a printed circuit board on which the circuit elements forming the circuit board are mounted. Incidentally, because bipolar transmitters are discrete, bipolar and separate from other devices, they require a significant amount of power and provide extra delay in the transmitted signal.

The present invention provides a new and improved transmitter circuit implemented using MOSFET devices to generate signals in trapezoidal waveforms for transmission over a bus.

In short, the new bus transmitter circuit is a buffer circuit with pull-uP and pull-down transistor currents whose current is controlled by a constant current source. And a MOSFET bus driver transistor driven by it. The capacitance C _GD between the gate and drain of the driver transistor is significantly higher than the other capacitance at the gate terminal. The gate terminal of the driver transistor is connected to the pull-up and pull-down transistors and controlled by these transistors. The drain terminal of the driver transistor is connected to the bus line to control this bus line. To assert a signal on the bus line, the pull-up transistor is turned on to drive the current into the node at a rate governed by the current source, increasing the voltage level of the node. When the voltage level of the node reaches the threshold level of the driver transistor, the driver transistor begins to turn on, causing the voltage level of the bus line to drop. At the same time, current begins to flow from the bus line into the node through the gate-to-drain capacitance of the driver transistor, limiting the voltage level at the node, thus limiting the current flow through the driver transistor. Thus, current flows from the bus line through the driver transistors in a manner that is partly controlled by the rate of change of the voltage level on the bus line, thereby achieving trapezoidal rotation of the signal on the bus line. Negate the signal on the bus line, the operation is similar, so that current flows out of the node through the gate-drain capacitance of the pull-down transistor and driver transistor.

The invention is pointed out in detail within the scope of the appended claims. The above and other advantages of the present invention can be better understood by referring to the following description in conjunction with the accompanying drawings.

Referring to FIG. 1, a transmitter 10 constructed in accordance with the present invention includes a bus driver transistor 11 whose gate terminal receives a BUF OUT buffer output digital data signal from the buffer circuit 12 in the form of an inverter. In response to the asserted (ie high state) BUF OUT buffer output signal from the buffer circuit 12, the bus driver transistor passes through the bus line 14 to the BUS OUT (L) bus output (assert low). Turn on to transmit a digital data signal. The bus driver transistor 11 has a drain terminal directly connected to the bus line 14 and a source terminal connected to the V _ss supply power supply which is efficiently at the ground voltage level. The bus driver transistor 11 is an n-type metal-oxide-semiconductor field effect transistor (MOSFET).

The buffer circuit 12 includes a P-type pull-up transistor 16 and an n-type pull-down transistor 17 connected between two constant current sources 20 and 21. The current source 20 is connected to the V _DD supply and controls the current coupled to the drain terminal of the pull-up transistor 16. The source terminal of the pull-up transistor 16 is connected to the node 22, which is also connected to the drain terminal of the pull-down transistor 17. The source terminal of the pull-down transistor 17 is connected to a current source 21 which controls the current flowing from the node 22 to the V _ss power supply. The BUF OUT inverter output signal coupled to the gate terminal of the bus driver transistor 11 is provided to the node 22 between the pull-up transistor 16 source terminal and the drain terminal of the pull-down transistor 17. Referring back to transistor 11, the transistor has a high capacitance between the gate and drain terminals (shown as C _GD in FIG. 1) relative to the other capacitance at node 22, and thus the gate and drain The capacitance C _GD of the liver is considerably superior to other capacitance sources on node 22.

The gate terminals of the pull-up transistor 16 and the pull-down transistor 17 are inverters 13 that invert the SIG OUT (L) signal output (asserted low) from another circuit (not shown). Is controlled in series by the SIG OUT (H) signal output (asserted high). The SIG OUT (L) signal output (asserted low) also controls the P-type transistor 15 having a drain terminal connected to the node 22 and a source terminal connected to the V _ss power supply.

Initially, the SIG OUT (H) signal output (asserted high) signal is in a low voltage (negated) state. As a result, the transistor 15 is turned on. Inverter 13 provides a high voltage level (negated) SIG OUT (L) signal output (asserted in a low state) signal that keeps transistor 17 on and transistor 16 off. Complement the SIG OUT (H) signal output (asserted high) to do so. At this time, the charge from the node 22 is transferred through the current source 21 to the V _ss source voltage level (ie, ground), so that the BUF OUT buffer output signal is at the low voltage level. Incidentally, because the driver transistor 11 is off, the BUF OUT (L) bus output (asserted low) is at a high voltage level, as shown at time A (figure 2) (and therefore This provides a signal with a negated logic level.

When the SIG OUT (H) signal output (asserted high) signal is shifted from the negated (low voltage) state to the asserted (high voltage) state, the transistor 15 is turned off. Incidentally, the inverter 13 is SIG OUT (H) signal output (asserted high) to form a SIG OUT (L) signal output (asserted low) in a low voltage (asserted) state. ) Repair the signal. As a result, the transistor 17 is turned off to block the current path from the node 22 to the V _ss supply through the current source 21. Incidentally, the SIG OUT (L) signal output (asserted low) turns on the transistor 16 to generate a path from the V _DD supply to the node 22 through the current source 20.

Since transistor 16 is on, the voltage level of the BUF OUT buffer output signal starts to rise as shown from time A to time B in FIG. At time B (Figure 2), the voltage level of the BUF OUT buffer output signal rises to the threshold voltage level, so the bus driver transistor 11 begins to turn on. This allows current from the bus line 14 to flow through the bus driver transistor 11, so the BUS OUT (L) bus output (low asserted as shown) immediately after time B (figure 2). This causes the voltage level of the signal to drop. However, because the gate-to-drain capacitance C _GD of the bus driver transistor 11 is a relatively large portion of the total capacitance on the node 22, the current is also a node from the bus line 14 through the gate-drain capacitance C _GD . It is drawn in (22). Therefore, the gate-to-drain capacitance C _GD provides a feedback path such that the BUS OUT (L) bus output (asserted low) affects the voltage level at node 22.

At this time, two sources, namely, the current source 20 (via the pull-up transistor 16) and the bus line 14 (via the gate-drain capacitance C _GD of the bus driver transistor 11) are in opposite directions. Since the current is forced into the node 22 from the node 22, the voltage level of the node 22 relative to ground (i.e., the voltage level of the _Vss source supply) is shown between time B and C in FIG. As does not change. Thus, the voltage level on the gate terminal of the bus driver transistor 11 is maintained at almost the threshold level, so that the transistor 11 is kept on, but the voltage level of the bus line 14 is maintained at a level that drops to a controlled ratio. . That is, the voltage of the BUS OUT (L) bus output (asserted low) signal is related to the capacitance C _GD between the gate and the drain of the bus driver transistor 11 and the period related to the current flow provided by the current source 20. During the transition from high level to low level.

When the voltage level of the BUS OUT (L) bus output (asserted low) signal on bus line 14 has completed a downward transition, current flows from bus line 14 via the gate-to-drain capacitance C _GD . The rate of entry into node 22 also drops. As a result, the current drawn from the current source 20 into the node 22 through the pull-up transistor 16 dominates the node 22, and the voltage level of the node 22 is determined by the time C and D (FIG. 2). As shown between), it starts to add. The increase ratio depends on the capacitance of the node 22, including the capacitance C _GD between the gate and drain, and the current supplied by the current source 20. At time D (FIG. 2), node 22 is charged to the maximum voltage level. At this time, as shown by the high BUF OUT buffer output signal at time D of FIG. 2, the bus driver transistor 11 is fully on and the node 22 is fully charged. In addition, at time D, the BUS OUT (L) bus output (asserted low) is fully asserted. That is, at a low voltage level.

By time E, the BUF OUT buffer output signal remains at the high voltage level and the BUS OUT (L) bus output (asserted low) remains at the low voltage. At time E, the SIG OUT (H) signal output (asserted high) is negated. That is, driven at a low voltage level. As a result, inverter 13 complements the low SIG OUT (H) signal output (asserted in high state) signal to provide a high SIG OUT (L) signal output (asserted in low state) signal. A high S1G OUT (L) signal output (asserted low) turns off pull-up transistor 16 to turn off the current path from current source 20 to node 22 and pull-down The transistor 17 is turned on to provide a current path from the node 22 to the current source 21.

Incidentally, the high SIG OUT (H) signal output (asserted in high state) signal turns on transistor 15, direct current path between node 22 and the ground voltage level provided by the _Vss source supply. To provide. The current path through transistor 15 causes node 22 to quickly discharge to the threshold voltage level of transistor 15 between times E and F (FIG. 2). In one particular embodiment where transistor 15 is a P-type transistor, transistor 15 causes the voltage level at node 22 to drop from about 5V to about 2.5V from a fully charged state. A predetermined current also flows from node 22 through pull-down transistor 17 and current source 21 during this time, but the main current path passes through transistor 15. After sufficient current flows from the node 22 to cause the voltage level of the node 22 to become the dwell level of the bus driver transistor 11, the bus driver transistor 11 starts to be turned off, so that BUS OUT (L) By causing the voltage level of the bus output (low asserted) signal to rise, it negates the BUS OUT (L) bus output (asserted low) signal.

Around time F, when the voltage difference between the gate terminal and the drain terminal of the transistor 15 drops to the threshold level of the transistor, the transistor 15 is basically turned off. However, current continues to flow from node 22 through pull-down transistor 17 and current source 21. At the same time, the current continues to flow from the node 22 in the opposite direction, ie through the capacitor C _GD between the gate and the drain of the bus driver transistor 11. Since the current flows out of the node 22 in the opposite direction, the voltage level of the node 22 which provides the BUF OUT buffer output signal is controlled by the transistor 11, as shown at time FG in FIG. It remains constant at the level of equinox to keep on. This causes the voltage level of the BUS OUT (L) bus output (asserted to low state) signal to increase stably during this period, as shown in FIG.

At time G, the gate-drain capacitor C _GD stops drawing charge from the node 22, and therefore only to the node 22 through the transistor 17 which is still on at a controlled rate by the current source 21. An electric charge will remain. Thus, the voltage level at node 21 drops to the _Vss source supply power level, which is the ground level of transmitter circuit 10. Thus, the BUF OUT (L) buffer output (asserted low) drops to a controlled ratio between time GH (figure 2) as shown in FIG.

Transistor 15 is provided to reduce the time E-F required to pull the voltage level of node 22 to the point where bus driver transistor 11 begins to turn off. In the absence of the transistor 15, instead, current flows through the pull-down transistor 17 and the current source 21, but because the current source 21 restricts the flow of current, the voltage at the node 22 is driven. It takes a long time to get to the point where transistor 11 starts to turn off.

Incidentally, the large gate-to-drain capacitor C _GD essentially provides a feedback path so that the BUS OUT (L) bus output (low asserted) signal partially controls the voltage level on node 22 To control the rise and fall of. This is the BUS OUT (L) bus output (low state) with a leading edge (time of FIG. 2, BC) and a trailing edge (time FG of FIG. 2) with moderate rise and fall times. Generates an asserted) signal, providing a "sadie" signal. This signal type reduces ringing and other inherent noise in the signal with very short (ie spherical) rise and fall times. This signal type, as described above, is used to facilitate the flow of current through the capacitor C _GD between the gate and drain during the signal transition of the BUS OUT (L) bus output (asserted low) signal to the gate of the driver transistor. This is achieved by having a large gate-to-drain capacitance C _GD that significantly governs the total capacitance at the terminal.

The foregoing description is limited to specific embodiments of the present invention. However, it is possible to modify and alter the present invention by achieving any or all of its advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as may occur within the spirit and scope of the invention.

Claims (6)

A. A drive device comprising an output terminal and a control terminal, the driver device having a relatively large capacitance between the output terminal and the control terminal to provide a feedback path between the output terminal and the control terminal, and in response to the state of the B input signal. A control buffer device for determining a control node for controlling a control terminal of the driver device, the control buffer device including a current source device for controlling the current flow from and to the control node to turn on and off the driver device in a controlled manner; And the feedback path controls the ratio at which the driver device is turned on and off to control the voltage level of the signal at the output terminal. 2. A driver device according to claim 1, wherein the driver device comprises a source terminal device for connecting the source terminal to a drain terminal for the output terminal to be connected to the bus line and the control terminal for a gate terminal, and for connecting to the source supply power source. And a MOSFET driver transistor device having a capacitance between the gate terminal and the drain terminal that substantially dominates the other capacitance of the bus transmitter circuit. 2. The apparatus of claim 1, wherein the control buffer device comprises a pull-up device comprised of a MOS FET transistor device and a pull-up current source, and a pull-down device comprised of a pull-down MOSFET transistor device and a pull-down current source device; The pull-up MOSFET transistor device and the pull-down MOSFET transistor device are connected together to the control node and controlled in series by the input signal, and the current flowing to the control node through the pull-up MOSFET transistor device and the pull-down MOSFET transistor. Bus control circuit characterized in that is controlled by each current source. 2. The method of claim 1, connected to the gate terminal of the driver device and adapted to repair the input signal to facilitate a fast turn-off of the driver device by adjusting the state of the control node to a selected level when the input signal shifts the level. And a pull-down transistor device controlled by the bus transmitter circuit. A. It consists of a gate terminal that controls the current flow between the drain terminal and the source terminal connected to the bus tines, and a MOSFET transistor device having a large gate-to-drain capacitance to provide a feedback path between the drain terminal and the gate terminal. Bus driver device; And B. (i) a MOSFET pull-up transistor having an on state and an off state, and a pull-up having a pull-up current source for controlling the flow of current through the MOSFET pull-up transistor when in the on state; Device, and (ii) a MOSFET pull-down transistor in the on and off states, and a pull-down with a pull-down current source to control the flow of current through the MOSFET pull-down transistor when in the on state. A buffer device consisting of a device; The MOSFET pull-up transistor and the MOSFET pull-down transistor are controlled in series by the input signal, and either the MOSFET pull-up transistor or the MOSFET pull-down transistor is turned on in response to an alternating state of the input signal. A bus-upper device gate terminal connected to the control node, wherein the up-up device and the pull-down device are connected together to form a control node. 6. The input signal of claim 5, which is connected to a gate terminal of a bus driver device and, when the input signal shifts in level, adjusts the state of the control node to the selected level to facilitate fast turn-off of the bus driver device. And a pull-down transistor device controlled by the maintenance of the circuit.

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