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KR910010747A - Stack Capacitor and Manufacturing Method Thereof - Google Patents

Stack Capacitor and Manufacturing Method Thereof Download PDF

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Publication number
KR910010747A
KR910010747A KR1019890017544A KR890017544A KR910010747A KR 910010747 A KR910010747 A KR 910010747A KR 1019890017544 A KR1019890017544 A KR 1019890017544A KR 890017544 A KR890017544 A KR 890017544A KR 910010747 A KR910010747 A KR 910010747A
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KR
South Korea
Prior art keywords
electrode
charge storage
polysilicon
forming
storage electrode
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Application number
KR1019890017544A
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Korean (ko)
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KR920007794B1 (en
Inventor
엄재철
김필종
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정몽헌
현대전자산업 주식회사
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Priority to KR1019890017544A priority Critical patent/KR920007794B1/en
Publication of KR910010747A publication Critical patent/KR910010747A/en
Application granted granted Critical
Publication of KR920007794B1 publication Critical patent/KR920007794B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

스택캐패시터 및 그 제조방법Stack Capacitor and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제3도는 본 발명에 의한 스택캐패시터 제조 공정단계를 나타낸 단면도1 to 3 are cross-sectional views showing the manufacturing process steps of the stack capacitor according to the present invention.

Claims (4)

스택캐피시터에 있어서, 이동게이트의 드레인에 접속된 폴리실리큰이 게이트 전극의 일정 상부에서 상부방향으로 굴곡된 상태로 연장되어 전하저장전극이 형성되고, 상기 전하저장전극 상부에 캐패시터 유전체막 및 플레이트 전극이 각각 형성되어, 이로 인하여 트랜치 형태와 같이 상부로 연장되어 형성되도록 한 전하 보존전극, 캐패시터 유전체막 및 플레이트 전극에 의해 동일 셀 면적에서 캐패시터 용량을 증가시킨 것을 특징으로 하는 스택캐패시터.In the stack capacitor, the polysilicon connected to the drain of the moving gate is bent upwardly from a predetermined upper portion of the gate electrode to form a charge storage electrode, and a capacitor dielectric film and a plate electrode are formed on the charge storage electrode. And each of which is formed to thereby increase the capacitor capacity in the same cell area by the charge storage electrode, the capacitor dielectric film, and the plate electrode, which are formed to extend upwardly as in the form of a trench. 스택캐패시터 제조방법에 있어서, 실리콘 기판 상부에 이동게이트의 소오스, 드레인 및 게이트 전극 및 게이트전극선을 각각 형성하고 상기 게이트전극 및 게이트 전극선 상부에 절연층을 형성한 다음, 전 영역 상부에 실리콘 질화막을 형성하고 상기 이동게이트의 게이트 전극의 일정 상부에서 드레인 상부 및 게이트 전극선 일정상부까지 상기 실리콘 질화막을 제거하는 단계와, 드레인 상부에 전하저장전극 콘택홀을 형성한 후,전 영역 상부에 폴리실리콘을 침착하여 마스크 패턴을 공정으로 드레인에 접속된 전하저장전극을 형성하는 단계와, 상기 전하 저장전극을 3차원 구조로 형성하기 위하여, CVD산화막을 전체적으로 두껍게 도포한 다음, 마스크 패턴공정으로 상기 전하저장전극의 상부의 CVD산화막 일정 부분을 제거한 후 전 영역 상부에 다시 폴리실리콘을 침착시켜 하부의 전하전장전극에 접속한 폴리실리콘을 트랜치와 같은 형상으로 형성하는 단계와 , 상기 트렌치 형상의 폴리실리콘에 포토레지스트를 채우고 flow시킨다음 마스크없이 노광 및 현상공정을 실시하여 폴리실리콘의 상부높이와 평탄하게 형성하는 단계와, 상기 공정후 폴리실리콘을 CVD산화막 상부면까지 전면 식각한 후, 폴리실리콘 트렌치 형상 내부의 포토레지스트를 식각한 다음 측면의 CVD산화막을 식각하여 트렌치형상의 전하저장전극을 형성하는 단계와, 상기 트렌치 형상의 전하저장전극 상부에 캐패시터 유전체막과 플레이트 전극용 폴리실리콘을 각각가 형성시킨 다음 마스크 패턴공정으로 플레이트 전극을 형성하여 동일 셀 면적에서 캐패시터 용량을 증가시킨 것을 특징으로 하는 스택캐패시터.In the stack capacitor manufacturing method, a source, a drain and a gate electrode and a gate electrode line of a moving gate are respectively formed on a silicon substrate, an insulating layer is formed on the gate electrode and the gate electrode line, and a silicon nitride film is formed on all regions. And removing the silicon nitride layer from a predetermined upper portion of the gate electrode of the moving gate to a predetermined upper portion of the drain and the gate electrode line, forming a charge storage electrode contact hole in the upper portion of the drain, and then depositing polysilicon over the entire region. Forming a charge storage electrode connected to the drain by a mask pattern process, and in order to form the charge storage electrode in a three-dimensional structure, the entire CVD oxide film is applied thickly, and then the upper portion of the charge storage electrode is formed by a mask pattern process. After removing a portion of the CVD oxide film, Depositing polysilicon to form polysilicon connected to the lower charge electric field electrode in a trench-like shape; filling and flowing the photoresist in the trench-shaped polysilicon; Forming a flat top with silicon, and after the process, polysilicon is etched to the top surface of the CVD oxide film, and then the photoresist inside the polysilicon trench is etched and then the CVD oxide film on the side is etched to form a trench. Forming a charge storage electrode, and forming a capacitor dielectric layer and a polysilicon for plate electrode on the trench-shaped charge storage electrode, respectively, and then forming a plate electrode through a mask pattern process to increase the capacitor capacity in the same cell area. Stack capacitors, characterized in that. 제2항에 있어서, 상기의 전하저장전극 및 플레이트 전극은 ,폴리실리콘을 형성한 후 비소 또는 붕소 등의 불순물을 도핑시켜 형성한 다음, 마스크 패턴공정으로 상기 전하저장전극 및 플레이트 전극을 각각 형성하는 것을 특징으로 하는 스택캐패시터The method of claim 2, wherein the charge storage electrode and the plate electrode are formed by doping impurities such as arsenic or boron after forming polysilicon, and then forming the charge storage electrode and the plate electrode, respectively, by a mask pattern process. Stack capacitor, characterized in that 제2항에 있어서, 상기 실리콘 질화막은 두께를 100내지 500정도로 형성하는 것을 특징으로 하는 스택캐패시터.The method of claim 2, wherein the silicon nitride film has a thickness of 100 to 500 Stack capacitor, characterized in that formed to a degree. ※ 참고 사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890017544A 1989-11-30 1989-11-30 Stack capacitor and its manufacturing method KR920007794B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890017544A KR920007794B1 (en) 1989-11-30 1989-11-30 Stack capacitor and its manufacturing method

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Application Number Priority Date Filing Date Title
KR1019890017544A KR920007794B1 (en) 1989-11-30 1989-11-30 Stack capacitor and its manufacturing method

Publications (2)

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KR910010747A true KR910010747A (en) 1991-06-29
KR920007794B1 KR920007794B1 (en) 1992-09-17

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