KR910007648B1 - High performance low pin count for inter - Google Patents

Abstract

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Description

[Name of invention]

High-Performance Low-Pin Countbus Interface

[Brief Description of Drawings]

1 is a block diagram of a data processing system including a system bus using the present invention;

FIG. 2 is a block diagram of nodes in the data processing system of FIG. 1;

3 is a timing diagram showing timing signals used in the data processing system of FIG. 1;

4 is a block diagram of the data interface at the node of FIG. 2;

5 is a block diagram of an arbiter in the data processing system of FIG. 1;

6 is a detailed block diagram of the interface circuit for the data interface of FIG. 2 and the node bus of FIG.

FIG. 7 is a block diagram of the parts of the clock decoder 63 shown in FIG. 2;

8 shows a CMOS output circuit,

9 shows a CMOS input circuit;

FIG. 10 shows timing signals for the node bus 67 shown in FIG.

[Detailed murder of the invention]

[Background of invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the field of data buses in computers, and more particularly to express buses that enable bidirectional communication. Most buses, especially those containing multiple lines that transfer data in parallel format, have time windows while the data on the bus is valid. In synchronous buses, the periodically repeating cycles form the source of timing for these buses, in which each window is formed by an individual signal that is typically active once per bus cycle. During the time between windows, it is possible to change the data on the bus to a new level, which is considered invalid data.

In general, data communication on a bus involves a bus driver that places data on the bus and a storage device that retrieves and stores data from the bus. The bus driver may generally be of one of the following two types. One type is to allow only one bus line to be driven to one level, for example to ground potential, which requires a pull up or precharge device to establish another bus level. The other type is to allow the bus lines to be driven at two levels, which does not require a pre-charge or pull-up device. When the drive signal for controlling a bus driver is in one of the above states, the one type enables the bus driver to cause the bus driver to level the bus (equivalent or equal to the input data input at the input terminal of the bus driver). One of the inverted levels). Also, when the drive signal is in another state, the other type causes the bus driver to stop driving the bus.

Immediately after enabling the bus driver, if the data on the bus still changes, that data is also considered invalid. For specific driver technology and interface characteristics, these data dead times are relatively constant, but in practice depend on similar bus lengths and propagation delays of the bus drivers. As the bus frequency increases, the cycle time of the bus increases and likewise the bus driver enable time decreases. Thus, the bus driver enable time is also reduced while the data is valid.

The memory device stores current data on the bus in response to the operation of the latch signal. The latch signal must be properly adjusted so that the memory device stores data while it is valid on the bus, and a conventional technique of properly adjusting this latch signal causes the memory device to be held while the bus driver is still enabled. To remember the data. Thus, the normal drive signal keeps the bus driving for the "hold time" after the latch signal is activated. Conventional techniques for driving buses between sets of integrated circuit chips may not only determine the voltage level on the bus when the bus is not driven, but also during this time the memory actually stores the data to be transferred over the bus from the bus driver. Since it may not be remembered, the latch is activated before the bus driver is disabled.

The latch signal for obtaining the bus driver generation and hold time requires two separate clock signals, one for the latch signal and one for the drive signal. However, these two clock signals are sufficient in the case of unidirectional communication on a bus line. Full bidirectional communication on the same buslines requires four clock signals (two in each direction) as well as two storage / bus driver pairs.

In addition, since the drive signal used for communication in one direction on the bus must not overlap the drive signal used for communication in the other direction, the bus driver used for communication in each direction must It will not run. For example, if they do not simultaneously drive the bus, even for a short time due to clock distortion, the driver and bus lines will cause current spikes and the transfer of data by the second drive signal will be delayed.

The generation of multiple clocks for bidirectional communication becomes more complicated when such communication must be synchronized to the full system clock. For example, if a system bus coupled with one of the components of the bus has its own bus timing, the four clock signals needed for bidirectional communication can be synchronized according to the timing of this system bus. This synchronization can be difficult for several reasons.

First, the cycle time of the clock used for the system bus can be shortened so that further subdivision of its clock cycle time to obtain four different clock signals that meet the requirements for bidirectional communication.

Second, even if it is possible to obtain their clock signals, their pulse widths can be narrowed so that the logic circuits in the devices cannot reliably react to them.

One design is to eliminate the need for four separate clock signals by using two unidirectional buses. However, the addition of another line set to another unidirectional bus doubles both the number of bus lines and the area that should be dedicated to those lines. In addition, the use of these buses doubles the number of pins on the device that couple to that bus. Thus, for example, transferring 64-bit data in parallel using two unidirectional buses requires an additional 64 pins per interface compared to a single bidirectional bus.

Of all these drawbacks, the increased pin count may be the most serious problem. If the required pin count exceeds the number that can be supported on a single integrated circuit chip, then multiple chips must be used in the circuit. Thus, the design of high-speed circuits involves the development of a technique that minimizes the number of pins required to prevent splitting functionality across chip boundaries. The pin count is often a limiting factor in circuit design due to the limited space of those pins on the printed circuit board.

Another desirable design goal for a high speed bus interface between two buses, such as the user bus and the main system bus, is to replace on the user bus a copy of all communications on the main system bus. This allows a circuit coupled to the user bus to monitor the use of other resources on the main system bus. To meet this requirement, data must be transferred from the system bus to the user bus during each cycle of the system bus. If the user bus uses a single line for bidirectional communication, the bus must operate twice as fast as the system bus allowing two communications (one in each direction) during each cycle of the system bus cycle. This requirement exacerbates the problem of timing.

If a user bus can be synchronized as a system bus and regenerate traffic containing messages placed on the system bus from that user bus, there are several advantages. One advantage of such a system is that one user on the system bus can monitor all other users' system bus transactions. For example, one user can guarantee its validity by having its cache memories check all memory write operations of other users. Users can observe their own system bus transactions in relation to other users' system bus transactions. In addition, users can send messages to themselves via the system bus, making it easy to coordinate node resources such as system bus control and status registers that are accessible through the system bus.

Accordingly, a first object of the present invention is to minimize the number of click signals required for high speed bidirectional bus transmission without overlapping drivers.

It is a second object of the present invention to provide high speed data transfer between two buses so that one bus can get all traffic copies on the other bus.

A third object of the present invention is to allow one bus to provide a return copy of messages sent to another bus.

A fourth object of the present invention is to minimize the number of pins required for the interface to a high speed system bus.

Other objects and advantages of the invention will be set forth in part in the specification, and in part will be obvious from the description, or will be apparent by the embodiments of the invention. The objects and advantages of the invention may be realized or attained by means of the instruments and combinations thereof particularly pointed out in the appended claims.

[Summary of invention]

The present invention solves the problems and disadvantages of the prior art by performing bidirectional transmission between pin terminals and carefully controlling their transmission timing in their respective directions.

In order to achieve the above objects, the interface system of the present invention as broadly described herein provides bidirectional communication with a node having a user portion for processing data and a system bus that propagates data during repetitive bus cycles. to provide. The interface system includes a node bus coupled to the user portion for transmitting data in parallel; Coupled between the node bus and the system bus, coupled between the node bus and the system bus to provide bidirectional communication between the system bus and the node bus and also to copy copies of all data propagated on the system bus and timing means. And transceiver means for supplying the node bus.

The transceiver means also has input terminals coupled to the node bus and output terminals coupled to the system buses for receiving data from the node bus for subsequent transmission during the selected cycle of the system bus. First unidirectional communication means responsive to an active portion of the first clock signal that occurs every system bus cycle; Input terminals coupled to the system bus, each input terminal coupled to the system bus to transfer data propagated on the system bus to each node of the system bus, each of which is the other of the output terminals of the first unidirectional communication means. Terminal connected to a node bus) and an output terminal coupled to the node bus, each of which is connected to the other of the input terminals of the first unidirectional communication means, and is generated in each system bus cycle. Second one-way communication means responsive to the active portion of the two clock signal. Further, the timing means are coupled to the first and second unidirectional communication means to provide the first and second clock signals, so that the active portions of the first and second clock signals do not occur simultaneously, but the second The active portion of the clock signal also causes the second unidirectional communication means to return a copy of the data transferred from the node bus to the system bus to the node bus.

The accompanying drawings, which form a part of the specification, illustrate one embodiment of the present invention and, together with the description, serve to explain the principles of the present invention.

Detailed Description of the Preferred Embodiments

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

A. System Overview

1 shows an example of a data processing system 20 implementing the present invention. At the heart of this system 20 is the system bus 25, which is a synchronous bus that allows communication between several processors, memory subsystems, and input / output systems. Communication over the system bus 25 takes place synchronously using periodic bus cycles. The total bus cycle for this system bus 25 is 64 (nsec).

In FIG. 1, the system bus 25 is coupled to two processors 31 and 35, a memory 39, one input / output device 41 and one input / output device 51. Input / output device 53 is coupled to system bus 25 by input / output bus 45 and input / output device interface 41.

In a preferred embodiment of the data processing system 20, a central arbiter 28 is coupled to the system bus 25. This arbiter 28 supplies timing and bus arbitration signals directly to other devices on the system bus 25, sharing some signals with the devices.

The apparatus shown in FIG. 1 is only one preferred embodiment and should not be construed as limiting the invention. For example, input / output device 53 may be coupled directly to system bus 25 and arbiter 28 does not necessarily operate in the manner described herein.

In the terms used to describe the present invention, the processors 31 and 33, the memory 39, the input / output interface 41 and the input / output device 51 are all referred to as nodes. The term "node" is defined as a hardware device that connects to the system bus 25.

According to the terminology used to describe the invention, the terms "signal" or "line" are used interchangeably with the name of the physical wire. The term "data" or "level" is also used to refer to a value that signals or lines can assume.

The nodes perform transmissions with other nodes via the system bus 25. The term "transmit" is one or more consecutive cycles that share common transmission and common arbitration. For example, a read operation initiated by one node to obtain information from another node on the system bus 25 may be performed by a node at the first node followed by one or more return data transfers from the second node to the first node. Requires sending commands to

The term "transaction" is defined as a complete logical task that can be performed on the system bus 25 and can include one or more transfers. For example, a read operation consisting of a command transfer followed by one or more return data transfers is one transaction. In the preferred embodiment of the system bus 25, an acceptable transaction provides for transfer of different data lengths and includes read write (masked), interlock read, unwrite and interrupt operations. The difference between an interlock readout and a regular or non-interlock readout is that an interlock readout for a particular location retrieves the information stored at that location and subsequently restricts access to the stored information by the interlock readout command. This access restriction is performed by setting the lock mechanism. Subsequent unlock write instructions store the information in a special location and re-remember access to the stored information by resetting the lock mechanism at that location. Thus, the interlock read / unlock write operation is made up of a read-modify-write operation.

Since system bus 25 is a "pending" bus, it facilitates efficient use of bus resources to enable other nodes to use bus cycles that may result in waiting for other responses. For a "pending" bus, one node may initiate a transaction and then other nodes may initiate access to the bus before completion of that transaction. Thus, the node that initiated the transaction does not stall the bus for the entire transaction time.

This contrasts with non-pending buses where the bus is congested during the entire transaction. For example, on the system bus 25, after a node initiates a read transaction to perform a command transfer, the node involved in the command transfer may not be able to immediately return the requested data. Cycles on bus 25 may then be used between the command transfer and return data transfer of read transactions. System bus 25 allows other nodes to use those cycles.

In using the system bus 25, each node may assume different roles to perform the transfer of information. One of these roles is the "commander" defined as the node that initiated the ongoing transaction. For example, a commander in a write or read operation is a node that has requested a write or read operation, but is not necessarily a node that sends or receives data. In the preferred protocol for the system bus 25, one node remains as a commander throughout the entire transaction, even though other nodes may take ownership of the system bus 25 during some transaction cycle. For example, even though one node is controlled by the system bus 25 during the transfer of data in response to the command transfer of the read transaction, that one node is not a command on the bus. This node is called a "responder".

The responder responds to the commander. For example, if the commander initiated a write operation from data node A to node B, node B may become a responder. In addition, in the data processing system 20, a node can simultaneously function as a commander and a responder.

The transmitter and receiver are roles in which nodes assume individual transmissions. A "transmitter" is defined as a node which is an information source placed on the system bus 25 during a transmission operation. A "receiver" is a complement to the transmitter and is defined as a node that receives information placed on the system bus 25 during the transmission operation. For example, the commander during a read transaction acts as a transmitter during command transmission and as a receiver during transmission of return data.

If a node connected to the system bus 25 is required to act as a transmitter on the system bus 25, the node is connected to two request lines CMD REQ (connected between the central arbiter 28 and that particular node). Command request) and RES REQ (responder request). In general, a node's CMD REQ line requires the role of a commander to initiate a transaction on the system bus 25, and the node's RES REQ line serves as a responder to return data or messages to the commander. In general, central arbiter 28 detects when nodes want access to the bus (eg, when request lines are assumed). The arbiter then responds to one of the hypothesized request lines granting node access corresponding to bus 25 according to a priority algorithm. In the preferred embodiment, the arbiter 28 maintains two independent circular queues, one queued for commander requests or one queued for responder requests. Preferably, the responder has a higher priority than the commander request and is processed before the commander request.

The commander request lines and the responder request lines are considered arbitration signals. As illustrated in FIG. 1, the arbitration signal also includes a point-by-point conditional grant signal from the arbiter 28 to each node, and the system bus extends a signal performing a multi-bus cycle transmitter and also, for example, memory and When the same node becomes momentarily unstable due to traffic on the system bus, it extends the system bus suppression signal that controls the initiation of a new bus transaction.

Other types of signals that may constitute the system bus 25 include information transmission signals, response signals, control signals, console / front panel signals, and some miscellaneous notification signals. The information transmission signal includes a data signal, a function signal representing a function to be performed on a system bus during the current cycle, an identification signal identifying a commander, and a parity signal. The response signal generally includes an acknowledgment or confirmation signal generated at the receiver to inform the transmitter of the status of the data transmission.

Control signals include clock signals, warning signals such as identifying low line voltage or low direct current voltage, reset signals used during initialization, node failure signals, default signals used during idle bus cycles, and error default signals. The console / front panel signal may also transmit and receive serial data to and from the system console, boot signals to control the operation of the boot processor during startup, and enable modifications to the erasable PROM of the processor on the system bus 25. Signal, a signal that controls RUN LIGHT on the front panel, and a signal that provides battery power to the clock logic on any node. In addition to the preliminary signal, the notification signal includes an identification signal that allows each node to define its identification code.

2 shows an example of a node 60 connected to the system bus 25. This node 60 is a processor, memory, input / output device or input / output interface. In the example shown in FIG. 2, node 60 includes a system bus interface 64 including node designation logic 65, node bus 67, and data interface 61 and clock decoder 63. Include. It is preferably a standard element for the nodes connected to the data interface 61, clock decoder 63 and node bus 67 system bus 25. The node designation logic 65 using other integrated circuits at the system bus interface 64 is to include the standard circuitry for the interface as the node bus 67, as well as user-specified circuitry to perform the node's specific functions. desirable. In general, data interface 61 is the basic logical and electrical interface between node 60 and system bus 25, and clock decoder 63 is timing for node 60 based on a centrally generated clock signal. In addition, the node bus 67 provides a high speed interface between the data interface 61 and the node designation logic 65.

In the preferred embodiment of node 60 and system bus interface 64 shown in FIG. 2, click decoder 63 includes control circuitry to form a signal that will be placed on system bus 25. The clock signal received from the central arbiter 28 is processed to obtain timing signals for the node designation logic 65 and the data interface 61. Since the timing signal obtained by the clock decoder 63 uses the centrally generated clock signal, the node 60 is operated synchronously with the system bus 25.

3 is a timing diagram showing one bus cycle, a clock signal received by the clock decoder 63 and a timing signal generated by the clock decoder 63. FIG. The clock signal received by the clock decoder 65 includes a time H signal, a time L signal and a phase signal as shown in FIG. Time H and time L are inverted signals of the basic clock signal, and the phase signal is obtained by dividing the basic clock signal into three. The timing signal required by the data interface 61, which occurs once per bus cycle, is provided to the data interface 61, and the complete timing signal sets including the equivalent signals of the timing signals provided to the data interface 61 are buffered. Is supplied to the node designation logic 65. The purpose of this buffering is to prevent the node assignment logic 65 from incorrectly loading timing signals by not adversely affecting the operation of the system bus interface 64. The clock decoder 63 is used to cause the clock signal to generate six subcycles during each bus cycle and also to cause these subcycles to generate six timing signals CXY, where X and Y are one. It represents two adjacent sub cycles combined to form a time signal of.

Each node in the system bus has a set of timing signals corresponding to the timing signals generated by its clock decoder 63. While the corresponding signal occurs at virtually the same time at all nodes throughout the system, changes between the clock decoder 63 and other circuits in the multiple nodes cause a change in timing between the corresponding signals.

These timing changes are commonly known as "clock skews."

4 shows a preferred embodiment of the data interface 61. This data interface 61 includes a temporary memory circuit and a bus driver circuit to provide a bidirectional high speed interface between each line of the node bus 67 and each line of the system bus 25.

Data interface 61 as shown in FIG. 4 includes storage elements 70, 72 and system bus driver 74 to provide a communication path from node bus 67 to system bus 25. FIG. It is preferable. The data interface 61 also includes a memory element 80 and a node bus driver 82 to provide a communication path from the system bus 25 to the node bus 67. The term " memory element " used in the description of the data interface 61 generally means a bistable memory device such as a transparent latch or master slave memory element. Those skilled in the art will appreciate that such terminology is valid.

As shown in FIG. 4, the memory element 70 has an input connected to receive data on the node bus 67 and an output connected to the input of the memory element 72. As shown in FIG. The output of the memory element 72 is connected to the input of the system bus driver 74, and the output of the driver 74 is connected to the system bus 25. Memory elements 70 and 72 are controlled by node bus control signals 76 and 78, respectively, which are generated from timing signals generated by clock decoder 63. The memory elements 70 and 72 provide a two-stage temporary storage function for transferring data from the node bus 67 to the system bus 25. Also, different numbers of storage stages can be used.

System bus driver 74 is controlled by a system bus driver enable signal 79. According to the state of the system bus driver enable signal 79, the input of the system bus driver 74 is coupled to its output to transfer data from the output of the memory element 72 to the system bus 25 or It is either isolated from the output or either. When the system bus driver enable signal 79 separates the input and output of the system bus driver 74, the system bus driver 74 is present at high impedance with respect to the system bus 25. The system bus drive enable signal 79 is also generated by the clock decoder 63 in accordance with a clock signal received at the system bus 25 and a control signal received at the node designation logic 65.

The memory device 80 has an input terminal connected to the system bus 25 and an output terminal connected to the input of the node bus driver 82. The output of this node bus driver 82 is again connected to the node bus 67. The memory element 80, preferably the transparent latch, is controlled by a system bus control signal derived from the timing signal generated by the clock decoder 63. The node bus drive signal 87 controls the node bus driver 82 similar to the manner in which the system bus driver 79 controls the system bus driver 74. Thus, in response to the node bus driver signal 87, the node bus driver 82 couples its input to its output, or separates its input from its output, or as either, a node bus ( 67 provide high impedance.

In order to explain how data is transmitted over the system bus 25, it is important to understand the relationship between the system bus drive enable control signals 85. In an embodiment of the invention, this relationship is shown in FIG. The system bus drive enable signal 79 is nominally driven from the start point to the end point of the bus cycle. This new data is useful for reception on the system bus 25 after the driver propagation time and bus setting time have occurred. In the embodiment of the present invention, the memory device 30 is a transparent latch. The control signal 35 is logically equivalent to the clock C45. The bus timing is useful for the occasional reception of data on the system bus 25 before the non-assuming of the control signal 85. The memory device 80 stores at least the bus data for stabilizing the setup time before the non-temporalization of the control signal 85 to maintain the holding time after the non-temporary control of the control signal 85 in a stable state.

The node bus 67 is preferably an ultra-high speed data bus that allows bidirectional data transfer between the node designation logic 65 and the system bus 25 by the data interface 61. In the preferred embodiment of node 60 shown in FIG. 2, node 67 is an interconnect system that makes point-to-point connections between system bus interface 64 and node designation logic 65. However, according to the present invention, there is no requirement for such point-to-point interconnection.

5 shows a preferred embodiment of a central arbiter 28 also connected to the system bus 25. The central arbiter 28 provides a clock signal for the system bus 25, granting ownership of that bus to nodes on the system bus 25. This central arbiter 28 preferably includes an arbitration circuit 90, a clock circuit 95, and an oscillator 97. Oscillator 97 generates a basic clock signal. Clock 95 provides a timing signal for the arbitration circuit 71, a phase clock signal for the base time H, time L, and timing on the system bus 25. The arbitration circuit 71 receives the commander request and responder request signals to mediate inconsistencies between nodes requesting access to the system bus 25 and also maintains queues for commander and responder requests. Arbitration circuit 71 also provides a control signal to clock 95.

B. Bus Interface Circuit

In the node 60 shown in FIGS. 2 and 4, each data interface 61 is coupled to the corresponding line of the system bus 25 by a single pin terminal. Although the connection part may be directly involved, it is not relevant to the understanding of the present invention, and it is preferable to participate through the resistance. For the reason as described in the background of the present invention, the node bus 67 for the lines of the node bus 67 each data interface 61 corresponds to the lines of the system bus 25 by a single pin terminal. It is preferred to be coupled to the corresponding line of. By using single pin terminals, the node bus 67 can be a single bidirectional bus instead of two parallel buses, thereby minimizing the number of pins or terminals required. In addition, the circuit connected to the node bus 67 need not be split among just a few integrated circuit chips to meet the increased pin count required for the interface to twice the parallel buses.

In addition, in the context of the present invention, a bidirectional transmission complex in a circuit design that achieves a single pin terminal for a single pin terminal for the same reasons as previously described includes data on the system bus 25 provided by the node 60. The need to place copies of all data or messages on the system bus 25 on the node bus 67 is complicated. Doing so allows node assignment logic 65 to observe all data or messages on system bus 25 to help manage system bus 25. By making all data or messages on the system bus 25 available to the node specific logic 65, the node 60 uses resources of the data processing system 20 so that the processes can be transferred to the system bus 25. Recognition can be used to perform self-management techniques for use.

In addition, when bidirectional communication is provided between the data interface 61 and the system bus 25 through the pin terminals for each line of the system bus 25, the node assignment logic 65 monitors its own message to itself. Receive a message on the system bus 25. This connection also causes node assignment logic 65 to send a message by the system bus 25 so that other nodes can monitor the transaction.

Another advantage of the cycle by the cycle visibility of the system bus 25 to the node bus 67 is to maintain cache coherency. According to this use, if a node modifies the content at a memory location accessible through the system bus 25, other nodes can monitor such accesses and their own caches also contain copies of these memory locations. Can be determined.

In order to provide bidirectional transmission capability as well as a single pin terminal connection during each cycle of the system bus 25, the node bus 67 must operate at twice the speed of the system bus 25 as described in the context of the present invention. do. Therefore, node bus 67 should have a shorter transmission time than system bus 25. In a preferred embodiment of the present invention having 64nesc cycle time for the system bus 25, only six subcycles are available due to the circuit requirements at the system bus interface 64, for example composed of CMOS circuits. Do. Six timing signals C12, C23, C34, C45, C56 and C61 each covering two sub cycles are formed for the timing of the node bus 67.

In conventional methods for bidirectional bus transmissions requiring two pairs of clock signals, the timing required to form these signals makes it difficult to perform the use of timing signals in FIG. 3 or other signals due to six subcycles. In practice, the execution only generates a special timing signal for the driver that is longer than the timing signal shown in FIG. 3 (eg, a long signal for three subcycles, such as C123) or a latch shorter than that timing signal. This is made possible by generating a control signal (eg, a single sub cycle signal such as C1 or C2).

In the first case, longer clock signals (ie, C123 and C456) can be used to control the driver, so there is a high probability that two other drivers will drive the bus at the same time, and the clock skew will superimpose them. There is also a high probability of driving the bus simultaneously. In the second case, the shorter bus signal may not be long enough to be effectively used by the logic circuitry or to allow data transfer from the driver to the latch prior to the latch's operation, so the conventional bus driving method uses eight minimum subcycles. Requires a timing signal that can be obtained from This may allow a latch control signal that can continue during the first two drive signals of the two-third subcycle driver signal and three subcycle drive signals that are separated into one subcycle to prevent overlap.

The circuit of the present invention utilizes the phenomenon of bus lines, which was not previously recognized for the problem of bidirectional data transfer when there are a limited number of subcycles, and the problem of data transfer across the integrated circuit chip boundary, thereby adding to other circuits. To avoid the need. Each line of node bus 67 typically has a unique capacitance value of 5-10 pf. The inventors have found that this intrinsic capacitance value can be used to maintain an appropriate voltage level on the bus line even after the bus is no longer driven to a particular level by the bus driver. In order to store the charge as the intrinsic capacitance value of the bus line, the impedance of the capacitance value to the discharge passage must be high. In general, the discharge to the bus is performed through the driver output and the memory element input connected to the bus. The inventors also use devices with high input and high output impedance, especially CMOS devices, which add capacitance values of several pf to bus lines so that the intrinsic capacitance of those bus lines can be removed even after the drive signal is removed from the bus driver. It was found that the data placed on the bus could be used to expand for a period of time to make it valid.

The interface device has a plurality of bus drivers each corresponding to a different line of the bus. Each of these drivers can drive the corresponding bus line to either of two voltage levels. FIG. 6 shows an example of one line of bus 67 connected to the circuitry within node designation logic 65 and data interface 61. The already described bus driver 82 is shown coupled to such a line of bus 67. The bus driver 82 is an input terminal 90 for holding input data to be transferred from the memory device 80 to the line of the node bus 67 and a bus interface terminal actually coupled to the line of the node bus 67. (92). The bus driver 82 also receives a two-state drive signal, so-called driver signal 87 in FIG. 4, in particular having an enable terminal 94 shown as C61 in FIG.

3 shows the timing of the signal C61. When C61 is at a high level (this level is convertible and not required), its output terminal 92 drives the corresponding line of node bus 67 to one of the levels according to the input data. When the signal C61 is at a low level, the bus driver 82 stops driving the bus line to provide a high impedance to the line of the node bus 67.

The interface device also includes a number of latches corresponding to the other line of the bus. As shown in FIG. 6, the memory element 110 is coupled to the same line of the node bus 67 as with the driver 82. As shown in FIG. This memory element 110 has its input terminal 112 coupled to that line of the node bus 67, providing a high impedance to that line. The memory element 110 also has a control terminal 114 for receiving a control signal such as C61 shown in FIG. The control signal at terminal 114 causes the memory element 110 to store the level on the corresponding line of the node bus 67 when the control signal is activated (ie, when C61 is indeterminate). In general, the control signal is activated during signal transmission between states such as either rising or falling sections.

The interface device also includes signal generating means coupled to the plurality of latches for generating drive and control signals for transferring input data at the input terminals of the bus driver to the latches over the bus. 7 shows an example of a clock decoder 61 including a circuit for driving the signal C61. In FIG. 7, the time L signal is received through the buffer 130 and coupled to the clock input of the three bit shift registers 132. After the phase signal passes through the buffer 134, it is provided to the data input terminal of the shift register 132. The Q1, Q2 and Q3 outputs of that register are passed through buffers 140, 138 and 136 to form C12, C34 and C56 signals, respectively. The Q1 output of the shift register 132 supplies a data input to the 3-bit shift register 142 whose clock input is coupled to the time H signal through the buffer 114. Q1, Q2 and Q3 outputs of the register 142 are passed through buffers 150, 148 and 146, respectively, to form C23, C45 and C61 signals. As shown in FIG. 3, the active portion of the clock signal C61 in the preferred embodiment of the present invention continues for about one third of the cycle of the system bus 25. As shown in FIG.

The signal generating means includes first means for switching the drive signal from the first state to the second state in substantially the same period as the corresponding control signal is actuated. In other words, the drive signal does not need to maintain additional subcycles after the latch signal. In the preferred embodiment, clock decoder 63 generates timing signal C61 for both the driver signal and the control signal. As already explained, it is preferable to separate the timing signal C61 sent to the data interface 61 from the timing signal C61 sent to the node designation logic 65. However, these timing signals are substantially the same. This signal separation prevents the characteristics of the node designation logic 65 from changing the timing signal appearing at the data interface 65 due to improper loading, as well as the data interface by the timing signal of the clock decoder 63. (61) and to prevent adverse effects on the service.

The scheme of the present invention has no separate driver hold time for the bus lines as opposed to the conventional scheme. The absence of such a separate driver hold time is possible with the present invention because the intrinsic capacitance of the bus lines is used to maintain the level for those lines even if the node bus 67 is no longer driven active. Because. The discharge paths for the node bus 67 lines are made through the high input impedance of the memory element 110 and the high output impedance of the bus driver 82 when the driver is enabled, so that the lines of the node bus 67 The voltage level for is maintained at a constant level for a relatively predetermined period of time. The time can be calculated from the intrinsic bus capacitance, the capacitance and impedance of the driver 82 and the memory element 110.

The output circuit for the bus driver 82 is preferably a CMOS driver as shown in FIG. The circuit includes a p-channel pull-up transistor 200 and an n-channel pull-down transistor 210 connected in series. The p-channel transistor 200 has a current path coupled between the supply voltage Vcc and the output terminal 92. In addition, the n-channel transistor 210 has a current path coupled between the output terminal 92 and the reference terminal.

The prebuffer 220 sends a gate p signal to control the gate of the p-channel transistor 200 and a gate N signal to control the gate of the m-channel transistor 210. When bus driver 82 is enabled, gate P and gate N signals, respectively, cause transistor 200 to drive node bus 67 to either high or low levels corresponding to " 1 " or " 0 " data. And 210. In particular, when the node bus 67 is driven at a level, the gate P and gate N signals are at a high level (close to Vcc), and when the node bus 67 is driven at a high level, the gate P and the gate are at a high level. The N signal goes low (close to ground). When bus driver 82 is disabled such that terminal 90 is separated from output terminal 92, prebuffer 220 causes the gate P signal to be set to a high level and the gate N signal to a low level. This causes both transistors 200 and 210 to be disabled, typically providing a few megaohms of high impedance to node bus 67.

The input circuit to the latch 110 is also preferably a standard CMOS circuit. An example of this is illustrated in FIG. 9 as an inverter circuit 230 composed of a p-channel transistor 235 and an n-channel transistor 237. Typical input impedance of the circuit of FIG. 9 is also on the order of several megaohms.

By using the driver 82 having the CMOS driver circuit shown in FIG. 8 and the memory element 110 having the CMOS input circuit shown in FIG. 9, data on why the "hold time" is effective is used for the node bus. Holding on 67, the memory element 110 stores its level even if the bus driver 82 is disabled by the drive signal (also C61) in the falling section of the control signal C61. . In this way, the "hold time" overlaps with the hold time, which is regarded as "driver non-overlap time" in a conventional bus drive circuit.

The timing preferably ensures that the control signal is actuated during the " window " when the data is valid on the bus. However, the circuitry of the present invention allows for expansion of the window after the bus driver 82 has timed to actively stop during the node bus 67.

In the case of bidirectional communication over the same line of node bus 67, another driver / memory pair is required to transfer data from node-specific logic 65 to system bus 25. The node designation logic 65 as shown in FIG. 6 includes a bus driver 120 having an input terminal 121, an output terminal 122, and an enable terminal 124. The bus driver 120 is preferably structurally similar to the bus driver 82. The input terminal 121 of the bus driver 120 maintains a second input level as received by the memory device 130, which is shown in FIG. This second input level is coupled to the same line of node bus 67 to which output terminal 122 of bus driver 122 is coupled. The enable terminal in the embodiment of the present invention shown in FIG. 6 is connected to the timing signal C34 provided from the clock decoder 63. FIG.

The data interface 61 preferably includes the memory element 70 as a complementary element to the bus driver 120. The memory element 70 has an input terminal 71 and a control terminal 75. In the embodiment of the present invention shown in FIG. 6, the control signal at the control terminal 75 is also the signal C34.

The signal generating means of the interface device for providing bidirectional communication includes the memory elements 70, 110 and the bus driver for transferring data at each input of the bus driver 82 and 120 to the node bus 67. Generate other driver control signals for 82 and 120. The signal generating means (1) switches a drive signal for one of the bus drivers between the first and second states at substantially the same time as the corresponding control signals are operated, and (2) corresponding (3) Simultaneously drive in a first state of the first and second drive signals at the same time that the control signal for the latches is activated at the same time as the other one of the bus drivers. It includes means to ensure that no.

The clock decoder 63 as shown in FIG. 7 generates timing signals C61 and C34 that do not overlap as can be seen in FIG. In fact, there are time periods between the timing signals C34 and C61 corresponding to subcycles 2 and 5 so that the node buses 67 are not driven simultaneously by the bus drivers 82 and 120. It is guaranteed.

The overall bidirectional data transfer operation as well as other transfer relationships via the data interface 61 can be understood from the timing diagram of FIG. Timing signals C12 to C61 in FIG. 10 are reproduced similarly to current and existing system bus driver enable signals, valid data periods on system bus 25 and control signals 85. When the timing signal C45 is indeterminate at the end of the sub cycle 5, the data on the system bus 25 becomes valid and the transparent latch 80 captures the valid data. The data is then transmitted to the node bus 67 while the timing signal C61 is active because the timing signal, also shown as the drive signal 87, enables the bus driver 82. At the end of the sub cycle 1, for example, when the timing signal C61 is not assumed, the memory device 110 captures data from the node bus 67. In this way, data from the system bus 25 is transferred to the memory element 110 every cycle of the system bus 25.

During subcycles 3 and 4 of the same system bus cycle, even though timing signal C61 is not active, bus driver 120 causes data in memory 130 to be transferred to node bus 67. do.

In the case where C34 is not assumed as shown in FIG. 6, the data transferred to the node bus 67 by the bus driver 120 is captured by the storage element 70, for the reason shown in FIG. This is because of the control signal 75. Later, at the end of the sub cycle 2, the data in the memory element 70 can be captured by the memory element 72 when the node has accessed the bus and GC12 is assumed.

C. Interface System

The interface system of the present invention provides bidirectional communication between a node and a system bus. A system bus, such as system bus 25, propagates data during repetitive bus cycles, and a node, such as node 6, has a user portion, such as node assignment logic 65, to process the data. The interface system includes a node bus, such as node bus 67, coupled to node designation logic 65 to transmit data in parallel.

According to the interface system of the present invention, the transceiver means are coupled between the node bus and the system bus to provide bidirectional communication between the system bus and the node bus as well as to provide the node bus with a copy of all data propagated on the system bus. The data interface 61 in the preferred embodiment of the present invention provides such bidirectional communication.

According to the invention, the transceiver means further comprises first and second unidirectional communication means. This unidirectional communication means has an input terminal coupled to the node bus and an output terminal coupled to the system bus and receive data on the node bus to be transmitted to the system bus during selected cycles of the system bus. As shown in the figure, the first one-way communication means in the preferred embodiment of the present invention includes memory elements 70, 72 and a bus driver 74. The memory element 70 has an input terminal 71 coupled to the node bus. In addition, the output of the memory device 70 is coupled to the memory device 72. The bus driver 74 has an output terminal 77 coupled to the output of the memory element 72 and coupled to the system bus 25.

As described above, data on the node bus 67 is received in the memory element 70 during the operating portion (e.g., fall time) of the clock C34. The data is then transferred to the memory element 72 when it is operated by the signal GC12 as shown in FIG. Signal GC12 is the AND product of two signals C12 and GC12EN. The C12 signal shown in FIGS. 3 and 10 is one of the timing signals generated by the clock decoder 63, and the GC12EN signal indicates that the node 60 is a transmitter on the system bus 25 when it is active. And a signal indicating that data can be transmitted on the system bus 25 via the data interface 61. The GC12 signal is then generated by the clock decoder using signals from the arbiter 28 and the node designation logic 65.

The driver 74 as shown in FIGS. 4 and 6 has as its input a drive signal called system bus drive enable signal 79, which is received from the clock decoder 63 and stored in the memory element 72. Data is transferred on the system bus 25. The system bus drive enable signal 79 is generated upon a request from the node designation logic 65 as well as a request for some permission signal received from the data processing system 20. Thus, data is transmitted on the system bus 5 only during the cycles of the system bus 25 when the node 60 is a transmitter.

The second one-way communication means according to the invention has an input terminal coupled to the system bus and an output terminal coupled to the node bus. The input and output terminals of the second single direction communication means are respectively coupled to the corresponding output and input terminals of the first single direction communication means. The second one-way communication means also transmits data propagated on the system bus to the node bus every cycle of the system bus.

The memory device 80 as shown in FIGS. 4 and 6 has an input terminal coupled to the system bus 25 and is enabled by the clock signal C45 received at the clock decoder 63. The bus driver 82 has an output terminal 92 coupled to the node by the node bus 67 and coupled to the input terminal 71 of the corresponding memory element 70. The enable terminal 94 of this bus driver 82 is coupled to the C61 signal.

The interface system of the present invention also includes timing means coupled to and controlling the first and second unidirectional communication means. According to the present invention, the timing means controls the first one-way communication means to receive data from the node bus during the selected active portion of the first clock signal, and also controls the data on the system bus during the active portion of the second clock signal. The second one-way communication means is controlled for transmission to the node bus. The first means also generates first and first clock signals so that active portions of the clock signals are generated every cycle and do not overlap.

As already explained, the clock decoder 63 generates clock signals C34 and C61. The memory element 70 receives data at the end of clock C34 and transfers the data to the system bus 25 during selected cycles of the system bus 25. In addition, the memory device 80 receives data from the system bus 25 during the timing signal C45, and the driver 82 transfers the data to the node bus 67 during the C61 clock cycle. Thus, since data transmitted during every cycle of the system bus 25 is transmitted to the node bus 67 to permit the node bus 67, the node designation logic 65 transmits all the data transmitted on the system bus 25. Get a picture of the message. Since clock cycles C45 and C61 occur once per system bus cycle, the transfer from system bus 25 to node bus 67 also occurs once per cycle of system bus 25.

When used together, the bus interface circuit and interface system of the present invention provide several advantages over prior art systems. The benefits include high speed bus transfers using a minimum number of clock signals, thus allowing high speed data transfers between buses so that one bus, for example a node bus, can obtain a copy of all messages over another bus, such as a system bus. To provide. By providing such a copy and using a single pin connection to the system bus 25, a node coupled to the node bus can not only monitor its own messages, but also send messages back by that system bus. Nodes can monitor the messages.

It will be apparent to those skilled in the art that various modifications and variations can be made to the bus interface circuits and interfaces of the present invention without departing from the spirit and scope of the invention. It is intended that the present invention cover such modifications and variations as come within the scope of the appended claims and their equivalents.

Claims (14)

1. An interface system for providing bidirectional communication over a node bus having a user portion that processes data and a system bus that propagates data during repetitive bus cycles, the interface system coupled to the user portion to transfer data to and from the node. A node bus for performing data transfer of the; A transceiver means coupled between the node bus and the system bus to provide bidirectional communication between the system bus and the node bus and to provide the node bus with all copies of data transmitted on the system bus, The transceiver means has input terminals coupled to the node bus and output terminals coupled to the system bus, and selected cycles of the system bus in accordance with the active portions of the first clock signal that occur in each system bus cycle. Each system having a first one-way communication means for receiving data from said node bus for subsequent transmission to said system bus, and input terminals coupled to said system bus and output terminals coupled to said node bus, respectively. Active parts of the second clock signal that occurs every bus cycle. Thus, for transmitting the data propagated on the system bus to the node bus at every cycle of the system bus, the input terminals are respectively connected to the other output terminal of the output terminals of the first unidirectional communication means. Wherein the output terminals each comprise one second one-way communication means as it is connected to the other input terminal of the input terminals of the first one-way communication means; Coupled to the first and second unidirectional communication means such that active portions of the first and second clock signals do not occur simultaneously, and wherein the active portions of the second clock cause the second unidirectional communication means to And timing means for providing said first and second clock signals to return a copy of data transferred from a bus to a system bus to a node bus. 2. The apparatus of claim 1, wherein the first one-way communication means is coupled to the input terminals of the first one-way communication means to temporarily store data from the node bus during active portions of the first clock signal. Coupled to said output terminal of said first storage means and said first one-way communication means to store said stored data during selected active portions of a third clock signal synchronized with a first clock cycle. And first bus driver means for transmitting from said first storage means to said system bus. The second storage means according to claim 1 or 2, wherein the second single direction communication means is coupled to the input terminals of the second single direction memory means to temporarily store data propagated on the system bus. And coupled to the second storage means and to the output terminal of the second single direction memory means for transferring the stored data from the second storage means to the node bus during active portions of a second clock signal. An interface system comprising a second bus driver means. The interface system as recited in claim 2, wherein said first storage means comprises two sequentially coupled storage elements for providing two-stage storage of data received from a node bus. 3. The interface system of claim 2, wherein said timing means comprises second means for forming said third clock signal from signals generated at said user portion and timing signals received at said system bus. . A data transfer apparatus for providing bidirectional communication over a node bus having a user portion processing data and a system bus propagating data during repetitive bus cycles, the data transmission apparatus comprising: a plurality of lines, each having a unique electrical capacitance, A node bus for maintaining the data on the node bus for a predetermined period of time voltage levels, the data bus transferring the data; A node bus interface means coupled between the user portion and the node bus to transfer data between the node bus and the user portion, wherein the node bus interface means respectively correspond to the other line of the node bus, An input terminal for holding first input data to be transmitted to a corresponding line of the node bus, a bus interface terminal coupled to a corresponding line of the node bus, respectively, in which the first bus driver causes the corresponding node bus to be in a first state; A first driving the line to one of two levels by the first input data and in the second state causing the first bus driver to stop driving the corresponding bus line to provide a high electric impedance at its bus interface terminal; A plurality of first bus drivers including an enable terminal for receiving a drive signal, each of the Corresponding to the other line of the node bus, respectively, an input terminal coupled to a first latch providing a high electrical impedance at the corresponding line of the node bus and its input, the first latch causes the first control signal to be A plurality of first latches including a latch control terminal for receiving said first control signal which, when activated, stores said voltage level on a corresponding node bus line; A transceiver means coupled between the node bus and the system bus to provide bidirectional communication between the system bus and the node bus and to provide the node bus with a copy of all data propagated on the system bus. The transceiver means having inputs coupled to the node bus and output terminals coupled to the system bus for receiving data from the node bus to be transmitted to the system bus during selected cycles of the system bus. And an input terminal coupled to a second latch, each corresponding to the other line of the node bus, the second terminal providing a high electrical impedance at the corresponding line of the node bus and its input terminal, respectively. Causes the second control signal to actuate on the corresponding node bus line. A first one-way communication means comprising a plurality of second latches having a latch control terminal for receiving a second control signal for storing a level, an input terminal coupled to said system bus and a node bus coupled to said node bus; And output terminals, each of which is connected to the other terminal of the input terminals of the first one-way communication means, so that data propagated on the system bus is transmitted to the node bus every cycle of the system bus. An input terminal holding a second input data to be transmitted to a corresponding line of the node bus, each coupled to a corresponding line of the node bus, respectively; Bus interface terminal, in the first state, causes the second bus driver to connect the corresponding node bus line by second input data. Enable terminal to receive a second drive signal that drives at one level and, in the second state, causes the second bus driver to stop driving the corresponding bus line to provide a high electrical impedance at its bus interface terminal. Said second one-way communication means comprising a plurality of second bus drivers having a; Coupled to the node bus interface means and the first and second unidirectional communication means for controlling data transmission between the user portion and the system bus, the first control signal being actuated and simultaneously generating a first drive signal. By switching from the first state to the second state, the second control signal is activated and the second drive signal is switched from the first state to the second state so that the first and second drive signals are not simultaneously generated in the first state. And a timing means for disabling the data transmission apparatus for bidirectional communication. 7. The second latch of claim 6, wherein the first one-way communication means is respectively coupled to another latch of the plurality of second latches, the second latches storing voltage levels stored during selected active portions of a third clock signal. And a plurality of third bus drivers for transmitting the data to the system bus. 7. The apparatus of claim 6, wherein the second one-way communication means are each coupled to another one of the second bus drivers, and having a plurality of third latches for temporarily storing data propagated on the system bus. Characterized in that the data transmission device. 8. The data transfer apparatus of claim 7, wherein the second latches each comprise two sequentially coupled storage elements to provide a second gear of data received from the node bus. A data transfer apparatus for providing bidirectional communication over a node bus having a user portion processing data and a system bus propagating data during repetitive bus cycles, the data transmission apparatus comprising a plurality of lines each having a unique electrical capacitance, A node bus for holding the data on the node bus for a predetermined period of time voltage levels that are indicated and for transmitting the data; A node bus interface means coupled between the user portion and the node bus to transfer data between the node bus and the user portion, the node bus interface means respectively corresponding to the other line of the node bus; An input terminal for holding first input data to be transmitted to a corresponding line of the node bus, a bus interface terminal coupled to a corresponding line of the node bus, respectively, and causing the first CMOS bus driver in a first state to correspond to the corresponding node. Drive the bus line to one of two levels by the first input data and in the second state cause the first CMOS bus driver to stop driving the corresponding bus line to provide high electrical impedance at its bus interface terminals. A plurality of first CMOS bus drivers comprising an enable terminal for receiving a first drive signal An input terminal coupled to a first latch, each corresponding to the other line of the node bus, the first latch providing a high electrical impedance at a corresponding line of the node bus and at its input, the first latch causing a first control A plurality of first CMOS latches for receiving a first control signal for storing data corresponding to a voltage level on a corresponding node bus when the signal switches between a first state and a second state; A transceiver means coupled between the node bus and the system bus to provide bidirectional communication between the system bus and the node bus and to provide the node bus with a copy of all data propagated on the system bus. The transceiver means having inputs coupled to the node bus and output terminals coupled to the system bus for receiving data from the node bus to be transmitted to the system bus during selected cycles of the system bus. And an input terminal coupled to a second CMOS latch, each corresponding to the other line of the node bus, each providing a high electrical impedance at the corresponding line of the node bus and its input terminal, the second CMOS latch. Responds when the second control signal switches from the first state to the second state. A plurality of second CMOS latches having a latch control terminal for receiving a second control signal for storing data corresponding to a voltage level on the node bus line, each of which responds to another of the plurality of second CMOS latches, An input terminal coupled to an output terminal of a corresponding one of the second CMOS latches, the third control signal receiving a CMOS flip-flop to cause a signal to be stored at the output of the corresponding second CMOS latch when the third control signal is activated A plurality of CMOS flip-flops, each having a flip-flop control terminal, and an input terminal coupled to the other bus of the system bus, each coupled to an output of a corresponding one of the third latches, the system bus A bus interface terminal coupled to the corresponding one line of the second bus driver in a first state according to the output of the third latch; A first unidirectional communication means comprising a plurality of second CMOS bus drivers having an enable terminal for receiving a second drive signal for driving a line, the input terminals coupled to the system bus and the Having output terminals coupled to the node bus, the output terminals being respectively connected to the other input terminal of the input terminals of the first unidirectional communication means, the input terminals being respectively of the first unidirectional communication means; And to transmit data propagated on the system bus to the node bus at every cycle of the system bus, connected to the other output terminal of the output terminals, each corresponding to the other line of the system bus. An input terminal coupled to the input terminal of the second single direction communication means, respectively, causing a fourth latch to perform the second single direction; A plurality of fourth CMOS latches having a latch control signal for receiving a fourth control signal for storing data corresponding to a voltage level on a corresponding input terminal of a new means, each of the other line of the node bus and the plurality of An input terminal corresponding to the other line of the fourth latch of, respectively, coupled to an output terminal of the fourth latch and holding second input data to be transmitted to a corresponding line of the node bus, the corresponding terminal of the node bus Bus interface terminal coupled to the line, causing a third bus driver to drive the corresponding node bus line to one of two levels by a second input data in a first state and to drive a corresponding bus line in a second state Has an enable terminal for receiving a third drive signal providing a high electrical impedance at its bus interface terminal. Of the 3CMOS and a second unidirectional communication means including a bus driver; Coupled to the node bus interface means and the first and second unidirectional communication means for controlling data transfer between the user portion and the system bus, the first drive signal between the first and second states and a second drive signal; And timing means for simultaneously switching the control signals and simultaneously switching the third drive signal and the first control signal between the first and second states so that the first and third drive signals are not simultaneously generated in the first state. A data transmission device for bidirectional communication, characterized in that. A method in which the second terminal is used to hold valid data for a predetermined period of time during each cycle occurrence of a plurality of repetition cycles for high speed bidirectional communication between the first and second terminals, the selection as the second terminal. Receiving first data from the first terminal during the active portion of the first clock signal occurring during each of the repeat cycles for efficient transmission; Transmitting the second data from the second terminal to the first terminal during the active portion of the second clock signal occurring during each of the repetition cycles to provide all of the second data to the first terminal; ; Generating first and second clock signals such that their active portions do not occur simultaneously, such that the first terminal and the second data transmitted include a copy of the first data transmitted to the second terminal. High speed bidirectional communication method characterized by. 12. The method of claim 11, wherein the first data receiving step includes temporarily storing the first data during the active portion of the first clock signal, and the second level transmitting step includes the second data during the active portion of the third clock signal. And temporarily storing the data. 13. The method of claim 12, further comprising generating the third clock signal such that a portion of the active portion of the third clock signal occurs concurrently with the active portion of the second clock signal. 12. The method of claim 11, wherein transmitting the second data from the second terminal includes a substep of storing the second data.

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