KR900002470Y1 - Noise cutting circuit - Google Patents

Abstract

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Description

Consonant Elimination Circuit

1 is a digital noise cancellation circuit according to the present invention.

2 is an operating waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

10, 20, 30: 1st, 2nd, 3rd circuit 40: inverter

50, 60: Andgate

The present invention relates to a noise canceling circuit, and more particularly, to a circuit for removing noise included in an encoder pulse of a motor.

In general, in a system for controlling the position by counting the number of encoder pulses of a motor, the controlled position is converted according to the counting number of encoder pulses that are coupled to the axis of the rotating motor to generate a pulse according to the rotation of the motor. Therefore, when noise is included in the encoder pulse for position control, an error occurs in the counting of the encoder pulse due to the noise force, which makes it difficult to accurately control the position.

Accordingly, an object of the present invention is to provide a noise canceling circuit for removing the input noise included in the encoder pulse.

Clock synchronization delay means for synchronizing the input data of the present invention for achieving the above object with a clock pulse or outputting first, second, and third delayed data, respectively, and the clock synchronization delay means. Signal pulse output means for inputting the first, second, and third output delay data and outputting the signal pulse from which the noise is removed, and inputting the delay data and the clock pulse output from the clock synchronization delay means within two cycles of the clock pulse. The pulse is characterized by consisting of noise detection means for detecting a noise signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a first latch circuit 10 for latching a data signal DT into a clock pulse CLK and outputting a synchronous delay to the clock pulse CLK according to the present invention. The second latch circuit 20 which latches one cycle delay signal output to the first latch circuit 10 with the same clock pulse CLK and outputs two cycles of delay, and the second cycle delay output from the second latch lightning arc 20. A third latch circuit 30 for latching the delayed signal to the clock pulse CLK and outputting a 3-cycle delay and outputting an inverted data signal, and an inverter 40 for inverting and outputting the input clock pulse CLK. And inputting the first, second, and third delay data output from the first, second, and third latch circuits 10, 20, and 30 to output a predetermined signal when the input data is all high. First and second cycle delay data output from the gate 50, the first and second latch circuits 10 and 20, and output from the third latch circuit 30 The inverted clock pulse to be output from the three-cycle delay inverted data and the inverter 40 ( ) And an AND gate 60 for outputting a signal within one cycle of the clock pulse as a noise pulse.

2 is a waveform diagram showing that the operation waveform noise signals of the respective parts of FIG. 1 are removed.

Hereinafter, a vertical example of FIG. 1 according to the present invention will be described with reference to the waveform diagram of FIG. 2.

Now, the reset signal as shown in FIG. 2 (b) is applied to the first, second and third latch circuits 10-30 while the clock pulse signal CLK is input as shown in FIG. 2 (a). Once input, the first, second, and third latches 10-30 are initialized to logic "0" as shown in FIG.

At this time, when the encoding pulse data 3 including the noise 1 or the noise 2 or 2 'is input to the first latch circuit 10 as shown in FIG. When the clock pulse CLK becomes the rising edge, the noise 2 of FIG. 2C is clocked by the first latch circuit 10 and is delayed by one cycle as shown in FIG. The output is output to the AND gates 50 and 60 and simultaneously input to the terminal D of the second latch circuit 20.

Then, the noise 1 less than one period of the input clock CLK and out of the edge state of the clock pulse CLK is removed.

The second latch circuit 20, which has received a signal outputting one cycle delay from the first latch circuit 10 as shown in FIG. 2d, latches an input signal when the clock pulse CLK is rising edge. As shown in (b) of FIG. 2B, the delay output is applied to the AND gates 50 and 60 as much as twice the period of the clock pulse CLK, and is output to the second latch circuit 30.

On the other hand, the third latch circuit 30 inputs the signal output from the second latch circuit 20 as shown in FIG. 2 (e) by clocking and latching the signal inputted by the clock pulse CLK. The signal of FIG. F is output to the AND gate 50, and the signal of the second diagram g inverted from the signal of f is output to the AND gate 60.

In addition, the inverter 40 inverts the clock pulse CLK and outputs it to the AND gate 96.

Accordingly, the AND gate 50 inputs a delayed signal of one cycle, two cycles, and three cycles as shown in FIGS. ) Outputs only input data (3 in the second c) having a width of two or more clock cycles as normal pulses as shown in FIG. 2 (h), and (1) floating (2) (2 ') As such, signals that do not have two clock cycles are regarded as noise and are output.

In addition, the inverted signals of the delayed output signals of the first and second latch circuits 10-20 (d) and (f) and the third latch circuit 30 are outputted from the first and second latch circuits 10-20. The input gate 6 inputs the output pulse of the inverter 40 which inverts and outputs the input clock pulse CLK, and regards the pulse signal input within one cycle of the clock pulse as noise. Output as the noise detection signal as i).

Therefore, noise pulses (1), (2), (2) of (1), (2), (2 '), (3) of FIG. ') Is removed and only the signal in (3) of FIG. 2 (c) is outputted to the AND gate 50 as a normal pulse.

As described above, if the period of the pulse signal input through the digital signal line is a signal within two periods of the clock pulse, it is determined as noise and is outputted. By judging and outputting the signal as a pulse, the noise included in the motor encoder pulse can be completely eliminated, while at the same time, the noise can be easily removed from a system processing all digital signals.

Claims (1)

In the noise canceling circuit of a system for processing a digital signal, a series of at least three latches connected in series with a clock pulse CLK having a predetermined period is inputted, and serial data inputted to the first input terminal of the serially connected latches. Clock synchronization delay means 10-30 for synchronizing the clock pulse CLK to output the first, second, and third delayed outputs of the serial data and inverting the third delayed output; Input to at least two cycles of the clock pulse CLK by being connected to the first, second, and third delay output terminals of the synchronous delay means 10-30 by ANDing the first, second, and third delay output data. A signal pulse output gate 50 for gating and outputting only data as normal data, an inverter 40 for inverting and outputting the clock pulse CLK input signal, an output terminal of the inverter 40 and the clock synchronization delay means ( 10-30), first and second delay output terminal and inversion A gate 60 connected to a third delayed output terminal to logically multiply the inverted clock with the first and second delayed outputs and the inverted third delayed output to detect a pulse less than two cycles of the clock pulse CLK as a noise signal; Circuit, characterized in that consisting of.