KR890001847Y1 - Data collector circuit - Google Patents

Abstract

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Description

Data collector circuit

1 is a frame configuration diagram of data.

2 is a circuit diagram of a data collector according to the present invention.

3 and 4 are operational waveform diagrams of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: shift register 11: first latch circuit

12: counter 13: demultiplexer

14: second latch circuit

The present invention relates to a data collector circuit, and more particularly, to a circuit for collecting data separated in each frame in a predetermined frame.

In a conventional private exchange, when a pair of telephone lines are used to connect a telephone and a data terminal capable of transmitting and receiving analog voice signals and transmitting and receiving digital data, two pairs of transmission lines have to be constructed separately.

In general, in order to solve the above-mentioned disadvantages, both a signal and a voice signal of a data terminal are converted into a digital signal and transmitted and received with a digital telephone, so that voice and terminal data can be simultaneously used in a pair of telephone lines.

There are three methods of communication between the private exchange and the digital telephone: frequency division, echo cancellation, and time compression.

As a circuit for taking frame synchronization and clock synchronization and providing an essential timing signal in the time compression scheme as described above, a two-wire digital disclosed in Patent Application No. 85-8055 filed on October 30, 1985 by the applicant of the present application The synchronization and timing signal generation circuit of the switch can be used.

In addition, there is a communication method of 2B + D Pommel, which is currently recommended in the CCITT regulations, in the communication method for simultaneously transmitting and receiving voice data and digital data during a private exchange and a digital telephone period.

The communication method of 2B + D Pommel is called Basic Access, and in this basic access, the transmission rate of B channel, which is a channel of voice and digital data, is 64Kbps, and the transmission rate of D channel, which is a signaling data channel. Is recommended at 16 Kbps.

The present invention relates to a signal data collector circuit among data having a frame structure shown in FIG. 1 in transmitting and receiving information using a time compression method.

1 is a diagram showing the configuration of one frame used in the present invention. The first bit of one frame is the synchronization bit for synchronizing the frame synchronization which always becomes "1", and the one bit used as synchronization data for collecting signal data. It consists of a signal synchronization bit, two signal bits each serving as one bit of instruction information, eight bits of audio data and eight bits of data.

The detailed description of the frame configuration of FIG. 1 described above is described in detail in the foregoing patent application No. 85-8055.

In one frame as described above, two bits of logic “Low” information may be added to remove switching noise due to switching switching in transmitting and receiving data.

The above-mentioned one frame information has a burst cycle of 125msec and is repeatedly transmitted and received by 2B + D foam between the private exchange and the digital telephone period, which occurs from the sync bit indicating the start of the current frame to the sync bit of the next frame. With 125㎲ec of time, one frame of information can be repeatedly transmitted and received every 125㎲ec.

As described above, the transmission / reception method using 2B + D Pomel's basic access has 16Kbps transmission rate of B channel and 16Kbps transmission rate of D channel, so that signaling data can be loaded in the time compression method having 125㎲ec as one frame. The D channel data can not exceed 2 bits.

In addition, the data of each B channel, which is a voice and digital data channel, cannot exceed 8 bits or more.

The signaling data of FIG. 1 is used as data for indicating control information, dial information, specific display information, and specific messages of the digital telephone and the private exchange period.

In this one-frame configuration, two-bit signals need to be an eight-bit group in order to be represented by byte operation information.

That is, in order for the microprocessor for analyzing dialing information or specific message information to be expressed as information for easy analysis, it is necessary to collect signal bits transmitted at 16 Kbps transmission speeds by 2 bits.

Therefore, if a signal carried in one frame is two bits, and a microprocessor performing byte operation operation becomes 8 bits, which is a unit for easy signal analysis, four frames must be collected and a synchronization signal indicating that 8 bits are collected. The signal sync bit is used to play this role.

Accordingly, an object of the present invention is to provide a circuit that collects information separated in each frame and makes 1 byte of information.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a data collector circuit according to the present invention, and a shift register 10 for extracting signal sync bit data and signal data contained in each frame, and a receive enable signal RXEN and 1/64 times the frame period. Inputs a clock of a period and gates the gate to the shift register 10 so as to shift the received restoration data (REDA) within a receivable time, and inputs the extracted signal sync bit data The first latch circuit 11 and the AND gate 18 outputting a reset signal for collecting the signal data into one byte, and the receive enable signal RXEN are inverted to extract the first latch circuit 11. An inverter 16 which provides a clock to the first latch circuit 11 to latch the received signal synchronization data, and the reset signal and one frame at a period, A counter 12 for generating a control signal for counting a predetermined clock and collecting the signal data in one byte, and a signal for outputting from the shift register 10 using the output signal of the counter 12 as a selection control signal; A demultiplexer 13 for continuously latching data by 2 bits and outputting the data in one byte, an inverter 17 for inverting the transmission frame synchronization signal TXFS and providing the enable signal of the demultiplexer 13, and a predetermined clock; The second latch circuit 14, which makes the output data of the demultiplexer 13 stable data and synchronizes with the received frame synchronization signal, and gates the output of the counter 12 to the second in a predetermined frame period. The NAND gate 19 provides a clock of the latch circuit 14.

In the above configuration, the demultiplexer 13 has a latching function, and F4723 / 34723 of FAIRCHILD, a chip maker in the United States, may be used.

3 and 4 are timing diagrams for explaining the operation of the data collector circuit according to the present invention of FIG.

In the third diagram, TXFS is a transmission frame synchronization signal, TXEN is a transmission enable signal, RXFS is a reception frame synchronization signal, RXEN is a reception enable, CLK1 is a clock synchronized with the reception enable signal RXEN, and REST is a reset signal. This is the output of the AND gate 18.

QA and QB are counting outputs of the counter 12, and the signal data is a 2-bit signal obtained by separating the shift-restored data reda by the shift register 10 of FIG. 2 by the gating clock of the AND gate 15. FIG. As data, it shows that the reception enable signal RXEN of the next frame is maintained until input when there is no gating clock of the AND gate 15.

RXEN in FIG. 4 is the same signal as RXEN in FIG. 3, and the output of the AND gate 15 is a gating pulse train based on the clock CLK2 of 1/64 times the clock CLK1 and the logical product of RXEN. Is the received restoration data, in which two empty bits are added to the total configuration bits of the frame as shown in FIG.

D0-D20 is a waveform outputted by the shifting operation of the shift register 10 when the gate clock of the AND gate 15 is input to the clock terminal of the shift register 10.

Hereinafter, the present invention will be described in detail with reference to the timing diagrams of FIGS. 3 and 4.

The second transmission frame sync signal TXFS is a clock generated by the clock generation circuit of the private exchange, and is a clock generated for use as a synchronization signal for transmitting a transmission signal to a digital telephone connected to the private exchange. As shown in FIG.

In addition, the transmit enable signal TXEN of FIG. 3 is a clock indicating the timing of transmission from the private exchange to the digital telephone, and the receive frame synchronization signal RXFS is a receive synchronization signal. The receive enable signal RXEN is a clock for receiving data transmitted from the digital telephone to the exchange. The private enabler transmits the transmit enable signal TXEN to the digital telephone to receive the digital telephone and then receives the digital telephone. This signal is output as shown in Fig. 3 with a delay time including the time delay of the transmission line from the end of the transmission to the private exchange.

On the other hand, the clock CLK1 is synchronized with the reception frame synchronization signal RXFS and has the same period as the reception frame synchronization signal RXFS, and the clock CLK2 is synchronized with the reception enable signal RXEN. And a clock having a period 1/64 times the clock CLK1. At this time, the period of the received frame synchronization signal (RXFS) is 8KHZ period of 125kHz. Accordingly, it can be seen that the clock CLK1 is a clock of 8KHZ.

In addition, Receive Restoration Data (REDA) of FIG. 2 is data restored from digital telephones, and is composed of 22 bits in which total bits of one frame of FIG. 1 are added to two null bits. , As shown in FIG.

Now, when the enable signal RXEN and the clock CLK2 are inputted to the AND gate 15 of FIG. 2, when the receive enable signal RXEN is high, as shown in FIG. 4, the clock CLK2 becomes the AND gate. Gated at 15) and output as shown in FIG. 4. The clock is provided to the clock terminal CK of the shift register 10. In FIG. Therefore, when the reception restoration data (REDA) as shown in FIG. 4 is input to the data input terminal (D) of the shift register 10 as the data, the shift register 10 shifts the input reception restoration data (REDA). In this case, the shifted output is output as shown in FIG.

Therefore, the gating operation of the AND gate 15 is stopped when the reception enable signal RXEN changes from “high” to “low”, so that the shift register 10 stops the shift operation, and the output of the output terminal D20 is stopped. Becomes the data SS of the signal synchronization bit.

On the other hand, the signals output to each of the output terminals D19 and D18 are each outputted with two bits of signal data S1 and S2.

Accordingly, the shift register 10 is a circuit for extracting the signal sync bit data SS and the signal data S1 and S2 of the reception restoration data REDA.

The signal sync bit data SS extracted as described above is input to the data input terminal D of the first latch circuit 11. In this case, the inverted signal of the receive enable signal RXEN of FIG. 4 is provided to the clock of the first latch circuit 11 by the inverting operation of the inverter 16, so that the output of the latch circuit 11 is output to the fourth. In Fig. T, the data SS of the signal synchronization bits extracted from the shift register 10 is latched, as shown in FIG.

Therefore, the data signal of the latched signal sync bit is always latched and output to the line 20 when the receive enable signal RXEN falls from "high" to "low".

However, the data of this signal sync bit is set to "1" in the first frame, and all of them are set to 0 from the second frame to the fourth frame to be "1" every 4 frames. Accordingly, one input line 20 of the AND gate 18 becomes “high” for one frame section in four frame periods as shown in FIG. 3, and the AND gate 18 is logically multiplied by the enable signal RXEN. The reset signal REST, which is the output of N, is as shown in FIG.

Therefore, the counter 12 is reset by this signal, and when the reset is released, the counter CLK1 is counted in synchronization with the receive enable signal RXEN, and the output change of the output terminals QA and QB of the counter 12 is changed. It is as shown in FIG.

The QA and QB outputs of FIG. 3 are input to the selection terminals A and B of the demultiplexer 13 of FIG. 2, and the output terminals D19 of the shift register 10 when the signals of QA and QB are "00". The signal data S1 and S2 of the frame output from (D18) are input to the data input terminal DA (DB) of the demultiplexer 13 and latched in the upper two bits of the output terminals Q0a and Q0b. 2 bit QA QB = "11" of the next output terminal Q1a (Q1b) if QA QB = "01". In this case, by latching and outputting 2 bits of the last output terminals Q3a and Q3b, 8 bits of signal data input during 4 frames are selected and latched.

That is, the output of the signal data is demultiplexed and shown in a latched state as shown in FIG. 3 as shown in FIG. Inverted by the enable terminal ( ), The data of the 8-bit data D0-D7 appear as valid data in the VD portion of FIG.

For example, if the demultiplexer 13 is F4723 / 34723 manufactured by FAIRCHILD Co., Ltd. as described above, the enable terminal ( ) Is the "low" input, the output of the counter 12 latches the input data to the output terminal as described above, and the enable terminal ( If ")" is "high", the demultiplexer 13 transitions to the memory mode, so that the signal data input by 2 bits over 4 frames is effectively output as 8 bits of data. This valid data is inputted to the clock input terminal CK of the second latch circuit 14 through the NAND gate 19 through the NAND gate 19 of the counter 12 which counts the clock CLK1 synchronized with the receive enable signal RXEN. Therefore, the stable data is outputted from the second latch circuit as shown by the arrow in FIG. 3 by being latched in synchronization with the enable signal RXEN. Therefore, the signal data divided into two bits in each of four frames of the received frame synchronization signal RXFS are synchronized with the received frame synchronization signal RXFS as one word of 8 bits every four frames in the second latch circuit 14. And output. The output of the second latch circuit 14 is input to a microprocessor or a central processing unit that manages data communication with a digital phone in a private exchange.

As described above, the present invention facilitates signaling because it is useful for converting incoming data separated by 2 bits and converting the data into 1 byte of information in a predetermined frame in a system that separates two bits into one frame and transmits the signal data. There is an advantage that can be analyzed.

Claims (1)

A data collector circuit of a system that separates synchronization data, signal data, and information data into a frame, and transmits and receives data, wherein the received restoration data (REDA) input to the frame is input and the receiver receives the received restoration data (REDA). A shift register 10 for shifting by a predetermined clock CLK2 input within an enable period and separating and extracting sync bit data and signal data in a frame; and inputting the extracted sync data and the receive enable signal RXEN. The first latch circuit 11 and the gate 18 for generating a reset signal for initializing data collection, and the clock CLK1 synchronized with the reception enable signal RXEN at the same period as the reception frame synchronization signal. And a counter 12 for inputting the reset signal to generate a data collecting control signal, and the shift signal by the control signal of the counter 12. A demultiplexer 13 for collecting and outputting the extracted predetermined bit signal data output from the register 10 into one byte, and a second latch for synchronizing and outputting the data collected in one byte as stable data; And a negative logic gate (19) for gating the output of said circuit (14) and said counter (12) to provide a clock for said second latch circuit (14) in a predetermined frame period.