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KR890004404A - 자기정합 금속 형성방법 및 반도체 소자 - Google Patents

자기정합 금속 형성방법 및 반도체 소자 Download PDF

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KR890004404A
KR890004404A KR1019880010808A KR880010808A KR890004404A KR 890004404 A KR890004404 A KR 890004404A KR 1019880010808 A KR1019880010808 A KR 1019880010808A KR 880010808 A KR880010808 A KR 880010808A KR 890004404 A KR890004404 A KR 890004404A
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layer
tungsten
nucleation
semiconductor device
exposed
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KR970011263B1 (ko
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메리 더블라시 자네르
짜하리아스 안토니우스 반 데르퓨터 파울루스
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이반 밀러 레르너
엔.브이.필립스 글로아이람 펜파브리켄
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/903—Catalyst aided deposition

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

요약 없음

Description

자기정합 금속 형성방법 및 반도체 소자
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도 내지 제 3 도는 본 발명의 MOS반도체 소자의 제조에 포함된 순차적 단계를 예시하는 소오스, 드레인, 게이트 및 절연 산화물 영역을 가지는 MOS소자의 실시예를 도시한 개략적인 단면도.

Claims (17)

  1. 반도체 소자의 노출된 반도체 영역에 자기정합 금속을 형성하기 위한 방법에 있어서, a) 소자 표면의 절연영역에 의하여 분리 노출된 반도체 영역상에 제 1 텅스텐층을 선택적으로 침착하는 단계와, b) 선택적으로 침착된 제 1 텅스텐층에 걸쳐 소자 표면상에 텅스텐을 위한 핵 형성 장소를 제공하는 핵형성 재료층을 침착하는 단계와, c) 절연영역의 예정된 부분을 상위하며 이들 절연영역에 인접하는 제 1 텅스텐층의 단부에 접촉하는 폐턴영역을 남겨두고 핵 형성층의 부분을 선택적으로 제거하는 단계와, d) 예정된 절연영역 양단에 금속을 상호 접속하기 위해서 핵 형성층의 잔여영역 및 제 1 텅스텐층의 노출된 부분상에 제 2 텅스텐층을 선택적으로 침착하는 단계를 구비하는 것을 특징으로 하는 자기정합 금속 형성방법.
  2. 제 1 항에 있어서, 금속 처리가 약 500℃이하의 온도에서 수행되는 것을 특징으로 하는 자기정합 금속 형성방법.
  3. 제 1 항에 있어서, 핵 형성층 패턴이 인접하는 제 1 텅스텐층의 단부에 중첩하는 것을 특징으로 하는 자기정합 금속 형성방법.
  4. 제 1 항에 있어서, 핵 형성층은 소자의 표면상에 포토 레지스터의 층을 형성하여 선택적으로 제거하며, 핵 형성층의 바람직한 패턴에 대응하는 패턴을 남겨두고 포토 레지스터의 부분을 선택적으로 제거하며, 핵 형성층의 노출된 부분을 선택적으로 에칭하며, 바람직한 핵 형성층 패턴을 남겨두고 포토 레지스터 패턴을 제거하는 것을 특징으로 하는 자기정합 금속 형성방법.
  5. 제 1 항에 있어서, 상기 핵 형성층이 비결정 실리콘인것을 특징으로 하는 장기정합 금속 형성방법.
  6. 제 1 항에 있어서, 제 1 및 제 2 텅스텐층의 두께가 적어도 100mm인 것을 특징으로 하는 자기정합 금속형성방법.
  7. 제 1 항에 있어서, 제 2 텅스텐의 선택적 침착에 따라, 얇은 절연층은 소자의 표면상에 형성되며, 적어도 하나의 접촉홀은 절연층을 통하여 개구되며, 적어도 하나의 접촉은 하위 금속에 홀을 통하여 형성되는 것을 특징으로 하는 자기정합 금속 형성방법.
  8. 제 7 항에 있어서, 얇은 절연층이 플래너화되는 것을 특징으로 하는 자기정합 금속 형성방법.
  9. 제 7항에 있어서, 상기 접촉은 알루미늄 및 알루미늄의 합금으로 선택되는 것을 특징으로 하는 자기정합 금속의 형성방법.
  10. 제 1 항에 있어서, 소자가 MOS 소자이며 노출된 반도체 영역이 적어도 소오스, 드레인 및 게이트 영역을 포함하는 것을 특징으로 하는 자기정합 금속 형성방법.
  11. 절연영역으로 분리된 노출된 반도체 영역과 소자의 노출된 반도체 영역에 자기정합 금속을 가지는 반도체 소자의 금속에 있어서, a) 노출된 반도체 영역과 접촉하는 제 1 텅스텐층과, b) 절연 영역의 예정된 부분에 상위하는 텅스텐의 선택적 침착에 대한 핵 형성장소를 제공하며 이들 절연 영역에 인접하는 제 1 텅스텐층의 단부에 접촉하는 패턴된 재료의 층과, c) 패턴된 핵 형성층 및 제 1 텅스텐층의 노출된 부분상에 절연 영역의 예정된 부분을 양단에 금속을 상호 접속하는 제 2 텅스텐층을 구비하는 것을 특징으로 하는 반도체소자.
  12. 제 11항에 있어서, 핵 형성층패턴이 인접하는 제 1 텅스텐층의 단부에 중첩하는 것을 특징으로 하는 반도체소자.
  13. 제 11항에 있어서, 핵 형성 장소를 제공하는 재료는 비결정 실리콘인 것을 특징으로 하는 반도체 소자.
  14. 제 11항에 있어서, 제 1 및 제 2 텅스텐층의 두께가 적어도 100mm인 것을 특징으로 하는 반도체 소자.
  15. 제 14항에 있어서, 제 2 텅스텐층의 두께가 적어도 120mm인 것을 특징으로 하는 반도체 소자.
  16. 제 11항에 있어서, 금속이 하위 금속과 접촉하도록 연장되는 상위 전기 접촉재료를 통하여 적어도 한 접촉홀을 규정하여 얇은 절연층으로 보호되는 것을 특징으로 하는 반도체 소자.
  17. 제 11항에 있어서, 노출된 반도체 영역이 적어도 소오스, 드레인 및 게이트 영역을 포함하는 것을 특징으로 하는 반도체 소자.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019880010808A 1987-08-27 1988-08-25 반도체 디바이스의 노출된 반도체 영역에 자기-정렬 금속화 부분을 형성하는 방법 및 반도체 디바이스 Expired - Fee Related KR970011263B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US090,301 1987-08-27
US07/090,301 US4822749A (en) 1987-08-27 1987-08-27 Self-aligned metallization for semiconductor device and process using selectively deposited tungsten

Publications (2)

Publication Number Publication Date
KR890004404A true KR890004404A (ko) 1989-04-21
KR970011263B1 KR970011263B1 (ko) 1997-07-08

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KR1019880010808A Expired - Fee Related KR970011263B1 (ko) 1987-08-27 1988-08-25 반도체 디바이스의 노출된 반도체 영역에 자기-정렬 금속화 부분을 형성하는 방법 및 반도체 디바이스

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Country Link
US (1) US4822749A (ko)
EP (1) EP0307021B1 (ko)
JP (1) JP2598481B2 (ko)
KR (1) KR970011263B1 (ko)
DE (1) DE3872803T2 (ko)

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DE3872803T2 (de) 1993-02-18
KR970011263B1 (ko) 1997-07-08
JPS6472524A (en) 1989-03-17
DE3872803D1 (de) 1992-08-20
EP0307021A1 (en) 1989-03-15
JP2598481B2 (ja) 1997-04-09
US4822749A (en) 1989-04-18
EP0307021B1 (en) 1992-07-15

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