KR840001465B1 - Video signal processing circuit - Google Patents

Abstract

A video signal processing circuit for an input video signal having a DC level, a pedestal level, and a blanking period, includes a first clamp circuit for clamping the pedestal level of the input video signal to a first predetermined DC level in response to a clamp voltage supplied from a clamp voltage source, a blanking circuit for setting the level of the input video signal to a second predetermined DC level which is higher than the pedestal level of the input video signal during the blanking period of the imput video signal and for producing a wave-formed signal, a peak-hold circuit for detecting and holding the darkest level of the wave-formed signal.

Description

Image signal processing circuit

1 is a schematic view used for explaining the case of driving a CRT.

2 and 3 are waveform diagrams used for explaining the present invention.

4 and 5 are each waveform diagram used in the schematic diagram and the operation of the embodiment of the present invention.

6 is a connection diagram of one embodiment of the present invention.

7 is a connection diagram showing another configuration of the comparison circuit in one embodiment of the present invention.

The present invention relates to a video signal processing circuit applied to, for example, a television receiver.

When the image signal is driven and supplied to the cathode of the CRT, the screen is darkest at the pedestal level V ₁ of the video signal, and the screen is brightest at the back level V ₂ of the video signal, as shown in FIG. Is chosen to lose. In this way, if the cutoff level (black level) of the CRT is equal to the pedestal level of the video signal, and the reproduction of the direct current is performed completely, the shift of the level of the setup level between stations (channels) becomes the shift of the black level as it is. Bars have the drawback that black is gray when the setup level is large. Therefore, in the actual television receiver, the DC transmission rate is set to about 0.5 to 0.5, so that the variation of the black level due to the deviation of the above-mentioned set-up level is relatively reduced. However, even in this case, there is a problem that the fluctuation of the black level cannot be completely eliminated.

The present invention detects the level at the rear side from the predetermined level as the blackest level in the video period, and regards this level as black, and sets this level as the cathode off level of the cathode ray tube, wherein the predetermined level is the video signal. By varying according to the average level of, the variation of the black level due to the deviation of the set-up level as described above is preferably prevented.

Regarding the black axis level in the video period as black detects the black axis level as indicated by the dotted lines among the video signals in one horizontal section as shown in FIG. 2A, and as shown in FIG. 2B. It means the signal processing to bring this level down to the pedestal level. However, in such signal processing, as shown in FIG. 3A, a video signal in which the average video level (hereinafter referred to as APL) is relatively high and the level variation is small is shown in FIG. 3B. Is converted to, the original signal and the luminance is very different.

Therefore, as shown in the dashed-dotted line in FIG. 3A, a predetermined level (e.g., APL is 20 [%]) is set to a value that can follow, and only the black level case is detected from this. To follow.

However, even if such consideration is taken, it is unsuitable. For example, the setup level as shown by the broken line in FIG. 3C is at an unusually high level, and the blackest level of the video signal becomes smaller than the level of the trackable value. In such a case, the whole screen is back or low contrast, and it is better to see the blackest level lowered to eliminate setup. As another example, as shown in FIG. 3d, the APL is dark gray at about 10%, and a pulsed level signal is included in an image with little change. If a part less than the value level that can be followed down to the pedestal, most of the image becomes dark black, and the bright information becomes small. Therefore, there may be anxiety for the person who sees whether the television set is malfunctioning.

In view of the foregoing, the present invention detects only a level smaller than a predetermined level and changes the predetermined level according to the average level of the video signal.

Hereinafter, an embodiment of the present invention will be described. FIG. 4 shows the basic configuration of the whole, in which the image signal from the video detection circuit is supplied to the clamp circuit 2 via the input terminal 1, and the clamp pulse from the terminal 3 is shown. This obtains the video signal S ₁ shown in FIG. 5A in which the pedestal level becomes the predetermined level V ₀ . The video signal S ₁ is supplied to the blanking circuit 4, and a section slightly wider than the horizontal blanking period is blanked by the blanking pulse P ₁ as shown in FIG. 5B from the terminal 5, so that in this section, For example, an output signal S ₂ as shown in FIG. 5C serving as a power supply potential is generated from the blanking circuit 4. This output signal S ₂ is supplied to the peak holder circuit 6 and output as the holder output S ₃ as shown in FIG. 5d corresponding to the peak level on the blackest side in the video period.

The output side of this peak holder circuit 6 is connected to the potential point (traceable value level) of (V ₀ + V _t ) via the diode 7 in the forward direction. Therefore, ignoring the forward voltage drop of the diode 7, the holder output S ₃ is the diode 7 is turned off cathode when in a lower level than (V ₀ + V _t), the holder output S ₃ is in response to the video signal On the contrary, when the holder output S ₃ is at a level higher than (V ₀ + V _t ), the diode 7 is turned on so that the holder output is at the level of (V ₀ + V _t ).

On the other hand, the video signal S ₁ from the clamp circuit 2 and the holder output S ₃ of the peak holder circuit 4 are supplied to the comparison circuit 8. The comparison circuit 8 outputs one of the signals S ₁ and S ₃ which becomes a level on the white side and generates the output signal S _{4 shown} in FIG. 5E. The output signal S ₄ of the comparison circuit 8 is supplied to the clamp circuit 19, and the clamp circuit 9 is also supplied with the clamp pulse P ₂ as shown in FIG. 5F from the terminal 10. From the output terminal 11 of the clamp circuit 9, as shown in FIG. 5G, a video signal S ₅ having a blanking period arranged at a predetermined level is generated.

The above-described trackable value level is varied in accordance with the output of the detection circuit 12. The APL detection circuit 12 detects the APL of the video signal from the terminal 13, and controls to increase the level V _t if the APL is high and to decrease the level V _t if the APL is low. . When APL of pedestal level V ⁰ is set to 0 [%], for example, when APL is as high as 80 [%] or more, V _t is about 35 [%] level level, and APL is 20 [%] or less As low as V _t , V _t becomes a level of about 10 [%], and V _t changes within a range of about 10 to 35 [%].

That is, the present invention detects the blackest level of the video signal that is behind the value level that can be followed, and as shown in FIG. 3B, damage that becomes very low compared to the original signal can be prevented. Can be. In addition, as shown in FIG. 3C, when an image close to black is blurred due to an abnormally high setup level, the level V _t is raised to delete the setup level so that the image can be easily viewed. do. Low and also the APL as shown in the 3d also, when the level of the video signal so as to correspond to the background less than the level V _t, the level V _t is lowered, and can prevent the true background black, It can be avoided that the image information is reduced. As described above, in the present invention, it is conceivable that APL becomes high when the blackest level of the video signal becomes large, or lower when the blackest level is low when APL is small. Correction is performed.

6 shows a circuit connection for realizing the configuration of FIG. A constant current source consisting of a transistor 15, an ion 16 and a resistor 17 is connected to a common connection point of the emitters of the pair of transistors shown as 14a and 14b, and a resistor (3) to the base of the transistor 15. The blanking pulse P ₁ is supplied from the terminal 5 connected via 17). Therefore, in the section where the transistor 15 is turned off by the blanking pulse P ₁ , the collector of the transistor 14b becomes approximately the power supply voltage (+ V _CC ).

The collector output of this transistor 14b is taken out through a current mirror circuit composed of a diode 18 and a PNP transistor 19.

The series circuit of the resistors 20 and 21 is inserted between the collector and the ground of the transistor 19, and the base of the NPN type transistor 22 is connected to both connection points. The emitter of this transistor 22 is grounded, its collector is connected to the base of the transistor 14b, and is connected to the connection point of the resistor 23 and the capacitor 24. The series circuit of the resistor 23 and the capacitor 24 and the transistor 22 inserted between the power supply terminal and ground constitute the peak holder circuit 6. When the base potential of the transistor 14a is higher than the base potential of the transistor 14b, no current flows in the diodes 18, 19, and 22, and the capacitor 24 supplies the power supply voltage through the resistor 23. Is charged by The time constant in this case is very large. On the other hand, when the terminal voltage of the capacitor 24 (base potential of the transistor 14b) becomes higher than the base potential of the transistor 14a, current flows in the diodes 18, 19, and 22, and the capacitor 24 Is discharged, the terminal voltage is lowered. Thus, since both base potentials of the transistors 14a and 14b are fed back to be equal to each other, the blackest level in the video period is maintained, and this holder output S ₃ is supplied to the base of the transistor 25a.

The above-mentioned connection point of the resistor 23 and the capacitor 24 is connected to the emitter of the transistor 26 through the diode 7, and the emitter of the transistor 26 has a large value for the electrostatic oil source. It is grounded via 27, and its collector is connected to a power supply terminal. The base of this transistor 26 is connected to the clamp voltage source via a resistor 28 and at the same time to the connection point of the resistors 29 and 30. The series connection of the resistors 29 and 30 is connected between the power supply terminal and the collector of the transistor 31, and the emitter of the transistor 31 is grounded through the resistor 32. By which the voltage drop across the resistor 28 is added to the clamping voltage source of V ₀ is the level of the follow-up value to the emitter (V ₀ + V _t) of the transistor 26.

The transistor 31 has its base potential varied by APL. In the configuration of FIG. 6, the APL is not detected directly, but the average value of the beam current of the cathode ray tube 33 is detected. The high voltage of the high voltage generating circuit 34 is supplied to the anode of the CRT tube 33. Reference numeral 35 denotes a feedback transformer, and a high voltage generating circuit 34 is connected to the secondary coil 36. In the resistor 37 inserted between one end of the secondary side coil 36 and ground, a voltage drop of the curve shown according to the beam current occurs. The connection point of the resistor 38 and the capacitor | condenser 39 is connected to the connection point of the secondary side coil 36 and the resistor 37, and a positive bias voltage is applied. Therefore, at the connection point of the resistor 38 and the capacitor 39, a voltage having a large or small beam current is generated and supplied to the integrating circuit 40 (shown surrounded by dotted lines) of the next stage, and the average value of the transistor It is given to the base of (31). This transistor 31 operates as a variable impedance element, and its average value is given to the base of the transistor 31. The transistor 31 operates as a variable impedance element, so that the higher the average value of the beam current, the smaller the output of the integrating circuit 40 becomes, the larger the impedance between the collector and the emitter becomes, and the resistor 29 and The potential at the connection point of (30) becomes high, and the trackable value level (V ₀ + V _t ) generated in the emitter of the transistor 26 is also changed to be high.

On the other hand, the switching level may be changed in two or more steps without changing the value level (V ₀ + V _t ) that can be continuously followed.

In addition, a transistor 25b in which the transistor 25a and the collector and the emitter are connected to each other is provided. The collector common connection point of these transistors is connected to the power supply terminal, and the emitter common connection point is grounded through the resistor 41. Is derived as the output terminal 8a. The transistors 25a and 25b constitute the comparison circuit 8, and the video signal S ₁ appearing from the clamp circuit 2 is supplied to the base of the transistor 25b. The signal having the greater level than the video signal S ₁ and the holder output S ₃ is taken out as the output signal S ₄ .

As the clamp circuit 9 connected to the output terminal 8a of the comparison circuit, a conventionally known configuration such as a feedback clamp circuit can be used. In addition, as shown in FIG. 7, an input signal is supplied to each of the anodes of the two diodes 42a and 42b, respectively, and the two cathodes are commonly connected, and this connection point is grounded through the resistor 43. In addition, a comparison circuit having a configuration derived as the output terminal 8a may be used.

As can be understood from the above description, according to the present invention, it is possible to eliminate variations in the black level due to deviation of the setup level, and at the same time, the video signal becomes very different from the original luminance, so that the background of the screen is too large. The inconvenience of darkening can be avoided.

In addition, the present invention is not limited to the television receiver as in the above-described embodiment, and can be similarly applied to the case of processing the output of the television camera. Then, the level on the black side is continuously detected from the predetermined level as the blackest level in the output signal of the television camera, and the processing can be performed to match this with the setup level.

Claims (1)

The blackest level of the input video signal during the video period is detected, and when the detected level is on the black side than the predetermined level, the video signal is changed so that the blackest level of the video signal matches the predetermined level. A video signal processing circuit comprising: an APL detection circuit (12) for varying the predetermined level by coordinating an average level of the video signal.

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