KR830001748B1 - Wireless telephone communication system - Google Patents

Abstract

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Description

Wireless telephone communication system

1 is a functional block diagram of a telephone system for wireless telephony communication of the present invention.

2 is a functional block diagram of the PCM A / D and D / A converter and multiplexer / demultiplexer unit shown in FIG.

FIG. 3 is a functional block diagram of the voice group interface shown in FIG. 2. FIG.

4 is a functional block diagram of the group multiplexer shown in FIG.

5 and 6 are functional block diagrams of the PCM message and the signal exchange part of FIG. 1 when arranged as shown in FIG.

8 is a functional block diagram of a supergroup interface shown in FIGS. 5 and 6;

9 is a functional block diagram of the slot exchanger shown in FIGS. 5 and 6;

FIG. 10 is a functional block diagram of a signal bit transceiver shown in FIGS. 5 and 6;

FIG. 11 is a functional block diagram of the switch computer interface shown in FIG. 6. FIG.

12 is a functional block diagram of the exchange control unit shown in FIG.

The present invention relates to an apparatus of a telephone system for wireless telephony communication, and more particularly to an improved telephone system for wireless telephony communication using PCM technology.

Conventional telephone systems for wireless telephony have one basic station that covers a large service area, such as the entire city, which in turn is connected to the telephone central station. Typically, a base station has a number of complex radio channels for providing wireless telephone service of a relatively limited number of mobile wireless telephones in a densely populated city. Therefore, in order to neutralize much of the wireless telephone service, there was no choice but to increase more wireless channels in the existing wireless telephone system. However, the number of radio channels used in such radiotelephone systems is limited by administrative legislation and may interfere with other radio channels. As a result, more mobile wireless phones need to be added to the existing system, which creates a strain on the system's limited wireless channel.

Problems with conventional telephone systems have enabled some of the improved wireless telephone systems by establishing many basic stations on the territories. Since the output of the base stations is relatively small, the channel assigned to the first base station can be reused in a second base station far from the first base station without any radio frequency interference. By reusing wireless channels in large areas, a large number of mobile phones can be accommodated in the wireless telephone system.

However, in order to control the operation of such a radiotelephone system, a more complex switching network capable of controlling a large number of remote base stations and a large number of mobile radiotelephones, including vehicles or cellular telephones, is required. . Moreover, the switching network should be designed to allow mobile wireless telephones to receive all telephone services currently received by landline telephone systems. For example, such telephony services are repertory dialing, auto-call transfers, and auto-conference calls. This feature was absent in traditional wireless telephone systems. Thus, conventional radiotelephone systems have not been able to accommodate a relatively large number of mobile radiotelephones, and have been unable to provide mobile radiotelephones with the aforementioned or equivalent automatic telephone service.

Due to the above-mentioned shortcomings and problems, there is a need for an improved telephone system for wireless telephony that can control a large number of base stations and mobile wireless telephones and provide various services to mobile wireless telephones.

Accordingly, it is a general object of the present invention to provide an improved method and apparatus for a wireless telephone system that can provide a mobile wireless telephone with all practical services found in existing landline telephone systems.

It is another object of the present invention to provide an improved telephone system for wireless telephone communication using stored program control techniques for providing automatic telephone service to mobile wireless telephones.

Another object of the present invention is to provide an improved telephone system for wireless telephony communication that can accommodate various wireless signaling methods.

It is another object of the present invention to provide an improved telephone system for wireless telephony communication using PCM digital switching technology between serial PCM bit streams (for switching).

Another object of the present invention is to provide an improved telephone system for wireless telephony of a highly reliable and complete non-blocking system.

It is another object of the present invention to provide an improved telephone system for wireless telephony communications that can process PCM supervised signals at an exchange.

Another object of the present invention is to provide an improved telephone system for radiotelephone communication in which the telephone system can be extended to basic units to accommodate the increase.

According to the present invention, the above-mentioned problems and disadvantages of the prior art are eliminated, and the various objects described above are provided with a mobile wireless telephone system connected to a wired switched network for providing a communication path between mobile wireless telephones and between mobile wireless telephones and landline telephones. This is accomplished by an improved telephony system for wireless telephony communications, including a wireline telephone system having a wireline switching network for providing communication paths to a number of wireline telephone systems.

Mobile telephone systems include a number of base stations, digital switching networks, and PCM analog / digital (A / D) converters and digital / analog (D / A) converters. Each base station establishes a communication channel for mobile telephones in its area.

Digital switching networks provide for the exchange between predetermined pairs of input and output serial PCM bitstreams. I / O serial PCM bitstreams are time-division (TDM) bit streams, each bitstream having a number of frames with a predetermined number of channels (e.g. 24 channels), each channel having its own message and signal bits have. A fixed number of PCM channels are repeated for each successive frame. A fixed number of consecutive frames, for example 12 frames, consists of multiple frames.

The PCM A / D converter and the D / A converter are installed between the digital switching network and the corresponding base station, the digital switching network and the wired switching network. PCM and A / D D / A converters have analog ports coupled to the base station and wired switch network. Each analog port corresponds to a preset input / output PCM channel. PCM A / D and D / A converters interface input and output serial PCM bit streams from digital switching networks.

Digital switching networks include multiplexers, time-slot exchangers (TSIs), and demultiplexers. The set number of incoming serial bit streams is multiplexed by the multiplexer to provide an input parallel bit stream similar to the TDM bit stream. The input parallel bit stream has a time slot corresponding to each PCM channel in a predetermined number of input serial PCM bit streams. The input PCM channels in the input parallel bit stream are exchanged by TSI according to the order of time-sluts stored in the routing memory to provide the output parallel bit stream. The output history bit stream is demultiplexed by a demultiplexer to provide a predetermined number of output serial PCM bit streams.

Digital switching networks have important signal processing capabilities to centralize the supervisory signal bits contained in the input and output serial PCM bit streams. The signal detector senses the input signal bits from the input serial bit stream of each input PCM channel. The signal processor couples the input PCM channel to the selected output PCM channel in response to the sensed input signal bits that determine the order of the time slots in the routing memory. The TSI joins the input PCM channel to the selected corresponding output PCM channel according to the order of time-sluts in the routing memory. The signal processor responds to the sensed input signal bits applied to the preset format recognized by the output PCM channel. The output signal bits are applied to the output parallel bit stream, which is limited to the demultiplexer.

According to another feature of the invention, the function of the signal processor is supplied by a computer having a stored program. The use of stored programs gives more flexibility, allowing signal processors to have different PCM formats (e.g. 24 or 30 PCM channels) in each serial PCM bit stream, as well as multiple formats on separate PCM channels. Makes it easier to deal with the supervisory signal supply sequence.

According to another aspect of the present invention, there is provided a method for processing signals over a digital switching network having a time-slot exchanger for converting an input PCM channel into an output serial bit stream according to the order of time-sluts in the routing memory. There is an improved way. This method is an improvement for processing the signal bits from the serial PCM bit stream and is performed in the following order.

Detects input signal bits from an input serial PCM bit stream representing each input PCM channel,

Ordering of time-sluts in routing memory in response to input signal bits,

The ordering of the time slots in the routing memory to send the input PCM channel to the selected output PCM channel is applied to the time slot exchanger, corresponding to the input signal bits, and recognized by the output PCM channel. This step produces an output signal bit that fits perfectly.

Additional features, objects, and advantages of the telephone system for wireless telephone communication according to the present invention will be more clearly understood from the following detailed description with reference to the drawings.

Description Overview

I. System description (Figure 1)

A. Outline

B. System Structure Description

II. Digital Switching Network (Figures 2 and 5-7)

III. Signal processing section (FIGS. 1 and 2)

* * *

I. System description (Figure 1)

A. Outline

The telephone system for wireless telephone communication according to the present invention shown in FIG. 1 includes a landline telephone system 20 for providing a communication path to a plurality of landline telephones, and between a mobile or simple portable wireless telephone and landline telephones. Mobile radiotelephone systems 30, 40, 50, and 60 coupled to a landline telephone system for providing a communication path. The mobile radiotelephone system is composed of various methods for providing necessary mobile radiotelephone services to a metropolitan area including a large number of neighboring cities or suburbs. Similarly, a mobile radiotelephone system may be configured to enable communication covering a large number of relatively large distances or large areas of the state. In addition, a mobile radiotelephone system capable of dividing a specific area into cells and organizing in a cell structure is described in US Patent No. 3,906,166, issued September 16, 1975 and named "Wireless Telephone System" by Martin Cooper et al. The present invention can be usefully applied to any wireless telephone system described, and can be applied to any telephone system without departing from the spirit and background of the present invention.

The mobile radiotelephone system according to the present invention includes a plurality of basic stations 60, a digital switching network 40, a PCM A / D and D / A converter 30, and a signal processor 50.

Each of the base stations 60 provides a communication path to the mobile radiotelephone within the area they can cover. The base station 60 may be located far from the digital switch 40 to meet the geographic needs of a particular telephone system. The digital switch 40 may be centrally located with the signal processor 50 and, for example, in a convenient location close to the wireline telephone system 20. The PCM A / D D / A and the converter 30 lie between the digital switch 40 and each basic station 60, and between the digital switch 40 and the wireline telephone system 20. The analog ports of the PCM A / D and D / A converters 30 are coupled to the base station 60 and the wireline telephone system 20, respectively, and input and output analog signals or voice information and supervisory signals respectively. It converts into a PCM bit stream signal. The PCM A / D and D / A converters 30 may be centrally located with the digital switching network 40 or may be located away from the base station 60 or the landline system 20.

Input / output serial PCM bit streams from the PCM A / D and D / A converters 30 are fed to the digital switching network 40. Each serial PCM bit stream consists of a number of frames consisting of many predetermined PCM channels having message bits and signal bits. The message bit corresponds to analog or voice information for the analog port, and the signal bit corresponds to the signal that oversees the analog port. The serial bit stream consists of two major international formats, as recommended by the International Telegraph and Telephone Advisory Committee (CCITT).

These formats are generally considered to be 24-channel North American formats (hereafter referred to as "T1 formats") and 32-channel European formats (hereinafter referred to as "Europe formats"). CCITT sets out the specifications of these two formats under Chapter 3, Chapter 7 of the Green Book, under the term “digital transmission system,” where the 24-channel format is in Q.47 and the 32-channel format. Is described in Q.46.

According to these two PCM specifications, analog ports are sampled at 8KHZ rates and digitalized into 8-bit words. Each analog (port is associated with a preset input / output PCM and channel. An 8-bit word or mage bit for the analog port is sent as a serial PCM bit stream to the corresponding PCM channel for each analog port. A stream consists of 24 or 32 contiguous frames, and a contiguous frame group consists of multiple frames, consisting of 12 frames in the T1 format and 16 frames in the European format, forming one multiple frame.

The digital switching network 40 of the present invention provides a non-blocking digital switching network for PCM channel switching between input and output serial PCM bit streams. The digital switching network is configured to handle a predetermined number of input and output serial PCM bit streams, for example 64 input and 64 output serial bit streams from the corresponding number of PCM A / D and D / A converters 30. have. For example, a serial PCM bit stream group comprising 16 serial PCM bit streams is time-divided (TDM) to provide a parallel bit stream with a predetermined time-slot for each PCM channel from the serial PCM bitstream group. The output parallel bit stream is interconverted by the digital switching network 40 according to the order of time slots in the routing memory to produce the output parallel bit stream.

The signal processor 50 of the present invention is provided for the central processing of the supervisory signal performed in the serial PCM bit stream. The input supervisory signal for each input PCM channel is sensed by the signal processor 50 and used to prepare the time-slot order and output supervisory signal for the digital switching network 40. All supervisory signals from the base station 60 and the wireline telephone system 20 can be transmitted in the serial PCM bit stream.

B. System Structure

One embodiment of a telephone system for wireless telephony communication constructed in accordance with the present invention is shown in FIG. The wireline telephone system 20 has a wired switching network, which may be a central station 21 having an analog trunk circuit or a central station 22 having a digital PCM trunk circuit. The mobile radiotelephone system has a PCM A / D and D / A converter 30, an exchange control unit 40, a signal processing unit 50, and a plurality of basic stations 60. Mobile radiotelephone systems may also be connected to geographically distant mobile radiotelephone systems located in remote areas such as neighboring states or other countries.

The telephone system for radiotelephone communication shown in FIG. 1 is particularly suitable for application to cellular radiotelephone systems such as those described in U.S. Patent No. 3,906,166 described above. Base station 60 may be geographically located within a particular cellular tissue. The base station 60 includes a plurality of radio channels, a voice control unit 63, a radio interface 62 and a radio base station 64 that can operate in conjunction with the base station controller 61. The base station controller 61 controls the operation of the wireless base station 64 so that a particular mobile signal format is used for communication with mobile radio telephones. The base station controller 61 typically includes a computer system to give functions necessary for the operation of the wireless base station 64. The necessary control signal from the base station controller 61 is applied to the voice control unit 63 and transmitted to the wireless base station 64 via the air interface 62. The audio transmitter or receiver from the wireless base station 64 is suitably regulated by the voice control section 63 and applied to the PCM A / D and D / A converters 30 directly or via a wired network. The PCM A / D and D / A converters 30 are located between the digital switching network 40 and the landline system 20 and the base station 60. The PCM A / D and D / A converters 30 allow conversion of analog information or supervisory signals for analog ports on outgoing and incoming serial PCM bit streams. The T1 format was applied to the embodiment of the PCM A / D and D / A converter 30. The PCM A / D and D / A converter 30 includes a plurality of voice group units 31 and 32. The voice group units 31 and 32 are used to receive 24 analog ports and a pair of input / output serial PCM bit streams. Voice group units 31 and 32 operate the "T324 PCM transport system" of No. 650038-823-001, issued in 1976 by the Transmission Department of Int'l Telephone & Tele-communication. The unit can be easily purchased commercially as described in the installation and maintenance manual.

The voice group sections 31 and 32 are commonly referred to in this field as "PCM channel banks".

Digital central station 22 is connected to digital switching network 40 by a digital PCM trunk having a pair of input and output serial PCM signals, commonly referred to as " " " T1 span lines. &Quot; By providing one global digital link equal to the 24 analog ports in), the required connections between the line and the device are greatly reduced.

Digital switching network 40 interfaces with PCM A / D and D / A converters only by a pair of input and output serial PCM bit streams. In addition, since the supervisory signal for the analog port is carried in the input / output serial PCM bit stream, an additional interface between the PCM A / D and D / A converter 30 and the digital switching network 40 is not required. The digital switching network 40 may be centrally located together with the signal processing unit 50, and may be connected to the PCM A / D and D / A converters 30 located remotely by T1 lines in the wireline network.

The digital switching network 40 includes a multiplexer / demultiplexer section 41 and a PCM message and synch exchange section 42. The pair of input / output PCM bit streams is called a "T1" bit stream. The multiplexer / demultiplexer section 41 controls a multiplex and demultiplex operation of receiving 64 T1 bit streams, T1 bit streams of a predetermined number, for example in the present invention, and converting serial bit streams into parallel bit streams. .

The PCM message and signal exchanger 42 receives the input parallel bit stream and exchanges the input PCM channels in the input parallel bit stream by the order of time-slots assigned to the routing memory to produce an output history bit stream.

The signal processing unit 50 includes an exchange control unit 58, a call processing computer 51, an organization structure computer 53, a data collection system (DAS), a database computer 52, and computer peripherals 54-57. have. Each of the blocks 51, 52, 53, and 58 of the signal processing unit 50 is controlled by a computer that stores a program that gives the function of each block. The computer may be a commercial computer or may be a microcomputer system such as Motorola's M6800. The supervisory signals from all analogue stages of the telephone system are monitored by the switching control unit 58 and sent to the call processing computer 51. For example, the supervisory state indicated by the supervisory signal indicates on-h00k and off-hook states, dialing, call clearing states, alarm states and other telephone system events.

The supervisory state of the analog ports associated with the telephone system is determined by the switching control unit 58, which senses the input signal bits corresponding to the input PCM channel of the input serial PCM bit stream. The logic state of the input signal bits corresponding to each PCM channel provides on-hook, off-hook, dialing and other supervision information. This supervised state is determined from the input signal bits and is transferred to the call processing computer 51 for subsequent processing. The call processing computer 51 receives the dialing and other information necessary to make a special call and confirm it via the DAS and database computer 52. Information maintained in the DAS and database computer 52 includes mobile and mobile station subscriber number files, telephone system dialing plans, telephone system group plans, operating parameters of the mobile telephone network such as the number of base stations, and the like.

In order to control the mobile telephone network of highly complex cellular tissues, tissue structure computer 53 needs a direct data link to each base station controller 61. This data link is connected to the voice group unit 32 via a modem link or a digital port. The digital port for the voice group unit 32 is adapted to occupy a position corresponding to one analog port and provides a data channel of 64,000 bits / sec or more.

Organization structure computer 53 supervises the establishment of a communication path between base station 60 and mobile radio telephones. Thus, call processing is performed by the call processing computer 51 and the organization structure computer 53. For example, after checking the dialed number received at the port connected to the telephone system and the port connected to the wireless channel of the base station, the call processing computer 51 calls the telephone to complete the call. Send a system port to a wireless channel port. The assigned wireless channel port is sent from the call processing computer 51 to the switching control unit 58, which arranges the channel time-sult to the routing memory to complete the connection. Time-slot ordering in the routing memory allows the TSI to connect the input PCM channel for the telephone system port to the output PCM channel for the wireless channel port, and to the output PCM channel for the phone system port. do. Next, the output signal bits corresponding to the format of the radio channel port are transmitted by the switching controller to the output PCM channel for the radio channel port. For example, dial numbers that are entered after the end of a number are truncated accordingly. This is because the number verification of the mobile radio telephone does not require all digits.

Thus, in order to establish a bidirectional connection between the two analog ports, the exchange control 58 must provide two designated time slots in the routing memory. Only a one-way connection is sufficient to provide the supervision tone to an analog port such as a dial tone. The output PCM channel to the analog port is combined with the input PCM channel for the dial tone. To complete the unidirectional connection, the exchange control needs to install one time slot in the routing memory.

II. Digital Switching Network (Figures 2 and 5-7)

The functional organization of the digital switching network is shown in more detail in the PCM messages and signal exchanges shown in Figures 5 and 6 in accordance with Figure 7 in accordance with the functional block diagram of the multiplexer / demultiplexer shown in FIG. A preferred embodiment of the digital switching network is based on the T1 format.

Each pair of input and output serial PCM bit streams or T1 bit streams are clock synchronized to the digital switching network. According to the T1 format, the T1 bit stream is transmitted at a frequency of 1,544 MHz. In the implementation example of the digital switching network of the present invention, each block consists of four blocks receiving 16T1 bit streams. Therefore, the digital switching network has 4 blocks of 384 channels, so it eventually has 1536 PCM channels.

A fixed input / output PCM channel is assigned to each port of the PCM A / D and D / A converters. For each 125 μsec PCM frame, there is one block with a total of 386 channel time slots numbered from 1 to 386 in order, of which 384 are used for the actual PCM channel and the remaining time slots relate to the frame bits of the T1 bit stream. It is not actually used. Thus, the PCM A / D and D / A converters only concern 384 time-slots in one block of the digital switching network. For example, time-slot number 185 of block number 1 is associated with a particular analog port. The input message bits for the input PCM channel at a particular analog port are in time-slot number 185 in the input parallel bit stream of block 1 and the output message bits for the output PCM channel corresponding to the particular analog port are block 1 Is in time-slot number 185 in the output parallel bit stream.

The T1 bit stream is combined with the multiplexer / demultiplexer unit (see FIG. 1) of the digital switching network 40. The multiplexer / demultiplexer unit 41 is divided into four blocks, each of which interfaces with 16 T1 bit streams. It is. The PCM message and signal exchange section 42 is also essentially divided into four blocks, each of which is coupled to a block corresponding to the multiplexer / demultiplexer unit 41. The PCM message and signal exchange section 42 There is an extra block, which can be exchanged for any of the other four blocks that are there, and if one of the four basic blocks malfunctions, the PCM message and signal exchange section 42 The extra blocks are automatically replaced Each block in the PCM message and signal exchange 42 receives all incoming PCM channels from 64 T1 bitstreams Each block in the PCM message and signal exchange 42 The block receives all input PCM channels, and the digital switching network is sufficiently noble because it can transmit the output PCM channels corresponding to the 16 T1 lines of any particular block. A king.

A. Multiplexer / Demultiplexer Unit (Figure 2)

In FIG. 2, a block diagram of the PCM group portion 260 and the multiplexer / demultiplexer portion 250 is shown. The multiplexer / demultiplexer unit 250 includes a group multiplexer A 200, a group multiplexer B 201, and 16 or more group interfaces 202-206. Each block of the multiplexer / demultiplexer unit 250 may control a super group or 16 T1 lines. Two group multiplexers 200 and 201 were installed to enhance the reliability of the telephone system. if. If any one of the group multiplexers 200 and 201 malfunctions, it is automatically replaced with the other. Each group multiplexer 200 and 201 provides the same parallel output bit stream coupled to the message and signal exchange.

The group interfaces 202-206 are interfaced with bit streams from the corresponding units 207-211, respectively, to separate shared buses coupled to the group multiplexers 200 and 201. Each group interface 202-206 multiplexes or demultiplexes the PCM channels into and out of the shared bus according to the composite signal from the multiplexers 200 and 201 of each group. Each group interface 202-206 has a time period for positioning and a time period for receiving parallel PCM bitstreams input and output from a shared bus coupled to the group multiplexers 200 and 261, respectively. Each group multiplexer 200 and 201 operate in synchronization with each other. Group multiplexer A 200 is a main unit that is incorporated into a block in the PCM message and signal exchange. In addition, the group multiplexer B 201 is a subordinate unit that is combined with the auxiliary block of the PCM message and the synch exchange unit.

Two group interfaces 202 and 203 interface with a serial T1 bit stream, and the other three group interfaces 204-206 interface with a parallel PCM bit stream. The voice group interface 202 is incorporated into the voice group unit 207, which operates, installs, and maintains the " T324 PCM carrier system " of 650033-823-001 issued in 1976 by the International Telegraph & Telephony Radio Transmission. It is the same number as a commercially available PCM journal bank, such as the transfer unit described in the manual. The voice group unit 207 is provided for conversion between 24 analog ports and the corresponding serial T1 bitstream.

The line interface 203 is fitted to the line portion 208, which is the same as the number of commercial T1 line terminals. Strand portion 208 is connected to digital central station 22 (FIG. 1) either directly or through a continuous T1 line repeater.

The retaining interface 204 is incorporated into the retaining portion 209, which is an auxiliary for checking the digital switching network. The maintenance interface 204 provides a 9 bit input parallel bitstream comprising parity bits of 8 messages and receives a 9 bit output parallel PCM bit stream. The party call interface 205 and the tone signal interface 206 exchange similar parallel PCM bit streams. The party call interface 205 is associated with a party caller 201 that provides a party or conference call between three parties. The party caller 210 provides an input PCM channel that is associated with the output PCM channel in accordance with any number of traditional methods to indicate a suitable combination of output PCM channels. The tone signal interface 206 is incorporated with the tone signal section 211, which is a digital tone detection circuit for sensing input signals in various formats already in frequency, and for output signals and telephone systems at various frequencies. It includes a digital tone generating circuit for generating various voice signals or progressing tones such as dial tone, busy tone, and the like.

1. Voice Group Interface (Figure 3)

The operation of the voice group interface shown in FIG. 3 is represented by the general principle of the operation performed by the various group interfaces included in the multiplexer / demultiplexer unit. The voice group interface receives the serial T1 bit stream and provides a parallel bit stream to and from the group multiplexer. The serial T1 bitstream from the voice group section is clock synchronized with the digital switch network by configuring a voice group beacon operated by a clock signal reproduced from the output serial PCM bitstream from the digital switch network. Operation by the reproduced clock is generally available in commercial voice group units similar to the T 234 carrier system described above.

The functional block diagrams shown in FIG. 3 and the functional block diagrams of FIGS. 4, 8, 9, 10, and 11 are shown by function as typical logic blocks and circuits. A master in this field was informed of the integrated circuits described in the "TTL databook" issued by Texas Instruments in 1976, and the conventional design in Dieter Meyer's book "Logical Design of Digital Systems" published by Bacon in 1971. In-design technology can be used to create a logic circuit of functional blocks.

The input serial PCM bitstream from the voice group section is applied to the bipolar / unipolar converter 301, which is uni- directional to the receive clock phase selector 302, shift register 303, multiple frame and frame synchronization logic 307. Provides polar logic output. The message bits for each successive PCM channel of the input serial PCM bitstream are continuously clocked to the shift register 302 by the control of the receive clock phase selector 301. The receive clock phase selector 302 provides a clock call that accommodates the set sum of the clocks in the input serial PCM bit stream.

Multiple frame and frame synchronous logic 307 detects the frame bits in the input serial PCM bit stream to establish the beginning of each frame and multiple frames. The alarm detector 310 checks the digital pattern of the detected frame bits in the actual existence of the bit order suitable for the T1 format. The alarm detector 310 also receives from the shift register 303 the second higher bit of the PCM message bits, indicating that there is an alarm from the voice group unit if it is logical 0 for the entire frame. If no proper bit order is detected or an alarm is detected from the voice group portion, the alarm detector 310 causes the alarm indicator 311 to operate to group the tri-state drivers 314 and 318. Instruct the alarm.

Once the input frame and multiple frames are synchronized, the message bits for each PCM channel entering serially in the shift register 303 are sequentially sent in parallel to the PCM first-in and first-out memory 305. . The PCM FIFO memory 305 is provided to store 24 PCM channels each of nine message bite earthquakes each including at least one frame or one parity bite. Any general FIFO memory with at least 9 bits x 24 words is enough, but the usefulness and limitations of traditional FIFO memory require different memories. The PCM FIFO memory 305 stores message bits of consecutive PCM channels starting from a frame with nine message bits of the first channel. Therefore, when the PCM FIFO memory 305 is first read out, the first PCM channel of the frame is accessed. Since the frame order of the digital switching network is not synchronized with the frame order of the input serial PCM bitstream, the PCM FIFO memory 305 is configured to store at least 24 channels of message bits in the frame. This is because each frame order may not be synchronized by the entire frame. The input PCM channel is read from the PCM FIFO memory 305 and applied to the drivers 313 and 317 under the control of the time-slot and the system frame order of the frame counter 309.

The parity generator 306 generates parity bits from the eight message bits of each PCM channel stored in the PCM FIFO memory 305 together with the message bits. Parity is maintained as message bits for each PCM channel through the entire digital switching network.

According to the T1 format, signal bits for each channel are included in the sixth and twelfth frames of each multiple frame. The lowest bit of the eight message bits of each PCM channel in each of these frames is the signal bit. During each of these frames of the input PCM bit stream, the signal bits of each channel are stored in signal bit FIFO memory 304. The signal bit FIFO memory 304 stores at least 48 signal bits for one multiple frame. The signal bits are stored in the signal bit FIFO memory 304 in the order in which they are received in the input string PCM bit stream. The signal bits 304 are sequentially read from the Cynbit FIFO memory 304 in accordance with frames 6 and 12 from the time-slot and frame counter 309. Therefore, the input signal bits are read from the signal bit memory 304 and applied to the drivers 312 and 316 according to the multiple frame order of the digital switching network.

The control line A provided by the group multiplexer A operates the tree-state driver 312-315, so that each input to the shared bus at the appropriate time slot for multiplexing the input signals of each PCM channel to the group multiplexer A is provided. Gate out the signal. Similarly, control line B provided by the group multiplexer B is provided to the tree-state multipler 316-319, so that a shared bus is provided at each time slot for multiplexing the input signals of each PCM channel to the group multiplexer B. Rho gates the input signal.

The clock and reference receiver 308 selects the clock and reference B in response to a clock control signal from the primary group multiplexer (see Chapter II A, 2). The selected clock and reference signal are applied to several blocks of the voice group interface. The time-slot and frame counter 309 supplies time and control signals that are synchronized with the frame order of the digital switching network by the received reference signals. The time-slot and frame counter 309 is preset using the reference signal to keep the system multi-frame order in a predetermined state.

The multiplexer and latch 321 latch the major bits of each output PCM channel from the group multiplexer A or the group multiplexer B through the shared bus by an instruction of a control signal of the group multiplexer. The latched mage bit of each output PCM channel is applied to the shift register 322 and again to the parity checker 320. If the parity bits from multiplexer and latch 321 do not match the generated parity bits, parity checker 320 applies a GI parity alert signal to drivers 315 and 319.

The mage bits stored in the shifter register 322 are continuously shifted out to the unipolar / bipolar converter 323. Frame bits are added to the shift register 322 by the multiframe sync pattern generator 324. According to the T1 format, a frame bit is added to each frame in a predetermined bit order for defining multiple frames. The unipolar / bipolar / converter 323 converts the serial bit stream from the shift register 322 into a bipolar serial PCM bit stream and applies it to the equalizing circuit 325. The equalizing circuit 325 provides impedance matching of the line on which the output serial PCM bit stream is transmitted.

2. Group Multiplexer (FIG. 4)

The group multiplexer (GM) controls the parallel PCM bits on the I / O shared PCM bus to be multiplexed into the group interface, and also supplies input / output PCM bitstreams to the PCM mage and signal exchange and buffers multiple alarm signals. Two identical-group multiplexers A and B are used to obtain a high reliability digital switching network.

These two group multiplexers continue to operate.

Group Multiplexer A (GM-A) Main unit connected to the dedicated Super Group interface of the PCM Mage and Signal Exchange.

The group multiplexer B (GM-B) unit is limited to a shared bus connected to the auxiliary supergroup interface of the PCM mage and signal exchange.

Referring to FIG. 4, the system clock and reference signals are received by differential receivers 415 and 416 to be coupled to the various blocks and group interfaces of the group multiplexer. Time-slot and frame counter 418 supplies the necessary timing for decoder 417.

Decoder 417 supplies 20 control lines to various group interfaces (up to 16) to control the multiplexing of the magebits to or from the shared input bus. A GM-A / B select line received by differential receiver 420 is provided to the group interface along with 20 control lines of decoder 417 to select output shared PCM buses from group multiplexers A and B. The clock and reference alarm detector 419 monitors the clock and reference signals received by the differential receivers 415 and 416 and switches the clock and reference signals received by its multiplexer in response to the detected malfunction. An output control line is supplied to operate the multiplexer 421.

Shared input PCM buses and group alarms from the 16 group interfaces are applied to an OR gate (nine separate OR gates) 401 whose output leads to a latch 402. If the alarm is a logic " 1 ", the output of the OR gate 401 becomes a logic '0' by the data of the corresponding input channel. If the major bits for the PCM channel are all logic '0', then a very low level signal, commonly referred to as a "quiet tone", is generated. The alert drawn by the four-stage register 403 is delayed by four time slots, which is applied to the OR gate 414 to make a logic '1' on the corresponding output PCM channel in the shared output PCM bus.

The latch 402 receives the mage bits in parallel with the signal bits, group alert and group interface parity alert for each PCM channel.

Therefore, during each time slot, the data in latch 402 represents the state of the various signals for that PCM channel. Parity checker and generator 404 generates parity bits for the major bits of each input PCM channel and applies the generated parity bits to differential driver 407. The generated parity bit is compared with the parity bit received from the group interface, and if it does not match, the GM parity alert signal is applied to the differential driver 409. The output of latch 402 is applied to differential drivers 405, 406, 407, and 408 to send respective signals to the PCM image and signal exchange.

The output parallel bit stream or highway of the PCM image and signal exchange is applied to the differential driver 410 and its output is applied to the latch 410. The output of the latch 402 for each PCM channel is applied to the OR gate 414 so that its output includes the output of the OR gate 414 to provide a shared output PCM bus to the various group interfaces to collect the parity bits. It is limited to the parity checker and generator 413 that generate. Similarly, if the generated parity is different from the received parity bit, the corresponding GM parity alert signal is supplied to the differential driver 411.

B. PCM Mage and Signal Exchange (Figures 5-7)

The PCM message and signal exchange unit is divided into four blocks and one auxiliary block, and each block can control 384 PCM channels or one supergroup. Referring to FIGS. 5 and 6 arranged according to FIG. 7, each block of the PCM mage and signal exchange unit includes a supergroup interface (SGI) 501-505, a time-slot exchanger (TSI) and a signal bit transceiver ( 506-510) (SBS / R).

Control of the various blocks is performed by the switch computer interface A) SCI-A) 516 and the switch computer interface B (SGI_B) 517. Super group interfaces 501-504 are coupled to dedicated group multiplexer A for receiving incoming and outgoing parallel PCM bit streams. Auxiliary super group interface 505 is coupled to four group multiplexers B to receive input / output shared parallel PCM bitstreams.

The mage bits of the input parallel PCM bitstream are connected to the super group interface 501-505 and run to each time-slot exchanger 506-510. Thus, each time-slot exchanger 506-510 can be contacted with the entire super group interface 501-505, including the auxiliary super group interface 505. Time-slot exchangers 506-510 store input major bits for each PCM channel in the information memory at the location where the time slot of each PCM channel is addressed. Stored message bits read the information memory and send it to the output parallel PCM bitstream addressed by the order of time slots in the routing memory. The parity bits and signal bits of the output parallel PCM bitstream coming from the time-slot switch 506-509 are applied to the corresponding signal bit transceivers 511-514 and the auxiliary signal bit transceiver 515.

In addition to the parity bits and the signal bits supplied by the signal bits transceivers 511-514, the remainder of the message bits (7 bits) for the output history bit stream are applied to the corresponding supergroup interface 506-509 to provide a particular channel. The selected mage bit for the PCM is returned and applied to the corresponding supergroup interface 501-505 with the output parallel PCM bit stream. The secondary supergroup interface 505 receives the output parallel bit streams of the mode time-slot exchangers 506-510 and the signal bit transceivers 511-515.

Auxiliary time-slot exchanger 510 transmits a 7-bit major signal and a precious control signal from the auxiliary signal bit transceiver to all the supergroup interfaces 501-505 together with the signal bits and the parity bits.

The signal bit transceivers 511-514 receive an input signal bit bus from the corresponding supergroup interface 501-504. In addition, the signal bit transceivers 511-515 receive the corresponding signal from the auxiliary supergroup interface 505. In addition, the auxiliary signal bit transceiver 515 receives the corresponding signal from all the supergroup interface (501-505).

The PCM Mage and Signal Switch may be automatically replaced by any Auxiliary Unit, Auxiliary Supergroup Interface 505, Auxiliary Time-Slot Switch 510, Auxiliary Signal Bit Transceiver 515 in place of the malfunctioning unit. For example, the supergroup interface 505 is replaced by the supergroup interface 504, the auxiliary time-slot exchanger 510 is a time-slot exchanger 507, and the signal bit transceiver 515 is a signal bit transceiver. 513 may be replaced. The insertion of an auxiliary unit makes the digital exchange network more useful. With the replacement of a suitable auxiliary unit, a malfunction of any one unit does not worsen the operation of the digital switching network.

Supergroup Interface (Figure 8)

The supergroup interface (SGI) buffers an input / output parallel bit stream between the group multiplexer, corresponding time-slot exchangers, and signal bit transceivers. In Figure 8, the output PCM bitstream and loop feedback control signals from TSI and SBS / R are multiplexed under the control of a select decoder 611 which controls multiplexer 609 of latch 602, parity checker and generator 604. Gated by 601. The selection decoder 611 decodes the selection line from the switch computer interface representing the structure of the PCM message and signal exchange.

The mage bit of each PCM channel and the parity bit generated from the parity checker and generator 604 are applied to the latch 602.

The output of the latch 602 is applied to the differential driver 603 to be sent to the corresponding group multiplexer in the output parallel PCM bit stream. If the parity bit generated by the parity checker and generator 604 is sent to the multiplexer 601 If the parity bit does not match, the corresponding SGI parity alarm signal is generated.

The input parallel PCM bitstream and the group alert bus and signal bit bus from the corresponding group multiplexer are received by the differential receiver 606 and applied to the latch 607. The message bits from latch 607 are applied to multiplexer 609 and parity checker and generator 608. The parity bits generated by the parity checker and generator 608 are applied to the multiplexer 609 and compared with the input parity bits of the latch 607. If the generated parity bit and the parity bit of the latch 607 do not match, the parity checker and generator 608 generates a corresponding SGI parity alert signal.

The multiplexer 609 typically sends input message bits from the latch 607 and the generated parity bit driver 610. However, by controlling the loop feedback control bit 605, the multiplexer 609 selectively gates nine bits of the multiplexer 601 to the driver 610.

This operation of the multiplexer 609 causes the output of the particular time-slot exchange and signal bit transceiver to return message bits to the input of the particular time-slot exchange. During each time slot, if the feedback control bit of the output PCM channel is logical '1', the message bit of the output PCM channel is returned instead of the message bit of the input PCM channel of the same time slot. The feedback control bits are stored in the TSI's routing memory with the time slots specified for each output PCM channel. Its feedback feature enables b-testing of unused PCM channels in the digital switching network. The signal bits and group alarm bits of latch 607 are applied directly to driver 610.

The parallel PCM bus of the driver 610 is applied to the entire time-slot exchanger, and the signal bit bus and group alarm bus at the driver 610 are applied to the corresponding signal bit transceiver and the auxiliary signal bit transceiver.

2. Time-Slut Exchanger (Figure 9)

The time-slot exchange (TSI) stores the message bits of the PCM channel from the input parallel PCM bit streams of all four supergroup interfaces. The secondary supergroup interface may be replaced with one of any supergroup interface in response to a malfunction. The message bits of the PCM channel are stored in the alarm memory addressed by the corresponding time slot for the PCM channel. The message bits for the PCM channel read the output parallel PCM bitstream as addressed in the order of the time slots stored in the routing memory.

Referring to FIG. 9, an information memory for storing input message bits of a PCM channel is composed of an odd memory block 708 and an even memory block 709. This configuration allows the use of slower memory circuits by allowing the input message bits of the input PCM channel to be stored in one memory block, and at the same time allowing the output message bits of the output PCM channel to be read from other memory blocks, thereby reducing the cost. Can be saved. At the end of one frame, this process is reversed, the memory block just read is written, and the memory just written is read.

Time-slot counter 704, controlled by the system clock and reference signal, addresses odd and even memories 708 and 709 via latch 716 through latching multiplexers 706 and 707, respectively. Provides a series of time slots. The time slot of the time-slot counter 704 also addresses the routing memory 702 to read out the specified time slot.

The predetermined time slot read from memory 702 is addressed via multiplexer 706 or 707 to address the message bits for the output PCM channel from particular memory block 708 or 709.

Recombining the order of time slots for the output PCM channel in routing memory 702 is through multiplexer 701 under the control of switch computer interfaces A and B defined by SCI selection A / B. The new time slot of the output channel, represented by the twelve data bits from the multiplexer 701 and exiting the switch computer interface, is writable of the switch computer interface during the time slot of the time slot counter 704 that responds to the output PCM channel. The signal is stored in the routing memory 702 instead of the 12 bits previously stored.

The routing memory stores 384 sequential time slots of 12 bits. Each 12-bit sequential time slot contains 9 bits for the time slot number, 2 bits for selecting one of 4 blocks of information memory, and 1 bit for loop feedback. With the exception of the feedback bit, multiplexers 706 or 707 address the remaining 11 bits to specific message bits in radix or even memory 708 or 909 so that the output parallel bit stream is read. The routing memory 702 may be composed of any number of conventional memories having a storage capacity of 384 x 12 bits.

The multiplexers 711-714 select the parallel PCM bit stream of the dedicated supergroup interface or the parallel PCM bit stream of the auxiliary supergroup interface by the control of the multiplexer 715.

Multiplexer 715 provides a selection line of switch computer interface A or B determined by SCI selection A / B.

The odd and even memories 708 and 709 are divided into four blocks corresponding to four dedicated supergroup interfaces. Each of these four blocks stores nine message bits for 384 PCM channels, corresponding to the corresponding parallel PCM bit stream. As long as four blocks have a memory capacity of 384 x 9 for each block, any number of general memories may be configured. Four blocks of radix memory 908 and four Tri-state outputs of even memory 709 are grouped together and applied to multiplexer 710. The message bits read from memory 708 or 70 are gated to multiplexer 710 by the control of time-slot counter 704 and sent to the output parallel PCM bit stream. Additional bits for loop return operation from the routing memory 702 are provided with the output parallel PCM bit stream.

3. Signal Bit Transceiver (Fig. 10)

The signal bit transceiver (SBS / R) stores the input signal coming from the corresponding supergroup interface for each input PCM channel, and reports the logical change of each signal bit to the signal processor if it is not intentionally ignored. The signal bit transceiver also stores each output signal bit, and the parity bits of the corresponding time-slot exchanger can be modified by the stored signal bits and control bits before being applied to the corresponding supergroup interface by the signal bit transceiver.

In FIG. 10, multiplexer 807 by select decoder 811 sends signal bits and group alert bits from the corresponding supergroup interface to debounce logic 806 and alert memory 809, respectively. The select decoder 811 decodes the select line from the switch computer interface indicating the configuration of the PCM message and signal exchange. The time-slot and frame counter 802 receives a system clock and a reference signal, sends the time-slot address to the memory address selector 803, the timing control to the memory control logic circuit 804 and the output control logic circuit ( 810). The memory address selector 803 selects a time-slot address from the time slot and frame counter 802 or a time-slot address from the bus interface 701 by the instruction of the memory control logic circuit 804, The selected address is sent to the signal bit memory 805, the debound logic circuit 806, and the alarm memory 80.

According to the T1 format, there are 12 frames in multiple frames, with frames 6 and 12 having signal bits for the input PCM channel. The order of the output frames is one frame delayed from the order of the input frames. For example, if input frame 6 is received, output frame 5 is transmitted. Time-slot and frame counter 802 provides the necessary input frame signal. Paraser, output signal bits are read from signal bit memory 805 during frames 7 and 1.

In the following, frames are all referred to as input frames. The signal bit memory 805 stores two input and output signal bits together with one control bit for 384 input / output channels each. Therefore, the storage capacity of the signal bit memory 805 is 384 x 5 bits. The output signal bits and output control bits of each PCM channel are changed or read out via the bus interface 801 by a computer switch.

During frames 6 and 12, the debound logic circuit 806 senses the change by comparing the logic state of the input signal bits selected from the multiplexer 807 with the signal bits received from the signal bit memory 805. The last three bits of the received signal for a particular PCM channel represent a change in logic state, which is stored temporarily to notify the switch computer interface of the change of the signal bit if it is not ignored. During frames 2 and 8, the temporarily stored contents are transmitted to the signal bit memory 805.

The debound logic circuit 806 includes a memory that stores the number of logic state changes and ignored (mak) bits of the input signal bits for each input channel. If the ignored bit of the input signal bit for the input PCM channel is a logic " 1 ", the logical state change of the particular input signal bit continues to be stored and not informed of the switch computer interface. This action is necessary because the signal bits of some PCM channels have no meaning. The mask bits of each input PCM channel stored in the memory of the debounce logic circuit 806 are changed or read out by the switch computer via the bus interface 801.

If the change in the logical state of the group alarm bit is detected, the alarm memory 809 is modified. A change in the status of the group alarm bit is detected. The change in alert bit state is then communicated to the switch computer interface via the bus interface 801. By the request of the switch computer interface, the alarm memory 809 is operated by the memory control logic circuit 804 together with the bus interface 801. Similarly, output signal bits and control bits received by bus interface 801 are stored in signal bit memory 805 when operated by memory control logic 804. Output signal bits and control bits for the output PCM channel are stored in the signal bit memory 805 addressed via the bus interface 801 by the memory address selector 803. Information is transferred from the bus interface 801 to the memory of the signal bit memory 805 or the debound logic circuit 806 during frames 3-5 and 9-11. Again, mask bits or signal bits are read by the switch computer interface during this frame period.

The multiplexer 808 sends output signal logic and parity bits of the time-slot exchanger selected by the select line to the output control logic 810 during frames 7 and 1. The output signal bits are read from the signal bit memory 805 of each corresponding time-slot address and applied to the control logic circuit 810. The output control logic 810 responds to control bits associated with the output signal bits and parity bits of the corresponding supergroup interface. For example, if both the control bit and the output signal bit of the signal bit memory 805 are logic '0', the output signal bit and the parity bit of the corresponding time-slot exchanger are provided to the supergroup interface. If the control bit is a logic '0' and the signal bit is a logic '1', the output signal bits and the parity bits of the time-slot exchange are logically swapped. However, if the control bit is a logic '1', the output signal bit of the signal bit memory 805 is supplied to the corresponding supergroup interface.

In all the examples listed above, if the signal bits going to that supergroup interface are different from the output signal bits of the time-slot exchange, the parity bits are logically changed to hold the parity of the message bits for the particular PCM channel. During all other frame 2-6 and 8-12 periods, the output signal bits and parity bits from the TSI are provided directly to the corresponding SGI by the output control logic circuit 810. It should be appreciated that many other implementations of the output control logic circuit 810 may give possible other functional functions to be performed on the output signal bits and the parity bits.

4. Switch Computer Interface (Figure 11)

The switch computer interface (SGI) is associated with a signal processor that allows the exchange of supervised signal information for each PCM channel and also orders the time slots in the digitizing memory.

The switch computer interface informs the signal processor of all alarms detected on the digital switching network. The signal processor receives the reported alerts and makes up the block structure of the digital switching network to compensate for the malfunction.

Referring to FIG. 11, the differential clock and reference receiver 902 receives a system clock and a reference signal, and supplies the clock and reference signals to the time-slot and frame counter 901 so that the entire PCM message and signal exchange unit can be found. To pass on.

The time-slot and frame counter 901 provides time control of the parity alert encoder 903, the SBS / R control latch 910 and the TSI control latch 912. The parity alert encoder 903 receives the SGI parity alert and the GM parity alert and the GI parity alert via the automatic receiver 904.

The parity alert encoder 903 multiplexes various parity alerts to the bus control 905 for transmission to the signal processor.

The bus control 905 includes a mask register that allows the signal processor to selectively ignore the alert bit when the corresponding mask bit is a logic '1'. This mask bit can be modified or read by appropriate instructions of the swap processor.

The signal processor supplies the 16-bit output command switch computer interface stored in the latch 908. Eight bits of the output command from latch 908 are sent to command decoder 909. The command decoder 909 decodes an 8-bit output command and sends a decoded control command having up to 6 bits to the selected control latch. For the configuration of the multiplexer / demultiplexer unit and PCM message and signal exchange of the digital switch network, the system placement latch 906 responds to the appropriately decoded control command from the command decoder 906. The system placement latch 906 provides a control signal for selecting a group multiplexer A or B in the four supergroups of the multiplexer / demultiplexer unit, via the automatic driver 907. Thus, system placement latch 906 configures redundant TSI, SGI, and SBS / R according to the selected SGI to replace the failed module when needed, and controls PCM messages and signal exchanges to select SCI A or B. Provide a line. The system placement latch 906 is read through the bus control (05) by appropriate instructions in the signal processor to provide an immediate configuration of the message and signal exchange.

The SBS / R control latch 901 receives a decoded control command to select one of the signal bit transceivers. At the same time, the decoded command activates the SBS / R data latch 913 to receive data bits from the latch 908 which is sent to the selected SBS / R. Again, IRD latch 914 also operates by a decoded SBS / R control command to receive data bits from latch 908 to provide address information to SBS / R. The data sent to the selected SBS / R provides mask bits, output signal bits and corresponding control bits that ignore the input signal bits for the selected input PCM channel. If data is read from the selected SBS / R, the read data and its corresponding address are returned to the bus control 905 via the bidirectional data buses 920 and 921, respectively, for transmission to the signal processor.

The TSI control latch 912 is applied with the appropriate decoded control command from the command decoder 909 to select one of the TSIs. The decoded TSI write-control command operates the IRS latch 911 to receive 12 data bits from the latch 908 to store a TSI data word for storing a new time slot in the routing memory of the shelf TS. to provide. The decoded TSI read-control command operates the selected TSI to read the stored time slots from the routing memory, transfer them to the bidirectional data bus 922, and send them back to the signal processor by the bus control 905. Read-control and write-control are performed during the time slots of the corresponding PCM channel being accessed.

III. Signal processing section (FIGS. 1 and 12)

The operation of the signal processor 50 may be further described with reference to FIG. 1. The exchange control unit 58 processes the supervisory signal from the T1 bit stream for transmission to the call processing computer 51.

The call processing computer 51 determines the time slot order of the PCM channel to the digital switching network in response to the supervisory signal from the switching control section 58.

The call processing computer 51 is processing the work of the organization structure computer 53, the DAS and the database computers 52 together to establish a communication path between the mobile radio telephone and the fixed landline telephone.

The call processing computer 51 ensures that all calls are connected according to the telephone system dialing plan for the telephone system in a specific area. The telephone numbering plan is described in Chapter 1 of the "Basic Telephone Switching System", published by Hayley Publishing Co. in 1969 and published by Tleyley, and published in "1975." It is well described in Chapter 2.

A teleprinter 54 enables human-machine communication with the call processing computer 51 to access the source of the telephone system and automatically record the routine and alarm information.

The processing of a particular call is made by the exchange control unit 58 and the call processing computer 51. Upon detecting an off-hook or on-hook condition of any particular analog port, the exchange control unit 58 automatically connects the particular port to the progress tone of the tone signal generating unit. In preparation for the reception of dialing, a predetermined analog port using a multi-frequency signal is connected to the tone signal section by the switching controller 58 in order to receive a certain type of multi-frequency signal. Otherwise the dialed number is received and sent to the call processing computer 51 for analysis. The dialing information is analyzed and verified by the call processing computer before it is fixed in a particular format for output pulses to the output PCM channel of the called. When the call ends, the signaling action required by the exchange control unit 58 is provided.

The analysis of the dialed number by the call processing computer 51 works with the DAS database computer 52 to determine the interpretation of the number of dialed numbers that match the calling party's class of service and the system dialing plan. In the case of a mobile radiotelephone, this decision is whether a particular mobile telephone number is valid and whether it belongs to the subscriber list of the telephone system.

Mobile phones that are not subscribed are denied service. Mobile wireless telephones that do not belong to a local mobile telephone network belong to a remote mobile telephone network that can be accessed from a local mobile telephone network.

Subscribers, files, number analysis tables and other necessary system files are stored in mass storage 56. The DAS and database computer 52 keep a record of billing in a magnetic recorder (magnetic tape) 55.

Once it is determined that the dialed number is valid, organization structure computer 53 provides the necessary radio path for the called mobile radio telephone. If the call was initiated by a mobile radiotelephone, the radio communication path was already made by the organization structure computer 53. The organization structure computer 53 manages tracking of the mobile radio telephone during the call in order to perform the necessary hand-off when the mobile radio telephone has moved from one cell to another. For example, a hand-off of a call may be initiated by setting up a Paris call through the party page, with an empty radio channel in the nearby organization being included as a third fly in the particular telephone organization. If the mobile radiotelephone is moved to an adjacent organization, the old radio channel is shattered and communication is carried out by the new radio channel.

In FIG. 12, the exchange control unit includes an exchange control computer 100, a clock and reference A 101, and a clock and reference B 102. In FIG. The switching control computer 100 is interfaced with the call processing computer by various internodal links A and B, and is interfaced to the switching computer interface unit via a 32-bit input / output bus. The computers 51, 52, 53, and 58 (FIG. 1) of the telephone system are composed of two computers, so that one can perform the necessary work in the event of a failure. The computer could be a microcomputer system, for example Motorola's M 6800, or any computer or microcomputer available on the market.

The detailed operation and programming of Motorola's M 6800 microcomputer is described in "M 6800 Microcomputer System Design Data" and "M6800 Programming Reference Manual" published by Motorola in 1976, Thomas H, June 14, 1977 This is described in detail in US Pat. No. 4,030, 079 to "Processor with Incrementer and Program Register Structure" by Bennett et al.

The 32-bit I / O bus to SCI consists of a unidirectional bus with 16-bit output. Instructions from the switching control computer 100 are provided to the 16-bit output bus by a 16-bit word with a command portion and a data portion. Similarly, information from SCI 16 is provided on a 16-bit input bus with a data portion and a coded address portion that indicates the nature of the data portion. This 16-bit bus is a commercially available interface adapter, such as the Motorola 6820 Peripheral Interface Adapter described in the above-mentioned manual, or as described in US Pat. It is interfaced to the control computer 100 by the interface adapter.

Clocks and references A and B (101, 102) provide a system clock and reference signal that synchronizes the various units in the digital switching network.

Clock and reference A 101 are main units, and clock and reference B 102 are subunits. The clock signal is automatically provided to the digital switching network at a frequency of 3.088 MHz. In addition, another 3.088 MHz clock signal is supplied to each computer of the signal processing section. Each reference signal provided automatically is a pulse that occurs at the beginning of each multiple frame of the T1 format, which is used to synchronize the digital switching network with the multiple frames.

The clock and reference B 102 are in phase synchronization with the clock and reference A 101, but the clock and reference B 102 operate independently even when the clock and reference A 101 malfunction.

The above implementation was intended to illustrate the principles of the invention. Accordingly, those skilled in the art may make other modifications or implementations without departing from the scope and spirit of the invention.

Claims (1)

Digital switching network 40, including multiple basic stations 60, digital switching network 40, PCM A / D and D / A converters 30, etc., has multiplexer 41 and time-slot exchanger ( In a telephone system composed of a mobile radiotelephone system 30, 40, 50, 60 comprising a demultiplexer 41 and a wired telephone system 20, the signal detecting means 41, 42 are connected to an input PCM channel. An input signal bit sensed for each of the input serial PCM bit streams to detect an input signal bit and for determining a time slot in the routing memory such that the input PCM channel is associated with the selected output PCM channel in the signal processing unit 50. And a time-slot exchanger 42 responds to the sequence of timeslots in the routing memory to couple the input PCM channel with the corresponding selected output PCM channel, and the signal processor 50 outputs the output PCM. Can be recognized by the channel Responsive to the sensed input signal bits to generate corresponding output signal bits corrected in a predetermined format, and characterized in that the signal detection means (41, 42) are arranged to supply the output signal bits to the output parallel bit stream. Wireless telephony system.

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