KR830001634B1 - Instruction display - Google Patents

Abstract

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Description

Instruction display

1 is an electrical block diagram of one embodiment of the present invention.

2 and 3 are plan views of electrode patterns showing a part of the above embodiment.

4 to 5 are detailed circuit diagrams of the main parts of FIG.

6 is a diagram illustrating the operation of FIG.

7 is a plan view showing the state of the specific indications.

8 is an electrical block diagram of another embodiment.

9A and 9B are plan views of electrode patterns.

10 to 12 are detailed circuit diagrams of the main parts of FIG.

13 is a table for explaining the operation of FIG.

14 is a plan view showing the state of the specific indications.

The present invention relates to a guide display device for use in an analog electronic clock.

In the conventional display device for an analytical electronic clock, it is roughly classified into using mechanical erosion display and optical display instead of erosion display. In the latter display device, a light emitting device such as a light emitting diode is arranged in a circular shape, the light emitting device is integratedly displayed, or the lighting state is sequentially moved to display the progress of time. . However, since we are in the habit of looking at the time according to the positional relationship between the long and the short hands, it is inconvenient to quickly recognize the essential time of the clock, as the optical display form may have a decorative effect. . Thus, efforts have been made to approach the display in the form of a guideline at all, and such an optical display device can be seen, but due to the limitations of electronic circuits and display elements, most of them cannot display the guideline completely. There was a difficulty.

Therefore, according to the present invention, at least two kinds of pulse signals are selectively applied to the segment electrode and the divided common electrode constituting the aggregate according to the display information selected in time division by bending the aggregate of the plurality of display portions having the guide shape. The above-described conventional drawback is eliminated by providing a guide display device which is applied to control the lighting of the display unit.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In Fig. 1, (1) is a crystal oscillator, (2) is a frequency divider, (3) and (4) is a hexadecimal and five-counter counter that counts the minute unit. (5) and (6) are counters of digits and digits that post the unit of time.

Each counter above generates an output of a binary decimal code. (7) and (8) are gate circuits having an end function, and the output of the flip-flop circuit 9 controls the passage of each output of the counters 3 and 4. The gate circuits 10 and 11 also have an end function in the same manner, and control the passage of each output of the counters 5 and 6. (12) and (13) are gate circuits having a malfunction function. (14) and (15) are decoders for code conversion. Numeral 16 denotes an output rank switching circuit for switching the order of the output of the decoder 14, which is necessary for the wiring form of the electrode described later. Reference numeral 17 denotes a segment potential setting circuit for setting a potential to be drawn to a segment electrode of the display device. 18a and 18b are common potential setting circuits for setting potentials to be applied to the common electrode of the display device. Numeral 19 is a flip-flop circuit whose output controls on and off of the switching circuits 20-27 composed of semiconductors and the like. Reference numeral 28 is an inverter, and 29-33 are gate circuits.

2 and 3 show an electrode pattern of a liquid crystal display device displaying instructions.

In Fig. 2, reference numeral 34 denotes an excretion state of a segment electrode having an electrode number of 60, and a segment electrode 34a having an electrode number of 12. 34a is connected to terminals e ₁ -e _{12 of the} segment potential setting circuit 17 as shown in the figure. The other segment electrode has the connection relationship shown below. In addition, the order of segment electrode is made into the segment electrode 34a connected to the terminal e ₁ first, and makes it clockwise. The 12th segment electrode 34a is the 13th segment electrode 34a, and the 11th is the 14th segment. The first is the 24th, the 24th is the 25th, the 25th is the 26th, and so on. The thirteenth is jointly connected with the thirty sixth. The segment electrodes up to the 60th are connected in the above relationship.

FIG. 3 shows the common electrode pattern 35, and constitutes common electrodes 35a and 35b divided into five parts inward and outward. And each of the divided grooves 35c of the common electrodes 35a and 35b. Reference numeral 35c denotes between the 12th and 13th segment electrodes in the clockwise direction, the 24th and 25th segment electrodes, the 36th and 37th segment electrodes, the 48th and 49th segment electrodes, and the 60th and 1st segments. It is configured to be positioned between the segment electrodes of.

In addition, the liquid crystal display device is constituted by an aggregate of a display unit composed of a liquid crystal between a segment electrode and a common electrode, but the configuration can be easily carried out by a person skilled in the art, and the present invention is such a configuration. It is omitted because it does not have its own characteristics.

4 is a detailed view of the output priority switching circuit 16 and the segment potential setting circuit 17 shown in FIG. 1, wherein (36) to (50) are gate circuits, and (51) to (60) are shown in FIG. The switching circuits 61-65 as shown in FIG. 1 are inverters.

5 is a detailed view of the common potential setting circuit 18a, where (66)-(71) is a switching circuit as shown in FIG. 1, and (72)-(74) are inverters. The common potential setting circuit 18b also has the same configuration.

가 “1”일때 각 단자에 발생하는 전위를 나타내고 있다. 또, 전압(Vs-C)는 단자(S₀),(S₁) 및 단자(C₀),(C₁)간의 전위차를 나타내고 있다. 이것에 의하여 명백하듯이, 단자(S₀)와 (C₀)에 발생하는 전위차에 의하여 표시부가 점등된다.In the above configuration, the potentials to be applied to the segment electrodes generated at the terminals S ₀ and S _{1 of} FIG. ₁ and the potentials to be applied to the common electrodes generated at the terminals C ₀ and C _{1 are} shown. The state and the voltage between both electrodes will be described. The set potentials are (O), (V ₀ ), (2V ₀ ), and (3V ₀ ), and the liquid crystal display device in this embodiment has a non-lighting under voltage | 1V ₀ | , Shall be lit above voltage | 3V ₀ |. Potential (3V ₀ ) at terminals (l ₀ ) and (l ₅ ) of switching circuits 20 and (25), potential (2V ₀ ) at terminals (l ₃ ) and (l ₆ ), terminal (l ₂ ), ( A potential V ₀ is applied to the terminal ₇ and a terminal O ₁ and a terminal ₄ , so that the flip-flop circuit 19 is triggered by the output of the flip-flop circuit 9. Output When the switching circuits 20 to 27 are switched, the potential generated at the terminals S ₀ , S ₁ , C ₀ , and C ₁ and the low voltage between the terminals are as shown in FIG. do. In the table, the potential Vs represents the potentials that the terminals S ₀ and S ₁ can take, the potential VC represents the potentials that the terminals C ₀ and C ₁ take, The left side of the two potentials is the potential generated at each terminal when the output Q ₂ of the flip-flop circuit 19 is the logic value "1" (hereinafter simply referred to as "1"), and the right side is the output.

Indicates the potential generated at each terminal when is "1". In addition, the voltage Vs-C represents the potential difference between the terminals S ₀ , S ₁ and the terminals C ₀ , C ₁ . As is apparent from this, the display portion is turned on by the potential difference generated at the terminals S ₀ and C ₀ .

는 “1”, (X)는 “0”가 된다.According to the above state, the display operation when the counters 3 to 6 post 10:10 will be described. In this state, the minute counters 3 and 4 are "10" and "0", respectively, and the counters 5 and 6 of the hour are "2" and "4", respectively. Whenever "1" occurs periodically at the output Q ₁ of the flip-flop circuit 9 by the output of the divider 2, the gate circuits 7 and 8 are opened so that the counters 3 and 4 ) Data is selected to generate a binary coded decimal code of "10" and "0" at each output of the gate circuits 12 and 13. That is, "1" is generated at the terminals of (2 ¹ ) and (2 ³ ) of the gate circuit 12, and 0 is generated at the terminals of (2 ⁰ )-(2 ² ) of the gate circuit 13. Thus terminals

Is “1”, (X) is “0”.

가 “1”임으로, 게이트회로(45)의 출력이 “1”, 따라서 게이트회로(47)의 출력이 “1”가 되고 스위칭회로(57)이 온이되고, 세그멘트전극의 단자(e₁₁)에, 단자(S₀)에 생기는 전위가 발생한다. 한편, 상기 이외의 게이트회로(38)(41),(44)…(50)의 출력이 “0”이 되기 때문에 스위칭회로(52),(54),(56)…(60)이 온이 되고, 단자(S₁)이 생기는전위가 단자(e₁)-(e₁₀),(e₁₂)에 발생한다.Each output code of the gate circuits 12 and 13 is converted to the decoders 14 and 15, and the decoder 1 is connected to the terminal of the decoder 10 at " 1 " “1” is generated at the terminal of “0” of 15). Referring to FIG. 4 here, the terminal

Is “1”, the output of the gate circuit 45 is “1”, so that the output of the gate circuit 47 is “1” and the switching circuit 57 is turned on, and the terminal electrode ₁₁ of the segment electrode is turned on. Is generated at the terminal S ₀ . On the other hand, the gate circuits 38, 41, 44... Switching outputs 52, 54, 56,... (60) turns on, and a potential at which the terminal S ₁ is generated is generated at the terminals e _1- (e ₁₀ ) and (e ₁₂ ).

On the other hand, since the terminal j ₀ of the decoder 15 is “1”, referring to FIG. 5, the switching circuit 66 is turned on, and the potential generated at the terminal C ₀ is the terminal g of the common electrode. ₁ ) occurs. And the switching circuit 69. Since 71 is turned on, a potential generated at the terminal C ₁ is generated at the terminals g ₂ and g ₅ .

In addition, since the output Q ₁ of the flip-flop circuit 9 shown in FIG. ₁ is "1", the output terminal Y ₀ of the gate circuit 29 becomes "1". Therefore, as shown in the common potential setting circuit 18a shown in FIG. 5, which is configured similarly to the common potential setting circuit 18b, the potential generated at the terminal C ₀ is applied to the terminal K ₁ . Generated, and a potential generated at the terminal C ₁ is generated at the terminals K ₂ -K ₅ .

According to the table shown in FIG. 6, the relationship between the potential states of the above-described respective elements is composed of a segment electrode connected to the terminal e ₁₁ and a common electrode connected to the terminals K ₁ and g ₁ . The display section lights up.

에 주기적으로 “1”가 발생할 때마다 시의 카운터(5),(6)의 시의 데이터가 선택되고 데코우더(14)의 “2”의 단자에 “1”, 데코우더(15)의 “4”의 단자에 “1”를 발생한다. 게이트회로(13)의 (2⁰)의 단자는 “0”이므로 단자(X)는 “0”,

는 “1”이 된다.Next, the output of the flip-flop circuit 9 shown in FIG.

Whenever "1" occurs at the time, the data of the time of the counter (5) and (6) of the hour is selected and "1" to the terminal of "2" of the decoder 14, and the " “1” is generated at the terminal of 4 ”. Since the terminal of (2 ⁰ ) of the gate circuit 13 is "0", the terminal X is "0",

Becomes "1".

Referring to FIG. 4, the output of the gate circuit 42 is "1", and therefore, the output of the gate circuit 44 is "1", and the switching circuit 55 is turned on so that the terminal is connected to the terminal e ₃ . A potential occurring at (s ₀ ) occurs. The other terminal is generated, the potential generated in the terminal (s _1). In addition, since the terminal j ₄ of the decoder 15 is "1", the potential generated at the terminal g ₅ and the terminal c ₀ in FIG. ₅ is generated, and other terminals g _1- ( g ₄ ) generates a potential generated at the terminal c ₁ . On the other hand, the gate circuits 29-33 shown in FIG. ₁ have their outputs being "0" because the output Q ₁ of the flip-flop circuit 9 is "0", and the terminal k _1- The potential generated at the terminal c ₁ is generated at (k ₅ ).

In this way, the display portion constituted by the segment electrode connected to the terminal e ₃ and the common electrode connected to the terminal g ₅ is turned on.

7 shows the display state of the above guideline.

Next, an example of the three-needle display will be described. In Fig. 8, (75) and (76) are decimal counters and hex counters that start the units of seconds, respectively, and (77) and (78) are the decimal counters and hex counters that respectively indicate the units (79) and (80) are decimal and hex counters that respectively indicate units of time.

Each counter above generates an output of a binary decimal code. 81 is a 12-digit counter. Reference numeral 82 denotes a timing pulse generator, which sequentially generates pulses at terminals p _{1 to} p _{3 with} the generation of an output pulse from the divider 2. (83)-(88) are gate circuits having an AND function, and are controlled by pulses sequentially generated from terminals p _{1 to} p ₃ . Reference numerals 89 and 90 denote gate circuits having a negative function.

Reference numerals 91 and 92 are decoders for converting output signals of the gate circuits 89 and 90, respectively. Reference numeral 93 denotes an output priority switching circuit, and the output rank of the decoder 61 is switched in accordance with one output state of the gate circuit 90. Reference numeral 49 denotes a segment potential setting circuit for selecting the potential applied to the segment electrode, which will be described later in detail, and 95 denotes a common potential setting circuit for selecting the potential applied to the common electrode. Reference numeral 96 denotes a flip-flop circuit, reference numeral 97 denotes a potential setting circuit, and potentials 0, v ₀ , and 2v at terminals s ₀ , s ₁ , c ₀ , and c ₁ . ₀ ) and (3v ₀ ) generate a predetermined potential periodically. Reference numeral 98 is an inverter. 1, the same reference numerals denote the same functions.

9A and 9B show the patterns 99 and 100 and the wiring pattern of the segment electrode and the common electrode, respectively. FIG. 9A shows the 60 needle electrode 99a, and has the same wiring form as FIG. 2A except that the number of segment electrodes in the group is changed from 12 to 10. FIG.

9B is composed of common electrodes 100a and 100b, divided into six in the main direction, and each divided common electrode 100a and 100b faces a segment electrode having an electrode number of ten. Doing. The segmented electrode, the common electrode, and the liquid crystal form a display portion of the guide shape.

10 is a detailed circuit diagram of the output priority switching circuit 93 and the segment potential setting circuit 94, (101)-(115) is a gate circuit, and (116)-(125) is a switching circuit as shown in FIG. 126) -130 are inverters.

11 is a detailed circuit diagram of the potential setting circuit 97, 131 to 138 are switching circuits, and 139 are inverters.

12 is a detailed circuit diagram of the common potential setting circuit 95, (140)-(145) is a gate circuit, (146)-(155) is a switching circuit as shown in FIG. 1, and (156)-(160) is an inver It is an aftertaste.

In the above configuration, the state of the potential to be applied to the segment electrode and the common electrode and the voltage between both electrodes will be described. The potentials are (0), (v ₀ ) (2v ₀ ) and (3v ₀ ), and the lighting and non-lighting voltages of the liquid crystal display in this embodiment are the same as in the previous embodiment. In the 11 degrees to the terminal _{(l 1), (1 4} ) to (0), the terminal _{(l 2), (1 7} ) to (v _0), the terminal _{(l 3), (1 6} ) (2v 0) The potentials of (3v ₀ ) are applied to the terminals l ₀ and 1 ₅ . When "1" is periodically generated at the terminal p ₁ of the timing pulse generating circuit 82 in FIG. 8, "1" and "0" are alternately generated at the output Q of the flip-flop circuit 96. do. For this reason, the potentials 0 and 3v ₀ at the terminal s ₀ shown in FIG. 11, the potentials v ₀ and 2v _{0 at the} terminal s ₁ , and the potential at the terminal c _{0 are} shown. The potentials 2v ₀ and (v ₀ ) alternately occur at (0) and (3v ₀ ) and the terminal (c ₁ ). This relationship is summarized in FIG. 13, and the configuration of the diagram is as described above. As is apparent from FIG. 13, when a potential is applied to the terminals s ₀ and (c ₀ ), the display portion corresponding thereto is lit.

에 “1”, 단자(h)에 “0”, 데코우더(91)의 단자(x₅)에 “1”를 발생한다. 여기서 제10도를 참조하면, 게이트회로(105),(113)의 출력이 “1”가 되기 때문에 단자(s₀)에 생기는 전위가 단자(e₆)에 발생한다. 그밖의 단자(e₁)-(e₅) 및 (e₇)-(e₁₀)에 대해서는 스우칭회로(117)…(119),(123)…(125)가 온이되기 때문에, 단자(s₁)에 생기는 전위가 발생한다.As an example, a description will be given of the indications when the counters 75-80 shown in FIG. 8 show 10: 5 seconds. In this timekeeping state, the counter 75 is "5", the counter 76 is "0", the counter 77 is "0", the counter 78 is "0", the counter 78 is "0", The counter 80 counts "5". Here, as the pulses are periodically generated at the terminal p ₁ of the timing pulse generating circuit 82, the gate circuits 83 and 86 in the unit of seconds are opened, and the data of the seconds of the counter 75 is opened. The second data of the counter 76 is input to the gate circuit 89 to the gate circuit 90. Therefore, "1" is generated at the terminals of (2 ⁰ ) and (2 ² ) of the gate circuit 89, and "0" is generated at the terminals of (2 ⁰ )-(2 ² ) of the gate circuit 90. do. As a result

At “1”, “0” at terminal (h), and “1” at terminal (x ₅ ) of decoder 91. Referring to FIG. 10, since the output of the gate circuits 105 and 113 becomes "1", a potential generated at the terminal s ₀ is generated at the terminal e ₆ . For the other terminals (e ₁ )-(e ₅ ) and (e ₇ )-(e ₁₀ ), the stitching circuit 117... (119), (123)... Since 125 is turned on, a potential generated at the terminal s ₁ is generated.

는 “1”이고, 게이트회로(140)-(145)가 열려 있다. 따라서, 스위칭회로(146)이 온이되고, 단자(c₀)에 생기고 있는 전위가 단자(g₁)에 발생한다. 그밖의 단자(k₂)-(k₆), (g₂)-(g₆)에 단자(c₁)에 생기고 있는 전위가 발생한다. 그결과, 단자(e₆)과 단자(g₁),(k₁)에 전위가 인가되었을때에 표시부가 점등된다.Next look at the décor woodeo 92, the terminal and (y ₀₎ to "1", generating a terminal voltage generated in the (k ₁₎ to the terminal (c _0), as shown in the FIG. 12 to occur due. In addition, terminals of the timing pulse generating circuit (82) (p ₃₎ a terminal because it is "0"

Is "1", and the gate circuits 140-145 are open. Thus, the switching circuit 146 is turned on, and a potential generated at the terminal c ₀ is generated at the terminal g ₁ . The potential generated at the terminal c ₁ is generated at the other terminals (k ₂ )-(k ₆ ) and (g ₂ )-(g ₆ ). As a result, the display portion lights up when a potential is applied to the terminal e ₆ and the terminals g ₁ and k ₁ .

는 “1”(h)는 “0”를 유지한다.Next, when a pulse is periodically generated at the terminal p ₂ of the timing pulse generating circuit 82, the gate circuits 84 and 87 are opened, and the respective data “0” of the counters 77 and 78 are “0”. Go through them. Therefore, “1” is generated at the terminal (x ₀ ) of the coder 91, and “1” is generated at the terminal (y ₀ ) of the decoder 92.

Keeps "1" (h) "0".

Accordingly, the output of the gate circuit 111 in FIG. 10 becomes "1", the switching circuit 116 is turned on, and a potential generated at the terminal s ₀ is generated at the terminal e ₁ . In addition, potentials generated at the terminal s ₁ are generated in (e ₁ )-(e ₁₀ ).

In FIG. 12, potentials generated at the terminals s ₀ are generated at the terminals g ₁ and k ₁ , and the other terminals g _2- (g ₆ ) and (k ₁ )-(k _{6) are generated.} ), A potential generated at the terminal c ₁ is generated. Thus, in the diagram of FIG. 13, the display portions corresponding to the terminals e ₁ , the terminals g ₁ , and k ₁ are lit.

When the gate circuits 85 and 88 are opened by the pulses periodically generated at the terminal p ₃ of the timing pulse generation circuit 82, the outputs of the counters 79 and 80 are interposed therebetween. To pass. As a result, a potential generated at the terminal s ₀ is generated at the terminal e ₁₀ of the segment potential setting circuit 94. The potential generated at the terminal c ₀ is generated at the terminal k ₆ of the common potential setting circuit 95, and the potential generated at the terminal c ₁ is generated at the other terminals k _1- (k ₅ ). . When a pulse is generated at the terminal p ₃ , the output of the gate circuits 141-145 shown in FIG. 12 becomes "0". Therefore, in the terminals g ₁ -g ₆ , In all, a potential generated at the terminal c ₁ is generated.

Therefore, the display portions corresponding to the terminal e ₁₀ and the terminal k ₆ are turned on. 14 shows the indications of the present embodiment.

As described above, the present invention divides the segment electrodes, and connects segment electrodes of a predetermined rank in each group in common, and the guide display unit includes the segment electrodes and the divided common electrodes as components. In this case, the pulse signal is selectively supplied according to the time-divided display information. Therefore, despite the large number of segment electrodes, the number of terminals is small, so that the reliability is high and extremely effective in connection with the circuit system. Moreover, since the operating margin is large, there is no crosstalk, the response is quick, and there is stability over a wider range of temperatures. Since it is the same form as the conventional erosion, time can be seen quickly. In addition, the driving of the display device is not a dynamic drive for each common electrode, but a quasi-static drive for each information unit, so that power consumption is low.

In addition, in order to control the lighting of the display unit for each set unit information, even if the total information amount increases, the information amount to be displayed at the same time is constant, so that the display can be performed without changing the set potential state.

Claims (1)

An aggregate comprising a segment electrode 34a and a common electrode 35a and 35b as a component and radially disposing a display unit for indicating a guide shape, wherein the common electrode is divided into at least two segments in a guide direction for each predetermined number of segment electrodes. A configuration in which the corresponding segment electrodes in each segment electrode group having the configuration as the group having the predetermined number of segment electrodes are conductively connected, and time-divisionally selects the unit output of the counter 3-6 for timekeeping. A segment electrode selection circuit 14-16 which has a circuit 7-11 and selects a segment electrode of the display portion to be lit in response to a part of the output from the selection circuit 7-11; 11) in response to the remaining output of the carry from the common electrode selection circuit (15,30-33) for selecting the common electrodes of the display, voltage 0, v _0, each pulse train of ₀ and 2v 3v ₀ (列Pulse generator that generates (19-27), the segment potential setting circuit 17 which applies a pulse string for lighting to the segment electrode of the display part to be lit, and applies a pulse string for non-lighting to the segment electrode of the display part to be turned on, turns on A guide display device having common potential setting circuits (18a, 18b) for applying a pulse train for lighting to a common electrode of a display unit and applying a pulse train for non-lighting to a common electrode of a display unit to be turned on.

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