KR20240161700A - Photonic communication platform and related architectures, systems and methods - Google Patents

Abstract

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communications are described. Techniques, architectures, and processes that improve the performance of conventional computers are described herein. Some embodiments provide photonic interposers that utilize photonic tiles, each tile including programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some of the tiles are instantiations of a common template tile that are stitched together in a 1D or 2D array. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles with photonic links.

Description

{PHOTONIC COMMUNICATION PLATFORM AND RELATED ARCHITECTURES, SYSTEMS AND METHODS}

Cross-reference to related applications

This application claims the benefit of U.S. Provisional Application Serial No. 63/324,598, filed March 28, 2022, entitled PACKAGE ASSEMBLY FLOW AND MATERIALS (Attorney Docket No. L0858.70053US00), U.S. Provisional Application Serial No. 63/325,113, filed March 29, 2022, entitled PACKAGE ASSEMBLY FLOW AND MATERIALS (Attorney Docket No. L0858.70053US01), U.S. Provisional Application Serial No. 63/332,518, filed April 19, 2022, entitled PACKAGE ASSEMBLY FLOW AND MATERIALS (Attorney Docket No. L0858.70053US02), entitled METHOD FOR OPTICAL FIBER ATTACH ON U.S. Provisional Application Serial No. 63/327,717, filed Apr. 5, 2022, entitled "3D STACKED WAFER" (Attorney Docket No. L0858.70054US00), U.S. Provisional Application Serial No. 63/355,275, filed Jun. 24, 2022, entitled "WAFER-SCALE HETEROGENEOUS COMPUTING SYSTEMS" (Attorney Docket No. L0858.70057US00), U.S. Provisional Application Serial No. 63/397,609, filed Aug. 12, 2022, entitled "INCREASING THE YIELD OF FIBER ATTACH BY REDUNDANCY" (Attorney Docket No. L0858.70059US00), and "PHOTONIC PROGRAMMABLE INTERCONNECT This application claims the benefit of U.S. Provisional Application Serial No. 63/428,003, filed November 25, 2022, entitled "CONFIGURATIONS" (Attorney Docket No. L0858.70061US00), each of which is hereby incorporated herein by reference in its entirety.

Computer systems include random access memory (RAM) that stores data and machine code. RAMs are typically volatile memories, which means that the stored information is lost when power is removed. In modern implementations, the memories take the form of integrated circuits. Each integrated circuit contains a number of memory cells. To enable access to the stored data and machine code, the memories are arranged in electrical communication with the processors. Typically, these electrical communications are implemented as metal traces formed on the substrates on which the memories and processors are arranged.

Some embodiments relate to a photonic interposer comprising a plurality of photonic tiles that are instantiations of a template photonic tile, each of the plurality of photonic tiles comprising: a transceiver comprising a transmitter and a receiver; electrical connections coupled to the transceiver and configured to allow electrical communication between the transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in response to the photonic tile; an optical distribution network comprising a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides, and a plurality of programmable interconnects, each programmable interconnect configured to selectively position a bus waveguide of the first set of bus waveguides to optically communicate with a bus waveguide of the second set of bus waveguides, each programmable interconnect comprising a waveguide crossing and an active coupler.

In some embodiments, the transceiver includes a plurality of modulators coupled to a first bus waveguide of the first set of bus waveguides, the modulators being tuned at different wavelengths relative to one another; and a plurality of drop filters coupled to a second bus waveguide of the first set of bus waveguides, the modulators being tuned at different wavelengths relative to one another.

In some embodiments, the plurality of modulators are resonant modulators and the plurality of drop filters are resonant drop filters.

In some embodiments, the transmitter is configured to transmit data along a first bus waveguide of the first set of bus waveguides in the first direction or the second direction.

In some embodiments, each of the plurality of photonic tiles further includes a 2x2 coupler coupling the transceiver to a first bus waveguide of the first set of bus waveguides.

In some embodiments, the 2x2 coupler includes first, second, third and fourth terminals, the first terminal coupled to an output of the transmitter, the second terminal coupled to an input of the receiver, and the third and fourth terminals coupled to a first bus waveguide of the first set of bus waveguides.

In some embodiments, each of the plurality of photonic tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter, wherein the transmitter is coupled to the input of the interferometer, the first and second outputs of the interferometer are coupled to the resonant filter, and the resonant filter is coupled to a first bus waveguide of the first set of bus waveguides.

In some embodiments, each of the plurality of photonic tiles further comprises an interferometer having an output portion and first and second input portions, and a resonant filter, the resonant filter being coupled to a first bus waveguide of the first set of bus waveguides, the first and second input portions of the interferometer being coupled to the resonant filter, and a receiver being coupled to an output portion of the interferometer.

In some embodiments, the waveguide intersection comprises a first waveguide patterned in a first waveguide layer, a second waveguide patterned in a second waveguide layer, and a third waveguide layer patterned in a third waveguide layer, the second waveguide layer being between the first waveguide layer and the third waveguide layer, the first waveguide being evanescently coupled with the second waveguide, and the second waveguide being evanescently coupled with the third waveguide.

In some embodiments, the first waveguide layer is made of silicon and both the second and third waveguide layers are made of silicon nitride.

In some embodiments, the active coupler includes a first terminal coupled to the first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide crossover.

In some embodiments, the active coupler includes first and second Mach Zehnder interferometers (MZI), a first terminal corresponding to a first output of the first MZI, a second terminal corresponding to a second output of the first MZI, and a third terminal corresponding to an output of the second MZI.

In some embodiments, the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles.

Some embodiments relate to a photonic interposer, the photonic interposer comprising: a plurality of photonic tiles that are instantiations of a template photonic tile, the plurality of photonic tiles including first, second, third, and fourth photonic tiles, each of the plurality of photonic tiles including: a first transceiver; and electrical connections coupled to the first transceiver and configured to allow electrical communication between the first transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in response to the photonic tile; first and second bus waveguides intersecting the first and second photonic tiles, respectively; third and fourth bus waveguides intersecting the third and fourth photonic tiles, respectively; and first and second fibers - the first fiber, the first bus waveguide and the fourth bus waveguide are arranged to optically communicate a first transceiver of the first photonic tile with a first transceiver of the fourth photonic tile, and the second fiber, the second bus waveguide and the third bus waveguide are arranged to optically communicate a first transceiver of the second photonic tile with a first transceiver of the third photonic tile.

In some embodiments, each of the plurality of photonic tiles further includes a second transceiver, wherein the second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile.

In some embodiments, the second transceiver of the third photonic tile is in optical communication with the second transceiver of the fourth photonic tile.

In some embodiments, the photonic interposer further comprises a third fiber, wherein the third fiber, the first bus waveguide and the fourth bus waveguide are arranged to further optically communicate the first transceiver of the first photonic tile with the first transceiver of the fourth photonic tile.

In some embodiments, the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile form a closed loop.

In some embodiments, the photonic interposer further comprises a fourth fiber, wherein the fourth fiber, the second bus waveguide and the third bus waveguide are arranged to further optically communicate the first transceiver of the second photonic tile with the first transceiver of the third photonic tile.

In some embodiments, the second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile, and the first transceiver of the third photonic tile form a closed loop.

Some embodiments relate to a computing system, comprising: a photonic interposer including a plurality of photonic tiles, which are instantiations of a template photonic tile; first and second application-specific integrated circuits (ASICs) mounted on the photonic interposer, the first ASIC coupled with a first photonic tile of the plurality of photonic tiles and the second ASIC coupled with a second photonic tile of the plurality of photonic tiles; a data path positioning the first ASIC to communicate with the second ASIC, the data path comprising: a first die-to-die (D2D) interface including a plurality of wires, the first ASIC embedded therein; a first plurality of SerDes coupled to the plurality of wires; a plurality of optical modulators coupled to the plurality of SerDes and formed on the first photonic tile; a plurality of optical detectors coupled to the plurality of optical modulators and formed on the second photonic tile; a second plurality of SerDes coupled to the plurality of optical detectors; and a second D2D interface having the second ASIC embedded therein.

In some embodiments, a plurality of optical detectors are coupled to a plurality of optical modulators via waveguides formed on a photonic interposer.

In some embodiments, multiple optical detectors are coupled to multiple optical modulators via fibers.

In some embodiments, the first and second D2D interfaces include Advanced Interface Bus (AIB) interfaces.

In some embodiments, the first and second D2D interfaces include Universal Chiplet Interconnect Express (UCIe) interfaces.

In some embodiments, the data path spans a length greater than 2.5 cm from the first D2D interface to the second D2D interface.

Some embodiments relate to a method for manufacturing a photonic package, comprising: obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer; attaching an electronic chip to the first surface of the photonic interposer; encapsulating the electronic chip with an encapsulating material; disposing a protective material on the first surface of the photonic interposer to cover the grating coupler; after disposing the protective material, forming electronic connections on a second surface of the photonic interposer opposite the first surface; and after forming the electronic connections, removing the protective material from the first surface of the photonic interposer to expose the grating coupler to air.

In some embodiments, the method further comprises the step of cleaning the first surface of the photonic interposer after removing the protective material from the first surface of the photonic interposer.

In some embodiments, the method further comprises the step of attaching a fiber to the first surface of the photonic interposer after removing the protective material such that the fiber is optically coupled to the grating coupler when attached.

In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber is at a non-zero angle with respect to the first surface of the photonic interposer.

In some embodiments, the step of attaching an electronic chip to the first surface of the photonic interposer is performed after the step of disposing a protective material on the first surface of the photonic interposer.

In some embodiments, the protective material comprises a photo-imageable dielectric.

In some embodiments, the step of disposing a protective material on the first surface of the photonic interposer is performed after the step of attaching the electronic chip to the first surface of the photonic interposer.

In some embodiments, the step of disposing a protective material on the first surface of the photonic interposer is performed after the step of encapsulating the electronic chip with an encapsulating material.

In some embodiments, the protective material comprises a glass cover having a separable adhesive.

Some embodiments relate to a method for manufacturing a photonic package, comprising: obtaining a photonic interposer having a grating coupler formed on a first surface of the photonic interposer; attaching an electronic chip to the first surface of the photonic interposer; encapsulating the electronic chip with an encapsulating material, the encapsulating material leaving the grating coupler exposed to air; placing the photonic interposer on a carrier mount so as to cover the grating coupler; forming electronic connections on a second surface of the photonic interposer opposite the first surface after placing the photonic interposer on the carrier mount; and removing the carrier mount after forming the electronic connections.

In some embodiments, the step of encapsulating the electronic chip is performed after the step of attaching the electronic chip to the first surface of the photonic interposer.

In some embodiments, the method further comprises, after the step of removing the carrier mount, separating the photonic interposer into a plurality of systems, each comprising an electronic chip and a grating coupler.

In some embodiments, the method further comprises the step of attaching a fiber to the first surface of the photonic interposer after removing the protective material such that the fiber is optically coupled to the grating coupler when attached.

In some embodiments, when the fiber is optically coupled to the grating coupler, the fiber is at a non-zero angle with respect to the first surface of the photonic interposer.

Some embodiments relate to a photonic package, the photonic package including: a photonic interposer; a first electronic chip disposed on the photonic interposer; a circuit board having a first surface and a second surface opposite the first surface, the photonic interposer being coupled to the first surface of the circuit board; a voltage regulator module (VRM) coupled to the second surface of the circuit board; and a connector configured to provide an output voltage of the VRM to the first electronic chip, the connector crossing the circuit board and the photonic interposer.

In some embodiments, the photonic package further includes a substrate and a socket, wherein the photonic interposer is disposed on the substrate and the substrate is disposed on the socket.

In some embodiments, the connection further crosses the substrate and the socket.

In some embodiments, the photonic package further includes a power bus configured to provide an input voltage to the voltage regulator module.

In some embodiments, the voltage regulator module receives an input voltage from the power bus and regulates an output voltage to the first electronic chip.

In some embodiments, the first electronic chip is in contact with the photonic interposer.

In some embodiments, the photonic package further includes a cover covering the photonic interposer and a cooling plate covering the cover, the cover being in thermal contact with the first electronic chip.

Some embodiments relate to a photonic device, comprising: a photonic circuit; a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each of the chip-to-fiber couplers; an optical switch coupled between the plurality of optical channels and the optical circuit; and a controller, wherein the controller is configured to determine information indicative of a performance associated with each of the plurality of optical channels; identify a subset of the plurality of optical channels using the information indicative of the performance associated with each of the plurality of optical channels; and control the optical switch to selectively couple the subset of the plurality of optical channels to the photonic circuit.

In some embodiments, the plurality of optical channels further include a plurality of photodetectors coupled to respective waveguides, and determining information indicative of performance associated with each of the plurality of optical channels comprises determining an output of each of the plurality of photodetectors.

In some embodiments, multiple photodetectors are coupled to respective waveguides via tap couplers.

In some embodiments, determining information indicative of performance associated with each of the plurality of optical channels includes determining a bit error rate (BER) associated with each of the plurality of optical channels.

In some embodiments, the photonic circuit comprises a plurality of tiles patterned according to a template tile, each tile comprising: a transmitter; a receiver; a network of programmable optical connections; and electrical connections configured for vertical die-to-die connection with an electronic chip, the electrical connections being coupled to the transmitter, the receiver and the network of programmable optical connections.

In some embodiments, using the information to identify a subset of the plurality of optical channels comprises identifying a subset of the plurality of optical channels that exhibits the best performance among the optical channels.

In some embodiments, the chip-to-fiber couplers include edge couplers or grating couplers.

In some embodiments, the controller is further configured to control the photonic circuit to transmit data external to the photonic device using a subset of the plurality of optical channels selected by the optical switch.

Some embodiments relate to a method for transmitting data using a photonic device including an optical switch, a plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each of the chip-to-fiber couplers, the method comprising: determining information indicative of a performance associated with each of the plurality of optical channels; identifying a subset of the plurality of optical channels using the information indicative of the performance associated with each of the plurality of optical channels; controlling the optical switch to select the subset of the plurality of optical channels; and transmitting data external to the photonic device using the subset of the plurality of optical channels selected by the optical switch.

In some embodiments, the plurality of optical channels further include a plurality of photodetectors coupled to respective waveguides, and the step of determining information indicative of performance associated with each of the plurality of optical channels includes the step of determining an output of each of the plurality of photodetectors.

In some embodiments, the step of determining information indicative of performance associated with each of the plurality of optical channels comprises determining a bit error rate (BER) associated with each of the plurality of optical channels.

In some embodiments, the step of using the information to identify a subset of the plurality of optical channels comprises identifying a subset of the plurality of optical channels that exhibits the best performance among the optical channels.

Some embodiments relate to a photonic interposer, the photonic interposer comprising a plurality of photonic tiles, each photonic tile comprising: a transmitter; a receiver; a network of programmable optical connections; electrical connections configured for vertical die-to-die connection with an electronic chip, the electrical connections being coupled to the transmitter, the receiver and the network of programmable optical connections; a monitoring photodetector; and a controller, wherein the controller is configured to determine information indicative of performance of each of the plurality of photonic tiles using an output of each of the monitoring photodetectors; identify a defective tile among the plurality of tiles using the information indicative of performance of each of the plurality of photonic tiles; and functionally swap the defective tile with a redundant tile.

In some embodiments, functionally swapping a defective tile with a duplicate tile includes redirecting data directed to the defective tile to the duplicate tile.

In some embodiments, redirecting data includes programming a network of programmable photonic connections.

Some embodiments relate to a photonic interposer, comprising: a bus waveguide; a plurality of photonic transmitters coupled to the bus waveguide; a plurality of photonic receivers coupled to the bus waveguide; and a controller, wherein the controller is configured to lock a first photonic transmitter of the plurality of photonic transmitters to a first photonic receiver of the plurality of photonic receivers by: dithering a photonic component of the first photonic transmitter at a first frequency; and dithering a photonic component of the first photonic receiver at the first frequency.

In some embodiments, each of the plurality of photonic transmitters includes a resonant modulator, each of the plurality of photonic receivers includes a resonant drop filter coupled to the bus waveguide, and wherein dithering the photonic component of the first photonic transmitter includes dithering the resonant modulator of the first photonic transmitter, and wherein dithering the photonic component of the first photonic receiver includes dithering the resonant drop filter of the first photonic receiver.

In some embodiments, each of the plurality of photonic transmitters includes a resonant summing filter coupled to the bus waveguide, each of the plurality of photonic receivers includes a resonant drop filter coupled to the bus waveguide, and wherein dithering the photonic component of the first photonic transmitter comprises dithering the resonant summing filter of the first photonic transmitter, and wherein dithering the photonic component of the first photonic receiver comprises dithering the resonant drop filter of the first photonic receiver.

In some embodiments, the first frequency is between 1 KHz and 1000 KHz.

In some embodiments, the photonic interposer further comprises a plurality of photonic tiles that are instantiations of the template photonic tile, each of the plurality of photonic tiles comprising a photonic transmitter of the plurality of photonic transmitters and a photonic receiver of the plurality of photonic receivers, and wherein the bus waveguide traverses more than one of the photonic tiles.

Some embodiments relate to a photonic transmitter, comprising: a resonant modulator configured to modulate light received from a laser using input data; a Mach-Zehnder interferometer (MZI) coupled to the resonant modulator, the MZI having a first output and a second output; a resonant summing filter coupled to a bus waveguide; and a controller configured to transmit the modulated light along the bus waveguide in a first direction or a second direction by selectively coupling the first output or the second output of the MZI to the resonant summing filter.

In some embodiments, the photonic transmitter further comprises a heater thermally coupled to the resonant modulator and a first monitoring detector coupled to the first output of the MZI, wherein the controller is further configured to lock the resonant modulator to the laser by applying a first ramp signal to the heater; and maximizing an output produced by the first monitoring detector.

In some embodiments, selectively coupling the first output or the second output of the MZI to the resonant summing filter comprises: applying a second ramp signal to the MZI; and minimizing an output produced by the first monitoring detector.

In some embodiments, selectively coupling the first output or the second output of the MZI to the resonant summing filter further comprises applying a third ramp signal to the resonant summing filter; and minimizing an output produced by a second monitoring detector coupled to the second output of the MZI.

In some embodiments, the resonant addition filter comprises a second-order filter.

Some embodiments relate to a photonic interposer, comprising: first and second photonic tiles that are instantiations of a template photonic tile, each of the first and second photonic tiles including a transceiver and a receiver; an optical channel coupling a transmitter of the first photonic tile to a receiver of the second photonic tile; an encoder coupled to the transmitter of the first photonic tile and configured to perform an Xb/Yb encoding scheme; a decoder coupled to the receiver of the second photonic tile and configured to perform an Xb/Yb decoding scheme; and a clock recovery circuit configured to time the receiver of the second photonic tile using an output of the decoder.

In some embodiments, the photonic interposer further includes a first local oscillator coupled to the encoder and a second local oscillator coupled to the decoder.

In some embodiments, the photonic interposer further comprises an equalizer coupled to the receiver of the second photonic tile, the equalizer configured to perform a linear combination of outputs of the receiver of the second photonic tile.

In some embodiments, the equalizer is further configured to determine a characteristic of the optical channel during runtime, and to adjust a number of taps associated with the equalizer based on the characteristic of the optical channel determined by the equalizer.

In some embodiments, the equalizer is further configured to determine a characteristic of the optical channel during runtime and to adjust coefficients associated with the equalizer based on the characteristic of the optical channel determined by the equalizer.

Various aspects and embodiments of the present application will be described with reference to the drawings below. It should be understood that the drawings are not necessarily drawn to scale. Items appearing in multiple drawings are indicated by the same reference numerals in the drawings in which they appear.
FIG. 1a illustrates a computing system based on a photonic interposer, according to some embodiments.
FIG. 1ba illustrates a semiconductor wafer according to some embodiments.
FIG. 1bb illustrates a set of photomasks according to some embodiments.
FIG. 1bc illustrates an exemplary photomask for forming optical waveguides according to some embodiments.
FIG. 1bd illustrates the wafer of FIG. 1ba patterned according to the photomask set of FIG. 1bb, according to some embodiments.
FIG. 1be identifies photonic circuits formed on the patterned wafer of FIG. 1bd according to some embodiments.
FIG. 1ca illustrates an exemplary tile of the patterned wafer of FIG. 1be, according to some embodiments.
FIG. 1cb illustrates a group of tiles of the type illustrated in FIG. 1ca, according to some embodiments.
FIG. 1da illustrates a group of tiles sharing the same pattern of metal traces, according to some embodiments.
FIG. 1db illustrates a group of tiles that share the same pattern of metal traces and create a moisture barrier, according to some embodiments.
FIG. 2aa illustrates an architecture in which tiles of a photonic interposer are interconnected using static connectors, according to some embodiments.
FIG. 2ab illustrates another architecture in which tiles of a photonic interposer are interconnected using static connectors, according to some embodiments.
FIG. 2ac illustrates another architecture in which tiles of a photonic interposer are interconnected using static connectors, according to some embodiments.
FIG. 2ad illustrates an architecture in which tiles of a photonic interposer are interconnected using static connectors and fibers, according to some embodiments.
FIG. 2ae illustrates an architecture in which tiles of a photonic interposer are interconnected using static connectors and two fibers, according to some embodiments.
FIG. 2af illustrates an architecture in which tiles of a photonic interposer are interconnected using static connectors and three fibers, according to some embodiments.
FIG. 2AG illustrates another architecture in which tiles of a photonic interposer are interconnected using static connectors and two fibers, according to some embodiments.
FIG. 2A illustrates another architecture in which the tiles of the photonic interposer are interconnected using static connectors and four fibers, according to some embodiments.
FIG. 2ai illustrates another architecture in which tiles of a photonic interposer are interconnected using static connectors and four fibers, according to some embodiments.
FIG. 2BA illustrates an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments.
FIG. 2bb illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments.
FIG. 2bc illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments.
FIG. 2bd illustrates in additional detail a tile of the photonic interposer illustrated in FIG. 2bc, according to some embodiments.
FIG. 2be illustrates an example of a programmable photonic interconnect according to some embodiments.
FIG. 2bf illustrates an example of an active coupler according to some embodiments.
FIG. 2ca illustrates an architecture having bidirectional buses, according to some embodiments.
Figure 2cb illustrates another architecture having bidirectional buses, according to some embodiments.
FIG. 2da illustrates a photonic circuit for coupling a transmitter to a bidirectional bus, according to some embodiments.
FIG. 2db illustrates a photonic circuit for coupling a receiver to a bidirectional bus, according to some embodiments.
FIG. 2e illustrates an example of a waveguide intersection according to some embodiments.
FIG. 2fa illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments.
FIG. 2fb illustrates an example of a coupler used in the example of FIG. 2fa, according to some embodiments.
FIG. 2fc illustrates an architecture in which tiles of a photonic interposer are interconnected using programmable connections, according to some embodiments.
FIG. 2fd illustrates another architecture in which tiles of a photonic interposer are interconnected using programmable connectors and fibers, according to some embodiments.
FIG. 2ga illustrates an architecture utilizing wavelength-based tile identification according to some embodiments.
FIG. 2gb illustrates another architecture utilizing wavelength-based tile identification, according to some embodiments.
FIG. 2gc illustrates another architecture utilizing wavelength-based tile identification, according to some embodiments.
FIG. 2gd illustrates an example of a programmable optical loopback utilized in the example of FIG. 2gc, according to some embodiments.
FIG. 2ha illustrates an ASIC having an Advanced Interface Bus (AIB) interface according to some embodiments.
FIG. 2hb illustrates ASIC-to-ASIC connections utilizing an AIB interface and optical links according to some embodiments.
FIG. 2hc illustrates a photonic interposer hosting multiple ASICs communicating with each other via AIB interfaces, according to some embodiments.
FIG. 2a is a block diagram illustrating a pair of ASICs interconnected using a Bunch of Wires (WoR) interface, according to some embodiments.
FIG. 2ib is a block diagram illustrating another pair of ASICs interconnected using a Bunch of Wires (WoR) interface, according to some embodiments.
FIG. 2ja is a schematic diagram illustrating a computing network architecture utilizing photonic interposers, according to some embodiments.
FIG. 2jb is a schematic diagram illustrating another computing network architecture utilizing photonic interposers, according to some embodiments.
FIG. 2jc is a schematic diagram illustrating another computing network architecture utilizing photonic interposers, according to some embodiments.
FIG. 2jd is a schematic diagram illustrating another computing network architecture utilizing photonic interposers, according to some embodiments.
FIG. 3A is a block diagram illustrating a plesiochronous clock distribution scheme according to some embodiments.
FIG. 3b is a block diagram illustrating a mesochronous clock distribution scheme according to some embodiments.
FIG. 3ca is a block diagram illustrating a portion of a photonic interposer configured to perform equalization according to some embodiments.
FIG. 3cb is a block diagram illustrating an example of an adaptive equalizer according to some embodiments.
FIGS. 3dA to 3dC illustrate a sequence for tuning a transmitter according to some embodiments.
FIGS. 3ea and 3eb illustrate sequences for tuning a receiver according to some embodiments.
FIG. 3fa illustrates a technique for locking a receiver to a particular transmitter using dithering, according to some embodiments.
FIG. 3fb illustrates an optical channel supporting communication between multiple transmitter-receiver pairs according to some embodiments.
FIG. 4aa illustrates a photonic integrated circuit (PIC) having photonic circuits and multiple fiber attachments according to some embodiments.
FIG. 4ab is a block diagram illustrating a pair of PICs connected to each other using k fibers, some of which are provided solely for redundancy, according to some embodiments.
FIG. 4ac illustrates overall system throughput (in percent) of a system having 16 fiber attachment sites as a function of the number of attachments on each site, according to some embodiments.
FIG. 4b illustrates photonic interposers having multiple tiles, one of which is provided for redundancy, according to some embodiments.
FIG. 4c is a schematic diagram illustrating a power monitoring grid embedded in a photonic interposer according to some embodiments.
FIG. 5a is a schematic diagram illustrating a fiber coupled to a grating coupler according to some embodiments.
FIG. 5BA is a schematic diagram illustrating a wafer patterned with a plurality of photonic circuits according to some embodiments.
FIG. 5bb is a cross-sectional view of the wafer of FIG. 5ba, according to some embodiments.
FIG. 5ca is a side view of a photonic interposer according to some embodiments.
FIG. 5cb is a side view of a packaged photonic interposer according to some embodiments.
FIG. 5d is a flowchart illustrating a process for manufacturing a packaged photonic interposer according to some embodiments.
FIG. 5e is a flowchart illustrating another process for manufacturing a packaged photonic interposer according to some embodiments.
FIG. 5f is a flowchart illustrating another process for manufacturing a packaged photonic interposer according to some embodiments.
FIG. 5g is a schematic diagram illustrating a packaged photonic interposer including a voltage regulator module (VRM), according to some embodiments.
FIG. 5ha is a block diagram illustrating a VRM according to some embodiments.
FIG. 5HB is a schematic diagram illustrating a package in which power delivery to electronic chips is performed using VRMs, according to some embodiments.

I. outline

The inventors have recognized and understood several challenges that limit the scalability of modern digital computing. First, current designs are power-limited. The trend in modern computing is toward ever-increasing power consumption, which limits its scalability. In addition, the power-hungry nature of modern chips often results in hot spots with temperatures exceeding 100°C. High temperatures substantially limit the performance of computers. Second, modern computing architectures are bandwidth-limited. These architectures rely on a large number of memory chips to provide the hundreds of gigabytes or terabytes of capacity required by modern applications. Unfortunately, providing connectivity between multiple memory chips is difficult. The physical space available on a board or rack to accommodate the interconnects is limited, thus limiting the overall bandwidth. In addition, maintaining coherence and consistency across multiple memory chips (e.g., memory-to-memory and processor-to-memory) is difficult to achieve. Some architectures rely on Peripheral Component Interconnect (PCI), Compute Express Link (CXL), or Ethernet for inter-chip communication. However, these interfaces involve board-level or rack-level communications, which increase power usage and reduce bandwidth. Wafer-scale electrical communications have also been explored, but these approaches suffer from reliability issues and power inefficiencies.

The inventors have developed photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communications. Techniques, architectures, and processes that improve the performance of conventional multi-chip computers are described herein. Some embodiments provide photonic interposers that utilize "photonic modules" (also referred to herein as "photonic tiles" or simply "tiles"). Each tile contains programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some photonic interposers are arranged in one-dimensional schemes, such as blocks of 3x1 tiles, blocks of 5x1 tiles, blocks of 10x1 modules, 20x1 tiles, etc. Some interposers are arranged according to two-dimensional schemes, such as blocks of 3x3 tiles, blocks of 5x3 tiles, blocks of 5x5 tiles, blocks of 10x10 tiles, etc. More generally, the photonic interposers enable arbitrary blocks of NxM tiles (where N≥1 and M≥1), and arbitrary topologies, such as T-topologies, L-topologies, X-topologies, etc. Each tile can act as a node of the computing system. Each node may have one or more digital processor chips, one or more analog accelerators, one or more photonic accelerators, one or more memory chips, one or more networking chips, or other devices.

The photonic interposers described herein are fabricated in a manner that limits manufacturing cost. These platforms may rely on the use of a common set of photomasks (or at least one common photomask) to fabricate a number of tiles. This approach reduces cost in two ways. First, it reduces the additional costs that would otherwise be incurred when procuring multiple different sets of photomasks. Second, it enables the fabrication of the tiles using standard semiconductor foundries that require the same set of photomasks (or at least one photomask) to be used across the entire wafer. Designing the tiles to share at least one photomask enables the fabrication of many tiles on the same semiconductor wafer while utilizing standard, low-cost step-and-repeat manufacturing processes. Thus, in some embodiments, the tiles are instantiations (copies) of a common template tile that are stitched together in a 1D or 2D array. Some embodiments involve two template tiles, with each tile of the interposer being formed as an instantiation of either a first template tile or an instantiation of a second template tile. The tiles of the different templates may be alternated in a checkerboard fashion, for example, such that each tile of the first type is adjacent to tiles of the second type. Other arrangements are also possible.

In one example, the photonic interposer includes a 6 × 8 array of tiles, each tile being an instantiation of a reticle shot in a step-and-repeat manufacturing process. Each tile measures 24.8 mm × 32 mm and can support heterogeneous technologies (e.g., general-purpose processors, GPUs, DRAM/HBM stacks, or custom accelerators). With a waveguide pitch of 3 μm, the photonic interposer can easily support more than 10,000 optical links exiting each tile.

Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles with photonic links. The communicating tiles need not be adjacent. For example, the physical network can be programmed such that a tile located at the top-left corner can communicate directly with a tile at the bottom-right corner without retransmissions in the intermediate tiles. The network configuration time can be less than 10 μs, and communication between any two tiles (whether adjacent or not) can have a pass-through latency of less than 5 ns. The photonic interposers described herein provide the flexibility to form a variety of logical network topologies (e.g., from a low-radix, high-diameter mesh topology to a high-radix, low-diameter bus topology). For example, a 4x4 photonic interposer can map an all-to-all logical network with dedicated channels between each pair of tiles, providing up to 14.4 Tbps of bandwidth per channel (between any two tiles), for a total bisection bandwidth of up to 1851 Tbps. As another example, the photonic interposer can provide up to 231 Tbps of bandwidth per channel for a 2-ary, 4-fly butterfly network.

The photonic interposers described herein enable efficient heterogeneous architecture solutions, where chips designed from different technology nodes and performing different functions can be housed together on a single wafer, while providing high bandwidth and low latency between the chips via photonic links. Furthermore, the photonic interposers described herein can address thermal constraints associated with large and power-hungry chips, as the photonic interposer allows slicing of a large chip into a number of smaller chiplets. The photonic interposer can host these smaller chiplets and provide energy-efficient communication (similar to on-chip communication) between these smaller chiplets.

In a multi-chip system, each chip typically has access to a dedicated main memory. Typically, data is shared between the multiple chips using Remote Direct Memory Access (RDMA) (e.g., via the Last Level Cache (LLC) or L2). The photonic interposers described herein can aggregate the main memories of all chips to form a shared global main memory. This global shared main memory is accessible to all chips via photonic links. For example, an LLC can be sliced from each chip, and the LLCs can be moved next to the common global shared main memory, enabling low-latency and high-bandwidth communication between the L2 and LLC pairs of each chip. Keeping all LLCs together enables coherency management across the LLCs with low overhead. In some embodiments, the photonic interposers described herein may reduce the overhead of utilizing standard cache coherence protocols (e.g., IV, MESI, and MOESI) across chips, for example, by enabling efficient design of cache-coherent non-uniform memory access machines (NUMA) architectures.

In traditional architectures, processor chips communicate with memory chips (e.g., DRAM and HBM) using high-speed electrical links. However, the capacitance associated with electrical links limits the available bandwidth and results in power consumption. Recently, co-packaged optics (CPO) have emerged as a potential alternative to electrical links. CPO provides communication between the processor and memory using optical fiber-based communication links. Unfortunately, CPO is not a scalable solution in that the utilization of fiber links to support communication between a single processor chip and multiple memory chips and vice versa remains a challenge. In contrast, the photonic interposers described herein can host processor chips and memory chips on the same substrate, enabling high-bandwidth, dense communication. Leveraging their wafer-scale nature, photonic interposers can spread a processor across multiple tiles, providing sufficient area for the processor components and multiple memory controllers. This enables architectures that require multiple memory controllers on each processor chip, such as one processor chip to multiple memory chips and one memory chip to multiple processor chips.

The photonic interposers described herein can be used in a wide variety of applications, including machine learning, privacy preserving, and graph applications. The photonic interposers can be used to support communication between analog computing chips (e.g., photonics, memristors) and memory chips, communication between digital computing chips (e.g., processors, FPGAs, GPUs) and memory chips, networking chips, digital switch chips, and communication between digital computing chips and analog computing chips.

Current machine learning models involve massive amounts of data, often hundreds of GB to tens of TB. Therefore, large amounts of memory are required to store the models and data. Current technologies do not provide sufficient memory on a single chip. The photonic interposers described herein provide a solution for integrating multiple memory chips onto a single substrate while providing high-bandwidth, low-latency communication between the memory chips and the computing chips. The result is a reduction in execution time during both training and inference operations.

As data privacy becomes a primary concern when designing systems, various privacy-preserving computing approaches have been proposed. One of these approaches is homomorphic encryption (HE). Memory bandwidth and latency are major bottlenecks in HE-based applications. The photonic interposers described herein can alleviate this problem by providing access to memory with high bandwidth and low latency.

Graph applications involve irregular accesses to memory. Furthermore, graph applications involve small data granularity since they do not typically utilize all data present in a cache line. The photonic interposers described herein can overcome this bottleneck by enabling efficient access to memory over high-bandwidth, low-latency photonic links.

Architectures, systems, and processes involving tile-based photonic interposers are described herein.

II. Tile-type photonic interposers

FIG. 1A illustrates an exemplary computing system based on a photonic interposer having nine tiles arranged in a 3x3 topology, according to one example. The computing system (10) includes a photonic interposer (20) patterned with nine tiles (22). The photonic interposer supports a processor die (30) positioned in the middle of the photonic interposer (20) and eight memory nodes surrounding the processor die. Some of the memory nodes include a single memory chip (e.g., see memory die (32)). Other memory nodes include stacked memory including a plurality of vertically stacked memory dies (e.g., see stacked memory (34)). The dies are stacked on top of a wafer defining tiles. A die may communicate with a base tile electronically (e.g., using through-silicon vias, copper pillars, micro-bumps, ball-grid arrays, or other electrical interconnects) and/or optically (e.g., using grating couplers, prisms, lenses, or other optical couplers).

As described in more detail below, the tiles may be patterned with optical waveguides and optical distribution networks. The optical distribution network of a tile may optionally place a die of that particular node into optical communication with any other die of the computing system. For example, the optical distribution network of a tile located beneath a processor die (30) may be reconfigured as needed by the processor. At the start of a routine, the processor may need to access data stored in a first memory node. This read operation involves configuring each of the optical distribution networks to place the processor into optical communication with the first memory node. Later in the routine, the processor may need to write data to a second memory node. This write operation involves reconfiguring the optical distribution networks to place the processor into optical communication with the second memory node.

Manufacturing tiles in large quantities can be expensive. The photonic interposers described herein are fabricated in a way that limits manufacturing costs. These platforms rely on the use of (a subset of) common photomask sets to manufacture a large number of tiles. This approach reduces costs in two ways. First, it reduces the additional costs that would otherwise be incurred when procuring multiple different photomask sets. Second, it enables the manufacturing of tiles using standard semiconductor foundries, some of which require that the same photomask set (or at least one photomask) be used across the entire wafer. Designing tiles that share at least one photomask enables the manufacturing of many tiles on the same semiconductor wafer while utilizing standard, low-cost step-and-repeat manufacturing processes.

The tiles described herein can be fabricated using microfabrication techniques, including, for example, complementary metal oxide semiconductor (CMOS) microfabrication techniques. Accordingly, some embodiments relate to silicon photonics-based optical interposers. Some specific microfabrication techniques involve step-and-repeat approaches, whereby stepper machines are used to pattern a semiconductor wafer with multiple copies of a template layout (e.g., a reticle). Each tile resulting from the step-and-repeat approach can correspond to a reticle. Figures 1B-1 through 1B-1 illustrate microfabrication techniques for fabricating the tiles. Figures 1C-1 and 1C-2 illustrate examples of tiles patterned using such microfabrication techniques.

Referring first to FIG. 1ba, this drawing illustrates a semiconductor wafer (11). The wafer (11) may be made of any material. For example, the wafer (11) may be made of silicon (or may otherwise include silicon). In one example, the wafer (11) is a silicon-on-insulator (SOI) wafer. In another example, the wafer (11) is a bulk silicon wafer. The wafer (11) may have any size. For example, the diameter of the wafer (11) may be 150 mm, 300 nm, or 450 mm, among other possible values. However, not all wafers need to have a circular shape.

FIG. 1bb illustrates a set of photomasks that can be used to pattern a wafer (11) using photolithographic techniques. The photomask set (200) includes three photomasks (201, 202, and 203), although other sets may include more or fewer photomasks. Each photomask has a specific pattern of opaque and transparent areas. When the photomask is exposed to light, the opaque areas block the light, preventing it from illuminating the wafer, and the transparent areas allow the light to pass through. As a result, the pattern of the photomask is transferred to the wafer.

Each photomask can define a specific layer of the tile. A single photomask can be used to define the optical waveguides. When the wafer undergoes an etching process, only the exposed areas (or only the unexposed areas) are etched away, leaving the other areas unetched. The photomask can be patterned to form a network of optical waveguides when the wafer is exposed to light through the photomask. FIG. 1bc illustrates a portion of a photomask that can be used to form waveguides on the wafer (11). The lines of the photomask (201) represent opaque areas. The background of the photomask (201) is transparent. Exposing the photomask (201) to light such that the image of the photomask is projected onto the wafer (11) allows for the waveguides to be patterned into the shapes of the opaque areas. In this particular example, the pattern of the lines of the photomask produces a grid of waveguides.

Some tiles involve the use of different levels of optical waveguides. In some such embodiments, the photomask set (200) may include a dedicated photomask for each waveguide level. Another photomask may be used to define n-doped regions. When the wafer undergoes an ion implantation or dopant diffusion process, only the exposed regions (or only the unexposed regions) are doped, while other regions remain undoped. Another photomask may be used to define p-doped regions using a similar process. Some tiles involve the use of different doping concentrations. In some such embodiments, the photomask set (200) may include a dedicated photomask for each doping concentration. In other embodiments, the photomask set (200) may include photomasks used to define the deposition of semiconductor materials other than silicon, such as germanium and/or other materials of the periodic table, such as Group III or Group V. Different photomasks may be used to define the metal contacts. Different photomasks may be used to define the metal traces. Some tiles involve the use of different levels of metal traces. In some such embodiments, the photomask set (200) may include a dedicated photomask for each metal trace level.

In some embodiments, the wafer (11) is patterned in a step-and-repeat manner. As the wafer (11) is processed in a stepper machine, the pattern of the photomask is repeatedly exposed across the surface of the wafer in a grid. This process involves moving the wafer back and forth and left and right in steps under the lens of the stepper, exposing the photomask at each step. As a result, the wafer (11) is patterned with multiple copies of the pattern defined by the photomask. This operation may be repeated for each photomask (or at least some of the photomasks) in the set. Thus, in some embodiments, the tiles are copies of a common template tile that are stitched together in a 1D or 2D array. Other embodiments involve two template tiles, such that each tile of the interposer is formed as an instantiation of a first template tile or an instantiation of a second template tile. The tiles of the different templates may be alternated in a checkerboard fashion, for example, such that each tile of the first type is adjacent only to tiles of the second type. Other arrangements are also possible.

In the example of FIG. 1bd, the wafer (11) is patterned into a grid of tiles (22). The tiles may share a pattern of one or more photomasks of the set (200). For example, the tiles may share a pattern of the same waveguide photomask(s) and/or the same m trace photomask(s). In other embodiments, the tiles share a pattern of all photomasks of the set (200). For example, the tiles may share a same optical waveguide pattern, a same n-doping pattern, a same p-doping pattern, a same contact pattern, a same metal trace pattern, etc.

In some embodiments, the entire surface of the wafer (11) is patterned using the photomask set (200). However, not all embodiments are limited in this respect, as some portions of the wafer (11) may be patterned using the first photomask set, and other portions of the wafer (11) may be patterned using the second photomask set. The first photomask set may correspond to a first reticle, and the second photomask set may correspond to a second reticle. The first and second types of reticles may be alternated in a checkerboard fashion.

Once patterned, the wafer (11) may include a number of photonic circuits. In one example, the wafer of FIG. 1be has been marked to obtain six photonic circuits from the wafer (11). The photonic circuits are monolithically integrated with the wafer. The drawing identifies a 1x1 photonic circuit having only one tile (22), a 2x2 photonic circuit having four tiles (22), a 2x3 photonic circuit having six tiles (22), and three 3x3 photonic circuits each having nine tiles (22). Separation of the photonic circuits from the wafer involves dicing the wafer around the perimeter of the desired photonic circuits. In this regard, the photonic circuits described herein may be viewed as a wafer-level architecture. Once diced, each photonic circuit forms a standalone photonic interposer. One of the 3x3 photonic circuits of the wafer (11) can be used as a photonic interposer of the exemplary computing system of Fig. 1a (see photonic interposer (20)).

FIG. 1ca illustrates an exemplary tile (22). In this example, the tile (22) is shaped as a rectangle (but other shapes, such as a square or other polygon, are also possible). As such, the tile (22) is bounded by four boundaries (boundaries 1, 2, 3, and 4). Boundary 1 is opposite boundary 2, and boundary 3 is opposite boundary 4. Boundary 1 is adjacent to boundaries 3 and 4, and boundary 2 is also adjacent to boundaries 3 and 4. The tile (22) includes an optical distribution network (104) coupled to waveguides (111, 112, 113, and 114). The waveguide (111) optically couples the optical distribution network (104) to boundary 1. In this way, optical signals coupled from the optical distribution network (104) to the waveguide (111) can be propagated out of the tile by crossing the boundary (111). Similarly, the waveguide (112) optically couples the optical distribution network (104) to boundary 2, the waveguide (113) optically couples the optical distribution network (104) to boundary 3, and the waveguide (114) optically couples the optical distribution network (104) to boundary 4. In some embodiments, the boundaries of the tile are defined based on a photolithography shot (e.g., the boundaries are defined by the boundaries of the photomask(s) used to fabricate the tile). However, in other embodiments, a single photolithography shot may define more than one tile. For example, a photomask may be patterned with multiple parallel instances of a template tile. In some such embodiments, the boundaries of the tile are defined where adjacent instances of the template tile meet.

Although the example of FIG. 1ca illustrates waveguides coupling the optical distribution network to each of the boundaries, not all embodiments are arranged in this manner. In other embodiments, a tile (22) may include two of these four waveguides, such as waveguides (111 and 112) or waveguides (111 and 113). In still other embodiments, a tile (22) may include three of these four waveguides, such as waveguides (111, 112 and 113). The optical distribution network (104) includes photonic components (e.g., photonic switches) for routing optical signals within and outside of the tile (22). Additionally, the optical distribution network (104) may include transmitters (which provide an electro-optical interface with an electronic chip mounted on the tile) and receivers (which provide an optical-electrical interface with an electronic chip mounted on the tile). Examples of optical distribution networks are discussed in detail in the sections below.

In some embodiments, the tile may include multiple layers of photonic waveguides. Similar to how multiple layers of conductive traces increase the ability of an electronic circuit to route electrical signals, multiple layers of waveguides increase the ability of the tile to route optical signals. In one example, one layer includes a silicon waveguide and one or more additional layers include a silicon nitride waveguide. The choice of material for each waveguide layer may be determined by the wavelength of light to be routed by the waveguide. For example, the silicon and silicon nitride layers may be used to route infrared light in telecommunications bands having wavelengths of about 1.3 μm or 1.5 μm. In some examples, the multiple layers of waveguides may also include aluminum nitride waveguides, which may be used to route visible light down to UV wavelengths, or aluminum oxide waveguides, which may be used to route UV light. Each layer may be arranged in a configuration similar to that illustrated in FIG. 1ca, with an optical distribution network that routes signals between the waveguides of the layer.

The tile (22) may further include one or more out-of-plane couplers (not shown in FIG. 1ca). The out-of-plane couplers may be configured to emit light outside the xy-plane, for example, in a direction parallel to the z-axis or obliquely relative to the z-axis. The out-of-plane couplers may be further configured to capture light incident from outside the xy-plane. In some embodiments, the out-of-plane couplers enable optical communication between the tile (22) and a die positioned above and/or below the tile. The out-of-plane couplers may be implemented using any suitable optical components, including, for example, optical gratings, lenses, and prisms. In some embodiments, the optical distribution network may be configured such that the same out-of-plane coupler enables optical communication in both directions (from the optical distribution network (104) to the die and from the die to the optical distribution network (104)). In some embodiments, the out-of-plane couplers enable optical communication between the tile (22) and the fibers.

The optical distribution network (104) can selectively couple any components of the tile (22) to any other components of the tile (22), as discussed in detail in the sections below. For example, the optical distribution network (104) can enable the passage of light between waveguides (111) and waveguides (112), and/or between waveguides (111) and waveguides (113), and/or between waveguides (113) and waveguides (114). This can be accomplished by equipping the optical distribution network with controllable optical switches.

The tile (22) may further include electrical connectors (117), which may be arranged to provide electrical access to the tile from an electronic chip mounted on the tile. For example, the electrical connectors (117) may be in the form of contact pads that provide landing surfaces for bonds, bumps, vias, or other types of vertical chip-to-chip interconnections. The electrical connectors (117) may be coupled to transmitters, receivers, and switches of the optical distribution network, thereby providing electrical access of the electronic chip to such photonic components.

A photonic circuit may include a number of tiles connected together to collectively form an optical network. FIG. 1cb illustrates an exemplary 2x3 photonic circuit including six tiles (22). The photonic circuit is obtained by dicing a group of 2x3 tiles from a wafer (11) (see FIG. 1be). The tiles (22) are arranged such that the waveguide (111) of an optical module is aligned with the waveguide (112) of an optical module to the left of the optical module, the waveguide (112) of the optical module is aligned with the waveguide (111) of an optical module to the right of the optical module, the waveguide (113) of the optical module is aligned with the waveguide (114) of an optical module above the optical module, and the waveguide (114) of the optical module is aligned with the waveguide (113) of an optical module below the optical module. As a result, the optical modules form an optical network. The optical distribution networks (104) can route optical signals anywhere within or outside the network. For example, assume that the processor is mounted in a tile located at the northwest corner of the photonic circuit, and the memory is mounted in a tile located at the southeast corner of the photonic circuit. A read operation may involve reconfiguring the optical distribution networks (e.g., by controlling its optical switches) to place the processor into optical communication with the memory. For example, an optical communication path can be formed by 1) coupling a processor to an out-of-plane coupler of a tile on which the processor is mounted, 2) coupling the out-of-plane coupler of that tile to a waveguide (112) of the same tile, 3) coupling the waveguide (112) of that tile to a waveguide (111) of an adjacent tile (a middle-top tile), 4) coupling the waveguide (112) of the middle-top tile to a waveguide (111) of the next adjacent tile (the northeast corner of the photonic circuit), 5) coupling the waveguide (114) of the tile located at the northeast corner to the waveguide (113) of a tile on which a memory is mounted, and 6) coupling the waveguide (113) of the tile on which the memory is mounted to the out-of-plane coupler of the same tile.

As described above, the waveguides of adjacent tiles are optically coupled to each other, thus allowing passage of light from one tile to the next. In some embodiments, the ends of the waveguides may be physically connected (although, as discussed in more detail below, not all embodiments are limited to this particular arrangement). In other embodiments, there may be a gap between the waveguides. In this example, each waveguide has an end positioned a distance from the boundary. Thus, a gap is formed in the boundary region. Despite the gap, the waveguides of adjacent tiles are still optically coupled to each other. In this case, light emitted from the end of one waveguide actually reaches the end of the other waveguide by free space propagation.

In some embodiments, the tiles (22) may be patterned according to a common metal trace photomask. As a result, the tiles share the same pattern of metal traces. In some embodiments, the tiles (22) are patterned according to multiple common photomasks. As a result, multiple levels of metal traces share the same patterns across different tiles. Some of the metal traces may be used to conduct power across the photonic circuit. For example, some of the metal traces may be arranged to form a power grid, as discussed in more detail below. FIG. 1D illustrates a 2x3 photonic circuit where each tile (22) shares the same pattern of metal traces. For purposes of illustration, only the metal traces are depicted in this figure, but each tile further includes waveguides, one or more out-of-plane couplers, and an optical distribution network. In this example, there are two levels of metal traces. The metal traces of each level were fabricated using the same photomask across different tiles. The metal traces of metal trace level 1 run horizontally to electrically couple tiles that are horizontally adjacent to each other. The metal traces of metal trace level 2 run vertically to electrically couple tiles that are vertically adjacent to each other. Of course, other arrangements are possible. For example, in other embodiments, the metal traces of the same level may electrically couple a tile to all of its adjacent tiles.

The metal traces are arranged to carry electricity (e.g., signals and/or power) across the boundaries of the tiles. This can be accomplished by patterning the metal traces to be continuous across the boundaries of the tiles. In this example, the metal traces of level 1 are continuous across the vertical boundaries, and the metal traces of level 2 are continuous across the horizontal boundaries. The metal traces of different levels can be connected to each other using vias. In some embodiments, the tiles can share the same pattern of vias, i.e., the same via photomask can be used for each tile. In some embodiments, the tiles can have many more (tens to hundreds) of metal traces. Some of these metal traces can be arranged to be continuous across the tiles, but in some embodiments, most of the metal traces need not be patterned to be continuous across the modules. In one example, as illustrated in FIG. 1db , some of the metal traces can be patterned so as not to reach the ends of a group of tiles. This creates a moisture barrier between the dicing lanes and the metals. Additionally, these metal traces for carrying signals and/or power may be connected to through-silicon vias (TSVs) that connect to other chips positioned on top of the substrate and/or tile. In some embodiments, the metal traces may also be connected to transistor elements that may act as electronic switches, amplifiers, or TX/RX components.

III. Optical distribution networks

This section discusses architectures for interconnecting tiles of a photonic interposer in a manner that enables high bandwidth, low latency, and high resource utilization. The interconnects can be static or programmable.

A. Static connections

FIG. 2aa illustrates an example in which tiles of a photonic interposer are interconnected using static connectors. The example illustrates an interposer having four tiles arranged in one dimension. Each tile has a transmitter (TX) and a receiver (RX). The transmitter may include (or be coupled to) a light source and an optical modulator. The optical modulator may be configured to encode light with information provided by an electronic chip to which the tile is connected. Each receiver may include a photodetector that converts the signal provided by the transmitter into electricity. In this arrangement, waveguides couple the TX of a tile to the RX of a neighboring tile. This arrangement is denoted "one hop right" in that each waveguide reaches the RX immediately to the right of the TX.

Figure 2ab illustrates another example where the tiles of the photonic interposer are interconnected using static connectors. In this example, a waveguide couples the TX of a tile to the RX of a second neighboring tile. This arrangement is denoted "2 hop right" because each waveguide reaches the RX two steps to the right of the TX.

Figure 2ac illustrates another example where the tiles of a photonic interposer are interconnected using static connectors. In this example, a waveguide couples the TX of a tile to the RX of a third neighboring tile. This arrangement is denoted "3 hop right" because each waveguide reaches the RX three steps to the right of the TX.

The arrangements of FIGS. 2ad, 2ae, and 2af are similar to the arrangements of FIGS. 2aa, 2ab, and 2ac, respectively, with the addition of optical fibers to close the loop. The use of fibers increases flexibility in that information can flow in a closed loop manner. In FIG. 2ad, a fiber loops around the photonic interposer by coupling the TX of tile 4 with the RX of tile 1. In FIG. 2ae, a first fiber couples the TX of tile 4 with the RX of tile 2, and a second fiber couples the TX of tile 3 with the RX of tile 1. In FIG. 2af, a first fiber couples the TX of tile 4 with the RX of tile 3, a second fiber couples the TX of tile 3 with the RX of tile 2, and a third fiber couples the TX of tile 2 with the RX of tile 1.

The arrangements of FIGS. 2ad, 2ae and 2af present one drawback, namely that the TXs can transmit data only in one direction (in these examples to the right), while the RXs can receive only from the opposite direction (in these examples to the left). Therefore, such a network cannot maintain a bidirectional link between the two pairs of TX and RX modules. To implement a bidirectional link, a complementary network in which the waveguides are cascaded in opposite directions may be included. Examples are shown in FIGS. 2ag and 2ah (implementing a 1-hop and 2-hop scheme, respectively). In each arrangement, links are provided in both directions. TX1, TX2, TX3 and TX4 transmit data in one direction, while TX5, TX6, TX7 and TX8 transmit data in the opposite direction. Similarly, RX1, RX2, RX3 and RX4 receive data from one direction, and RX5, RX6, RX7 and RX8 receive data from the opposite direction. Tile 1 includes TX1, RX1, TX5 and RX5. Tile 2 includes TX2, RX2, TX6 and RX6. Tile 3 includes TX3, RX3, TX7 and RX7. Tile 4 includes TX4, RX4, TX8 and RX8.

However, these arrangements do not provide a bidirectional link between two pairs of adjacent TXs and RXs. In fact, it would be desirable for a first tile to transmit to a second tile, and for the second tile to transmit back to the first tile. To implement a bidirectional link between two pairs of TX and RX modules, it is proposed to implement a "swap" between the TX modules. This is illustrated in Fig. 2ai. The swap allows the TX modules to transmit to the RXs connected in the complementary loop. This example illustrates a two-hop dual-loop architecture with swapped TX modules. As a result, TX1 can transmit to RX7, and TX7 can transmit back to RX1, thus closing the bidirectional link.

B. Programmable Interfaces

The static connections described above do not allow for reconfiguration based on the needs of the network, and the network topology is fixed. However, allowing the network to dynamically reconfigure itself according to the needs of the user may be useful in certain applications. Therefore, some embodiments relate to programmable connections between tiles of a photonic interposer. The arrangement of FIG. 2BA is similar to the arrangement of FIG. 2AF in that both arrangements implement a 3-hop architecture. However, instead of having static connections, the arrangement of FIG. 2BA includes waveguide buses (four in this example, equal to the number of tiles). Each bus can couple any TX to any RX. Each transmitter and each receiver can selectively connect to the buses via switches. The connection points are identified as "nodes" in FIG. 2BA. When a transmitter activates a switch, the transmitter can transmit data using the bus waveguide. Similarly, when a receiver activates a switch, the receiver can listen for data from the bus waveguide. Three fibers are used to close the loop. In this example, the first bus connects TX1 to RX4, the second bus (with the first fiber) connects TX2 to RX1, the third bus (with the second fiber) connects TX3 to RX2, and the fourth bus (with the third fiber) connects TX4 to RX3. The network can be reconfigured using switches to change the number of hops from 3 to 1 or 2.

To implement a bidirectional link, a dual-loop architecture with swapped TXs (similar to the architecture of Fig. 2ai) can be utilized. This is illustrated in Fig. 2bb. However, unlike the architecture of Fig. 2ai, this architecture allows for dynamic reconfiguration of the network, including buses and nodes.

FIG. 2bc illustrates another photonic interposer having programmable interconnects, according to some embodiments. This example includes four tiles, but any number of tiles, whether arranged 1D or 2D, are possible. Each tile includes a transceiver (100) and programmable photonic interconnects (120). Each transceiver includes one or more instances of a transceiver cell (110). The transceiver cell illustrated in FIG. 2bc includes a laser (101), which may be mounted on the same package as the photonic interposer or may be external to the package. The laser (101) emits light at eight distinct wavelengths in this example, although a different number of wavelengths are possible. Thus, the architecture of FIG. 2bc can utilize wavelength division multiplexing (WDM) to increase data throughput. A TX bus (102) receives light from the laser and optically couples it to a number of modulators (104). Each modulator is coupled to a respective TX module, which may include a digital-to-analog converter and a modulator driver. A PLL times the operation of the TX modules. The TX modules, in turn, may be coupled to an electronic chip mounted on the photonic interposer corresponding to the tile. Each modulator (104), which is implemented as a ring (or disk) resonator in this example, is tuned to a different wavelength (λ0...λ7) of the emission of the laser (101). Thus, each modulator is configured to feed data to a different WDM channel. On the receiver side, the RX module is coupled to a drop filter (108), which is implemented as a ring (or disk) resonator in this example. Each drop filter is tuned to a different wavelength (λ0...λ7) of the emission of the laser (101). As a result, each drop filter captures data from the RX bus (106) on a particular WDM channel. The RX module may also be coupled to an electronic chip, which may include a photodetector, a trans-impedance amplifier, and an analog-to-digital converter.

The programmable photonic interconnects allow communication between the tiles (and consequently between the electronic chips mounted on the photonic interposer) in a programmable manner. The programmable interconnects form a grid of switchable intersections interconnected by waveguides, as illustrated in FIG. 2bd , the waveguides being arranged to form row buses and column buses. A tile may further include electrical connectors (117) that may be arranged to provide electrical access from an electronic chip mounted on the tile to the tile. For example, the electrical connectors (117) may be in the form of contact pads that provide landing surfaces for bonds, bumps, vias, or other types of vertical chip-to-chip interconnects. The electrical connectors (117) may be coupled to a transceiver (100).

In the example of FIG. 2bc, the programmable interconnects are programmed to allow communication between each tile and every other tile. In this drawing, a first optical path is formed between tile 1 and tile 4, a second optical path is formed between tile 1 and tile 3, and a third optical path is formed between tile 1 and tile 2. Each optical path can support multiple wavelengths.

FIG. 2be illustrates an exemplary implementation of a programmable photonic interconnect (120), according to some embodiments. The programmable photonic interconnect includes active couplers (126) coupled to each other via waveguides. As further illustrated in FIG. 2bf (which illustrates an example of an active coupler), each active coupler can provide a one-to-many waveguide coupling configuration. The active coupler can operate in both directions. When light is propagated from a single waveguide, the active coupler can select one of the multiple waveguides for propagation of the light, thereby performing a switching operation. A possible implementation of the active coupler (126) involves a cascaded Mach-Zehnder interferometer (MZI), as further illustrated in FIG. 2bf (see also MZIs 127 and 128).

Referring again to FIG. 2be, the central waveguides of the active couplers are coupled to each other in such a way as to form a waveguide crossover (127). The waveguide crossovers (127) present challenges from a system perspective in that they introduce insertion loss and crosstalk. Below is an example of a waveguide crossover developed by the inventors that produces low insertion loss and low crosstalk.

The waveguide buses illustrated in FIG. 2bd may be bidirectional in some embodiments. In some such embodiments, instead of having a dedicated bus for transmitting and a dedicated bus for receiving, the tiles may transmit and receive using the same bus waveguide. Additionally, or alternatively, the transmitter may determine the direction of the bus in which to transmit data, and the receiver may determine the direction of the bus in which to receive data. An example of such an implementation is illustrated in FIG. 2ca according to some embodiments. On the TX side, the tile includes couplers (131) arranged to form an optical tree. The couplers may be controllable (similar to the active couplers of FIG. 2bf). Each output branch of the tree is coupled to the bus via couplers (133, 134, and 135). Coupler (133) selects one input and one output. Selecting the waveguide provided by the TX as the input allows the coupler (133) to place the tile in a transmit mode. Selecting one of the outputs allows the TX to communicate from right to left or left to right along the bus, thus allowing communication in two directions. The couplers (134 and 135) determine whether the bus is in add/drop mode (add for transmit or drop for receive) or thru mode (bypassing tile 1).

On the RX side, the tile also includes couplers (132) arranged to form an optical tree. Each output branch of the tree is coupled to the bus via couplers (133, 134 and 135), which allow selection of right-to-left or left-to-right direction during transmission. In this example, couplers (134 and 135) are implemented as 1x2 couplers and coupler (133) is implemented as a 2x2 coupler, although other configurations are also possible. The architecture of Fig. 2cb is similar to that of Fig. 2ca in that both architectures utilize coupler (133). However, the architecture of Fig. 2cb replaces couplers (133 and 135) with 2x2 couplers (137).

Figures 2da and 2db illustrate additional schemes allowing bidirectional propagation along the bus. On the TX side (Figure 2da), the TX is coupled to the MZI, which in turn is coupled to a resonant summing filter. Depending on which output of the MZI is selected, either the clockwise mode or the counterclockwise mode of the resonant filter is excited. As a result, transmission over the bus occurs from left to right or from right to left. On the RX side (Figure 2db), the RX is coupled to the MZI, which in turn is coupled to a resonant dropping filter. Depending on which input of the MZI is selected, either the clockwise mode or the counterclockwise mode of the resonant filter is selected. As a result, the RX selects a left-right or a right-left bus mode.

FIG. 2e illustrates an example of a waveguide crossover that may be utilized in some embodiments (e.g., in FIG. 2be). This implementation involves three waveguide layers (140, 141, and 142). The waveguide layers may be made of, for example, silicon or silicon nitride. In one example, the waveguide layer (140) is made of silicon and the waveguide layers (141 and 142) are made of silicon nitride. The waveguide crossover is designed to couple mode A from layer (140) to layer (141), then to layer (142), then from layer (142) back to layer (141), and back to layer (140). The tapers may be utilized to expand and contract mode A in the vertical direction. By pushing mode A out of the plane of layer (140), the overlap between mode A and mode B is limited, thus reducing crosstalk. The inventors have found that having a 3-layer scheme as illustrated herein is advantageous in that it can provide the same low insertion loss performance as compared to 2-layer schemes, but allows for negligible crosstalk between the layers (140 and 142).

Accordingly, some embodiments are directed to a photonic interposer including a plurality of photonic tiles (e.g., tiles 1-4 of FIG. 2bc) that are instantiations of a template photonic tile. Each of the plurality of photonic tiles includes a transceiver (100) including a transmitter and a receiver. Electrical connections (117) coupled to the transceiver are configured to allow electrical communication between the transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile (e.g., as illustrated in FIG. 1a). An optical distribution network includes a first set of bus waveguides (e.g., row busses of FIG. 2bd ), a second set of bus waveguides (e.g., column busses of FIG. 2bd ) optically coupled to the transceiver, and a plurality of programmable interconnects (120). Each programmable interconnect is configured to selectively place a bus waveguide of the first set of bus waveguides into optical communication with a bus waveguide of the second set of bus waveguides. Each programmable interconnect includes a waveguide crossover (127) and an active coupler (126).

In some embodiments, the transceiver includes a plurality of modulators (104) coupled to a first bus waveguide of the first set of bus waveguides, each of which is tuned at different wavelengths relative to the other, as illustrated in FIG. 2bc, for example. Additionally, a plurality of drop filters (108) coupled to a second bus waveguide of the first set of bus waveguides are tuned at different wavelengths relative to the other. In some embodiments, the plurality of modulators are resonant modulators and the plurality of drop filters are resonant drop filters.

In some embodiments, the transmitter is configured to transmit data along a first bus waveguide of the first set of bus waveguides in the first direction or the second direction, as illustrated in FIGS. 2ca, 2cb, and 2dA, for example.

In some embodiments, each of the plurality of photonic tiles further includes a 2x2 coupler (133) that couples the transceiver to a first bus waveguide of the first set of bus waveguides. The 2x2 coupler can include first, second, third, and fourth terminals. The first terminal is coupled to an output of the transmitter. The second terminal is coupled to an input of the receiver. The third and fourth terminals are coupled to the first bus waveguide of the first set of bus waveguides.

In some embodiments, each of the plurality of photonic tiles further comprises an interferometer (e.g., an MZI of FIG. 2dA) having an input and first and second outputs, and a resonant filter. A transmitter is coupled to an input of the interferometer, and the first and second outputs of the interferometer are coupled to the resonant filter. The resonant filter is coupled to a first bus waveguide of the first set of bus waveguides. Additionally, in some embodiments, each of the plurality of photonic tiles further comprises an interferometer (e.g., an MZI of FIG. 2dB) having an output and first and second inputs, and a resonant filter. The resonant filter is coupled to a first bus waveguide of the first set of bus waveguides. The first and second inputs of the interferometer are coupled to the resonant filter. A receiver is coupled to an output of the interferometer.

In some embodiments, the waveguide intersection includes a first waveguide patterned in a first waveguide layer (140), a second waveguide patterned in a second waveguide layer (141), and a third waveguide layer patterned in a third waveguide layer (142). The second waveguide layer is between the first and third waveguide layers, and the first waveguide is dissipatively coupled to the second waveguide and the second waveguide is dissipatively coupled to the third waveguide. In some embodiments, the first waveguide layer is made of silicon and both the second and third waveguide layers are made of silicon nitride.

In some embodiments, the active coupler includes a first terminal coupled to the first additional active coupler, a second terminal coupled to the first additional active coupler, and a third terminal coupled to the waveguide crossover, as illustrated in FIG. 2be, for example.

In some embodiments, the active coupler includes first and second Mach-Zehnder interferometers (MZIs), as illustrated in FIG. 2bf, for example. A first terminal corresponds to a first output of the first MZI (128), a second terminal corresponds to a second output of the first MZI, and a third terminal corresponds to an output of the second MZI (127).

In some embodiments, the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles (e.g., tiles 1-4 of FIG. 2bc).

FIG. 2fa illustrates another interconnect architecture. The advantage of this architecture over the architecture of FIG. 2bc is that waveguide crossings are omitted. The disadvantage is underutilization of the transceivers. In this architecture, each tile includes a number of transceivers (100). Each transceiver is coupled to one of the buses (151, 152, 153, 154, and 155). These buses cross the boundaries between the tiles and do not intersect each other. In this figure, bus (151) allows communication between tile 1 and tile 2, and between tile 3 and tile 4. Bus (152) allows communication between tile 1 and tile 3. Bus (153) allows communication between tile 2 and tile 4. Bus (154) allows communication between tile 1 and tile 4. Bus (155) allows communication between tile 2 and tile 3. The transceiver-to-bus interfaces can be programmed according to the needs of the network. Couplers (156) are used to selectively couple a transceiver to the bus or decouple a transceiver from the bus. An exemplary implementation of a coupler (156) illustrated in FIG. 2fb involves MZIs arranged in a closed loop configuration. The MZIs allow for two-way communication, either during transmission or reception.

The utility of the architecture of FIG. 2fa can be increased by including additional buses. For each row of transceivers spanning tiles 1 through 4, there are two buses (e.g., 151A and 151B) to which the transceivers are switchably coupled. One bus can support left-to-right communication and the other bus can support right-to-left communication, thereby closing the loop. However, in some embodiments, both buses can support communication in the same direction. In this figure, bus (151A) places tile 1 in communication with tile 4, bus (151B) places tile 1 in communication with tile 2, places tile 2 in communication with tile 3, and places tile 3 in communication with tile 4. For example, couplers (156) can be implemented as shown in FIG. 2fb. One drawback of this configuration is that the links between tiles at opposite ends of a row (e.g., tile 1 and tile 4) are longer than the other links, resulting in greater optical losses.

The architecture of FIG. 2fd addresses this problem by using optical fibers to connect the remote tiles. In this architecture, the tiles are arranged in two blocks of 1x2 tiles. A first block includes tiles 1 and 2, and a second block includes tiles 3 and 4. Each tile includes a number of transceivers (100). Tiles 1 and 2 communicate with each other using buses (161A and 161B). Having two buses allows for bidirectional communication. For example, the TX of tile 1 can transmit data to the RX of tile 2 using bus (161A), and the TX of tile 2 can transmit data to the RX of tile 1 using bus (161B). Similarly, tiles 3 and 4 communicate with each other using buses (164A and 164B). In one example, the TX of tile 3 may transmit data to the RX of tile 4 using bus (164A), and the TX of tile 4 may transmit data to the RX of tile 3 using bus (164B). As such, buses (161A, 161B, 164A, and 164B) may be viewed as intra-block buses. Alternatively, buses (162A, 162B, 163A, and 164B) may be viewed as inter-block buses. Bus (162A) is connected to bus (163B) via fibers (166A and 168A). Similarly, bus (162B) is connected to bus (163A) via fibers (166B and 168B).

Compared to the architectures of FIG. 2fc, the architecture of FIG. 2fd shortens the on-chip path connecting tile 1 and tile 4. Part of the on-chip path connecting tile 1 and tile 4 is replaced with fibers. Since the loss introduced by the fiber can be lower than the loss introduced by the integrated waveguide, the overall loss is reduced.

Accordingly, some embodiments are directed to a photonic interposer including a plurality of photonic tiles (e.g., tiles 1-4 of FIG. 2fd ) that are instantiations of a template photonic tile. Each of the plurality of photonic tiles includes a first transceiver (100). Electrical connections (not shown in FIG. 2fd ) coupled to the first transceiver are configured to allow electrical communication between the first transceiver and the electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile, as illustrated in FIG. 1a . The first and second bus waveguides (162A and 162B) traverse the first and second photonic tiles, respectively. And the third and fourth bus waveguides (163A and 163B) traverse the third and fourth photonic tiles, respectively. The first fiber (166A), the first bus waveguide (162A), and the fourth bus waveguide (163B) are arranged to optically communicate the first transceiver of the first photonic tile with the first transceiver of the fourth photonic tile. The second fiber (166B), the second bus waveguide (162B), and the third bus waveguide (163A) are arranged to optically communicate the first transceiver of the second photonic tile with the first transceiver of the third photonic tile.

In some embodiments, each of the plurality of photonic tiles further includes a second transceiver. The second transceiver of the first photonic tile can be in optical communication with the second transceiver of the second photonic tile (e.g., via buses 161A and/or 161B). Similarly, the second transceiver of the third photonic tile can be in optical communication with the second transceiver of the fourth photonic tile (e.g., via buses 164A and/or 164B).

In some embodiments, the interposer further includes a third fiber (168A). The third fiber (168A), the first bus waveguide (162A), and the fourth bus waveguide (163B) are arranged to further optically communicate a first transceiver of the first photonic tile with a first transceiver of the fourth photonic tile. The first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile, and the first transceiver of the fourth photonic tile can form a closed loop. The interposer can further include a fourth fiber (168B). The fourth fiber (168B), the second bus waveguide (162B), and the third bus waveguide (163A) are arranged to further optically communicate a first transceiver of the second photonic tile with a first transceiver of the third photonic tile. The second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile and the first transceiver of the third photonic tile can also form a closed loop.

C. Wavelength-based tile identification

The architectures discussed in connection with FIGS. 2aa through 2fd utilize WDM to increase the aggregate bandwidth of each tile-to-tile optical link. In other embodiments, wavelengths may be used to uniquely identify each tile. In a 4-tile architecture, for example, wavelength λ0 may uniquely identify tile 1, wavelength λ1 may uniquely identify tile 2, wavelength λ2 may uniquely identify tile 3, and wavelength λ3 may uniquely identify tile 4. Thus, a receiver can identify the source of data collected from the bus simply by determining the wavelength that supports the data. An example is illustrated in FIG. 2ga. This architecture includes four tiles. A first set of transceivers (100) are connected by a bus (171), a second set of transceivers (100) are connected by a bus (172), and a third set of transceivers (100) are connected by a bus (173). Each transceiver is labeled with a pair of numbers (x and y). The first number (x) identifies the transmitting wavelength of the transmitter of the transceiver. The second number (2) identifies the wavelength that the receiver of the transceiver is configured to read. It should be noted that all x numbers of the transceivers in a particular tile are the same. This allows the system to uniquely identify the transmitters by wavelength.

In the example of Figure 2gb, each tile in a row has its own transmit wavelength. However, the wavelengths are reused across different rows. A first row includes rows 1-4, a second row includes tiles 5-8, and so on. In this example, wavelength λ0 may uniquely identify tile 1 and tile 5, wavelength λ1 may uniquely identify tile 2 and tile 6, wavelength λ2 may uniquely identify tile 3 and tile 7, and wavelength λ3 may uniquely identify tile 4 and tile 8. A bus set (181) (comprising three buses) allows communication between the tiles in the first row (tiles 1-4). A bus set (183) (comprising three buses) allows communication between the tiles in the second row (tiles 5-8). A set of buses (182) (comprising eight buses) allows communication between each tile in the first row and each tile in the second row. Each tile includes transmitters and receivers, represented herein in the form of a resonant modulator (TX) and a resonant drop filter (RX). The wavelengths in parentheses represent the transmit wavelength (for the TX) and the drop wavelength of the resonant drop filter (for the RX).

The architecture of FIG. 2gc is similar to that of FIG. 2ga, but it further includes programmable optical loopbacks (190) that allow unidirectional traffic lanes. The exemplary programmable optical loopback illustrated in FIG. 2gd is implemented using MZIs.

IV. Die-to-die (D2D) interfaces

The photonic interposers described herein can be used to interconnect application-specific integrated circuits (ASICs) in ways that would otherwise be impractical (e.g., too expensive or energy inefficient) using conventional interfaces. Recently, new die-to-die (D2D) interface standards have emerged that allow chiplets from different sources to communicate with each other. D2D interfaces utilize very short channels to connect two dies within a common package to achieve power efficiency and very high bandwidth efficiency beyond what conventional chip-to-chip interfaces can achieve. A D2D interface can be viewed as being divided into a physical layer (PHY), a link layer, and a transaction layer. The PHY layer can be implemented using high-speed SerDes architectures for parallel-to-serial and serial-to-parallel data conversion. The primary role of the SerDes is to minimize the number of I/O interconnects.

Now, as electronic interposers and silicon bridges are moving into mainstream products, the industry is placing a lot of emphasis on advanced packaging. Examples of D2D interfaces include, among others, the Advanced Interface Bus (AIB), the Universal Chiplet Interconnect Express (UCIe), and the Low-voltage-In-Package-INterCONnect (LIPINCON). Bunch of Wires (BoW) is a relatively new D2D interface designed to standardize some of the interconnects that are expected to become more important in next-generation chips. These interfaces are designed for high-bandwidth communications between electronic ASICs that are located in relatively close proximity, for example, a few millimeters apart.

The inventors have recognized and appreciated that the relatively close proximity established by D2D interfaces poses practical limitations on the types of computing architectures achievable using such interfaces. The maximum die-to-die distance established by these interfaces (a few millimeters in wet case) ensures high bandwidth and reliability given the constraints of the electrical interconnect. The photonic interposers described herein can extend the applicability of conventional D2D interfaces to ASIC-to-ASIC distances greater than possible with conventional electronic interposers. In one example, the use of photonic interposers can enable AIB-based communications between a pair of ASICs separated by, for example, greater than 1 cm, greater than 1.5 cm, greater than 2.5 cm, greater than 3 cm, greater than 5 cm, or greater than 10 cm. Similarly, the use of photonic interposers can enable UCIe-based communications between a pair of ASICs separated by, for example, more than 1 cm, more than 1.5 cm, more than 2.5 cm, more than 3 cm, more than 5 cm, or more than 10 cm. A SerDes interface connected to a photonic interposer can multiplex wires into a single photonic link using a single photonic channel, whether a spatial channel (waveguide or fiber), a wavelength channel, or a polarization channel. In some embodiments, the photonic channel can support 56 Gbps using non-return to zero (NRZ) modulation, and up to 112 Gbps using PAM4 modulation.

FIG. 2ha illustrates an ASIC having an AIB interface. More specifically, the ASIC includes a "northwest" AIB unit, a "southwest" AIB unit, a "southeast" AIB unit, and a "northeast" AIB unit. Each AIB includes 24 channels (though other numbers of channels are possible). FIG. 2hb illustrates how an AIB interface may enable connectivity between two ASICs (ASIC 0 and ASIC 1) using a photonic interposer of the types described herein. The transmitter port of ASIC 0 supports 128 wires, each supporting 1.5 Gbps to 2.5 Gbps (e.g., 2 Gbps). With an 8:1 SerDes, signals from the 8 wires may be multiplexed to generate 12 Gbps to 20 Gbps (e.g., 16 Gbps). The SerDes may be formed directly on the photonic interposer in some embodiments (e.g., using transistors within an SOI wafer hosting the photonic interposer). Modulators formed within the photonic interposer convert data acquired from the SerDes into optical signals to be transmitted using waveguides formed on the interposer or fibers. At the receiver side, photodetectors receive the signals, the SerDes demultiplexes, and wires provide data to ASIC 1 via the AIB receive port.

FIG. 2hc illustrates a photonic interposer (20) hosting 16 ASICs having AIB interfaces. Each ASIC may be mounted on a respective tile of the photonic interposer, for example, in an arrangement similar to that illustrated in FIG. 1a. An external laser module couples light into the interposer using grating couplers, although edge coupling is also possible. Waveguides formed in the interposer and/or fibers support communication between the ASICs via the AIB interfaces. Any of the static or programmable photonic interconnects described herein may be utilized to support communication between the ASICs. It should be noted that the AIB interfaces discussed with respect to FIGS. 2hc through 2hc may be replaced with other D2D interfaces, including, for example, UCIe.

FIG. 2a illustrates a pair of ASICs (ASIC 0 and ASIC 1) communicating with respective tiles (tile 0 and tile 1) of the interposer. In this example, BoW interfaces are utilized. Communication occurs over waveguides formed in the photonic interposer, although in other embodiments fibers may be utilized. In some embodiments, to reduce the number of waveguides crossing tile boundaries, signals may be multiplexed onto a single waveguide or fiber using WDM and/or polarization diversity. In the example of FIG. 2b, one polarization is utilized in one transmit direction and the other polarization is utilized for the reverse direction.

The photonic interposers described herein enable several types of computer architectures, including those illustrated in FIGS. 2ja, 2jb, 2jc, and 2jd. In the example of FIG. 2ja, the photonic interposer (20) hosts sixteen ASICs. Of these, only one (ASIC 0) interfaces with components external to the interposer (20) using optical fibers. The ASICs communicate with each other using any one of the interconnects described herein. In the example of FIG. 2jb, the fibers are used to close the loop. As a result, ring network architectures can be formed. This architecture is particularly well suited for applications involving pipelined operations utilizing multiple ASICs. In the example of FIG. 2jc, each ASIC communicates with its neighbors, and additional links are formed to allow communication between ASICs located at opposite ends of a column or row. This allows for 2D hypertoroid architectures. Finally, in the example of Fig. 2jd, every ASIC communicates with every other ASIC, forming an all-to-all architecture. This architecture is particularly suitable for smaller layer sizes, parallel batch processing, sequential graph processing, and HPC/AI clusters where multi-tenancy is required.

The inventors have realized that a greater number of hops (in terms of photonic tiles) will require longer photonic paths and/or more photonic switches/crossovers. This can result in more optical losses and crosstalk. The topology of Fig. 2ja, which is an all-to-all topology, represents a baseline topology. The topologies in Figs. 2jb-2jd are achieved by reducing the number of hops a particular optical link takes with respect to the topology of Fig. 2ja. Thus, the optical losses of the links in the topologies of Figs. 2jb-2jd are lower than those of the links illustrated in Fig. 2ja. For efficiency reasons, the laser power/current can be lowered to reduce the amount of redundant light utilized for each optical link.

Additional topologies are also possible if the number of hops in a particular TX/RX link is higher in the reconfigured topology than in the baseline topology. In this case, that particular optical link may require higher laser power (to compensate for higher loss or crosstalk) to achieve the same performance (e.g., baud and BER). The higher laser power may be achieved without increasing the laser power of the overall system, for example, by routing additional power to the link from those optical links with a reduced number of hops. Alternatively, additional laser modules or increasing the power of the laser modules may be required. Another solution is to use a different communication protocol that is slower or has fewer bits (e.g., going from PAM-4 to NRZ, or from QAM-16 to QAM-4) or that accommodates higher bit/symbol error rates, which can be improved by the use of error correction codes.

VI. Clock distribution

The inventors have recognized and appreciated that it is impractical to synchronize an entire photonic interposer and the electronic chips connected to it using a single global clock. This is in part because global clock distribution schemes are complex and require significant power to operate.

In some embodiments, clock and data recovery (CDR) can be performed by generating a local clock within each tile. CDR recovery can be implemented for each TX/RX pair, with the optical communication channel crossing boundaries between tiles. CDR can be performed using plesiochronous schemes in some embodiments. Alternatively, CDR can be performed using mesochronous schemes in some embodiments. Both schemes are discussed below.

A. Plesiochronus schemes

In plesiocronus schemes, the clock can be transmitted within the same optical channel that the data is transmitted. Thus, the same TX circuitry and the same RX circuitry are used to transmit/receive both data and clock. This can be done by operating at a slightly higher bandwidth than would otherwise be required to transmit data alone, to account for CDR overhead. Several protocols may be used, including the 8b/10b protocol, the 64b/66b protocol, the 128b/130b protocol, or the 256b/257b protocol. Typically, the Xb/Yb protocol converts X bits of data into a string of Y bits to achieve DC balance to provide sufficient state transitions for clock recovery and data alignment. Examples of DC-balanced data strings are those where the difference between the counts of 1s and 0s within a string of at least 20 bits may not exceed 2, and/or the number of consecutive 1s or 0s (within a row) may be 5 or less. DC-balancing can be implemented using linear feedback shift registers in some embodiments. Clock recovery implemented according to these schemes relies on transitions of data (e.g., rising edges and/or falling edges).

The plesiochronous schemes described herein rely on separate local oscillators (LOs), one LO on the transmit side of the channel and one LO on the receive side of the channel. Having separate LOs can introduce clock drift. In some embodiments, clock drift can be compensated for using resilient first-in, first-out (FIFO) schemes, where the FIFO depth is established by the length of the packet in parts per million (PPM).

FIG. 3A is a block diagram illustrating a plesiochronous clock distribution scheme according to some embodiments. In this example, the data path involves communication from a photonic transmitter (TX) (301) located in tile 1 to a photonic receiver (RX) (203) located in tile 2. Routing between the tiles may be performed using any of the architectures discussed above. The optical communication channel (303) supports data using the Xb/Yb protocol (whether implemented as a bus waveguide of the photonic interposer or as a fiber). The system includes a local oscillator (LO) (310) on the RX side and an LO (316) on the RX side. Each LO may include a dedicated crystal, or alternatively, the LOs may be supplied by a common crystal. Optionally, a PLL may be utilized to achieve a higher clock frequency by multiplying the frequency of the LO (310) by a predefined factor. The system further includes an Xb/Yb encoder (312) on the transmitting side and a corresponding Xb/Yb decoder (314) on the receiving side.

B. Mesochronous schemes

In mesochronous schemes, the clock is transmitted using a separate optical channel for the data. Having a separate optical channel can involve a separate propagation medium (e.g., a separate waveguide or fiber), or the same propagation medium but with a separate wavelength or polarization.

FIG. 3B is a block diagram illustrating a mesochronous clock distribution scheme according to some embodiments. As in the previous example, the data path involves communication from a photonic transmitter (TX) (301) located in tile 1 to a photonic receiver (RX) (203) located in tile 2. However, the clock is transmitted using a channel (352), and the data is transmitted using channels (350). The channels may represent separate wavelengths or separate polarizations in a physical propagation medium, or a common medium. In this scheme, the transmitter includes an LO (310), but the receiver does not have a separate LO. Instead, a PLL (354) recovers the clock based on a signal transmitted over the clock channel (352). Optionally, a PLL (311) may be used to achieve a higher clock frequency by multiplying the frequency of the LO (310) by a predefined factor.

VII. Light up

The inventors have developed techniques for improving data throughput of photonic interposers involving analog and/or digital equalization. Equalization improves data throughput by reducing inter-symbol interference (ISI), and consequently, by reducing bit error rate (BER). Equalization may be performed at the transmitter side of the channel, at the receiver side of the channel, or both. Equalization may amplify high frequency content and allow for lower BER operation. Several types of equalization techniques may be utilized, including but not limited to pre-emphasis feed-forward equalization (FFE), continuous time linear equalization (CTLE), and discrete feedback equalization (DFE). Photonic interposers utilizing the equalization techniques described herein can be fast enough to support clock frequencies exceeding 10 GHz, 15 GHz, or even 25 GHz, which represents a substantial improvement over conventional processors.

FIG. 3ca is a block diagram illustrating a portion of a photonic interposer configured to perform equalization. On the transmit side, the FFE unit (360) performs pre-emphasis and/or de-emphasis. On the receive side, the unit (362) performs DFE and/or CTLE. In some embodiments, the system can determine whether to perform equalization (whether FFE, DFE, or CTLE) depending on whether the communication between tile 1 and tile 2 occurs within a common photonic interposer or across two separate photonic interposers. Alternatively, the system can determine whether to perform equalization depending on whether the communication between tile 1 and tile 2 occurs using a bus waveguide or a fiber.

In addition to determining whether to apply equalization, in some embodiments the characteristics of the equalizers can be adaptively changed depending on the properties of the channel. For example, the system can determine the S ₁₁ and/or S ₂₁ parameters of the channel and, based on that information, adjust the number of taps of the DFE/CTLE unit (362). FIG. 3cb is a block diagram illustrating an example of an adaptive equalizer. An ADC (370) disposed at the end of the channel digitizes the output of the channel by generating state samples y[n], y[n-1], y[n-2], etc. The DFE/CTLE unit (362) generates the output w[n] by computing a linear combination of the state samples y[n], y[n-1], y[n-2], etc. The linear combination can be expressed as follows:

Here, c _i is a coefficient (either real or complex) representing the channel response. Here, M determines how many previous state samples y[n] are used to implement the equalization. M represents the number of taps of the equalizer. Here, M is a finite number, and the digital equalizer (400) implements a finite impulse response (FIR) filter. However, in other embodiments, the digital equalizer (400) may implement an infinite impulse response (IIR) filter. Each state sample y[ni] corresponds to a past (where i > 0) or present (where i = 0) digitization of the amplitude of the analog signal, and w[n] corresponds to a computed steady-state output value for the present set of digital inputs. In the example of FIG. 3cb, the DFE/CTLE unit (362) includes a plurality of registers (372), a plurality of digital multipliers (374), and a digital adder (376). Each register (372) records a state sample (y) at a different time. For example, one register may record y[n-1], another register may record y[n-2], and so on. The registers allow the equalizer to store the history state samples. The digital multipliers (374) multiply the state sample by a corresponding coefficient. One of the digital multipliers may, for example, multiply the state sample y[n-1] by the coefficient c ₁ . The digital adder (376) adds together the results of the digital multiplications. As a result, the output w[n] represents a linear combination of the history state samples.

The number M (representing the number of taps) can be dynamically adjusted during runtime. This means that instead of transmitting a known signal to analyze the characteristics of the channel, the system relies on the payload itself (the data transmitted from TX to RX that carries the actual information) to adjust the number of taps. Adjusting the number of taps involves changing the number of registers and digital multipliers involved in equalization. Additionally, the values of the coefficients c _i can be determined based on the characteristics of the channel.

VIII. Channel Tuning

Some embodiments relate to optical interconnects that rely on resonant devices such as ring or disk modulators and ring or disk filters. The high index contrast of silicon relative to silicon oxide results in very high mode confinement, enabling the use of resonant devices having very small footprints while maintaining low optical losses. In one example, a ring modulator can have a diameter of less than 5 μm with a quality factor (Q) exceeding 10 ⁵ . Because resonant devices can be made small without sacrificing optical losses, these devices are advantageous over other types of modulators and filters when device density is paramount (such as in the photonic interposers described herein).

However, the use of resonant devices poses challenges. A prerequisite for resonance-based operation is that the relationship between the output wavelength of the laser and the resonant wavelength of the resonator remains constant over time. Unfortunately, both the output wavelength of the laser and the resonant wavelength of the resonator are subject to thermal drift, which can cause the wavelength to change due to unpredictable changes in the local temperature. Furthermore, the resonant wavelength of the resonator can also experience nonlinear effects, such as two-photon absorption in silicon, especially when the resonator confines light and increases the flux density. When the output wavelength of the laser and the resonant wavelength of the resonator drift with respect to each other, the operation of the photonic interposer can be significantly degraded.

The present inventors have developed techniques for locking resonant devices despite the presence of thermal drift. FIGS. 3Da through 3Dc illustrate a sequence for locking the wavelength of a transmitter. As illustrated in FIG. 3Da, the transmitter of this example is capable of transmitting data along a bus waveguide (410) in one or the other direction. The transmitter includes a resonant modulator (400), a modulator driver (402), a heater (404), an MZI (406), monitoring detectors (411, 412, 413, and 414), and a resonant summing filter (408) coupled to the bus waveguide (410). The modulator driver (402) drives the modulator (400) with data. As a result, light provided by the laser is modulated with data. Depending on which output of the MZI is selected, the modulated light is coupled into the bus waveguide in one direction (e.g., from right to left) or the opposite direction (e.g., from left to right). The summation filter ensures that the data to be added to the bus waveguide is at the desired wavelength, thus enabling the bus waveguide (410) to support WDM. In this example, the summation filter is a second-order filter designed to flatten the frequency response across the passband of interest.

The first tuning step is illustrated in FIG. 3dA. Here, a linear ramp signal controls the heater (404), thereby causing a shift in the resonant frequency of the modulator (400). As the modulator is ramped, a controller (not shown in FIG. 3dA) monitors the outputs (e.g., the sum of the outputs) of the detectors (414 and 412). By determining the point at which the outputs of the detectors are maximized, it can be determined what value of the ramp causes the modulator to lock to the laser. Sweeping the modulator in this manner ensures that the resonant wavelength of the modulator is tuned (or slightly detuned) to the wavelength of the laser. In the next step, the heater is driven at a value that maximizes the outputs of the detectors (414 and 412).

The step illustrated in FIG. 3db involves tuning the MZI (406). This step ensures that 100% (or nearly 100%) of the modulator's output optical power is transmitted in one direction or the other of the bus waveguide. This is to avoid transmitting data in the wrong direction of the bus waveguide. In this step, a linear ramp signal controls the MZI (406), thereby causing a shift in the percentage of power coming from the output of the MZI. As the MZI is ramped, the controller monitors the output of either the detector (414) or the detector (412), depending on the desired transmission direction. For example, if the desired direction is from right to left, the controller monitors the output of the detector (414). By determining the point where the output of the detector (414) is minimized, it can be inferred that all power is transmitted in the desired direction. Alternatively, if the desired direction is from left to right, the controller monitors the output of the detector (412).

The step illustrated in FIG. 3dc involves tuning the summation filter (408). For the modulator (400), a heater (not shown in FIG. 3dc) may be placed near the summation filter to cause a wavelength shift when a signal is applied. Tuning the filter ensures that the desired wavelength is transmitted on the bus waveguide. In this step, a linear ramp-shaped signal controls the heater near the summation filter (408), thereby causing a shift in the resonant frequency of the filter. As the filter is ramped, the controller monitors the output of either the detector (413) or the detector (411), depending on the desired transmission direction. For example, if the desired direction is from right to left, the controller monitors the output of the detector (411). By determining the point where the output of the detector (411) is minimized, it can be inferred that all power is transmitted on the bus waveguide at the desired wavelength. Alternatively, if the desired direction is from left to right, the controller monitors the output of the detector (413). If after step 3dc of FIG. 3, it is determined that the MZI (406) is no longer properly tuned, the controller may repeat step 3dc of FIG. 3 and/or step 3db of FIG.

FIGS. 3ea and 3eb illustrate a sequence for tuning the receiver. As illustrated in FIG. 3ea, the receiver of this example can receive data transmitted along the bus waveguide (410) from either one direction or the opposite direction. The resonant drop filter (420) is a counterpart to the resonant sum filter (408) in that it allows the bus waveguide to support WDM by selecting which wavelength to transmit to the receiver. In this example, the drop filter is a second order filter designed to flatten the frequency response across the passband of interest. Monitoring detectors (424 and 425) monitor the state of the drop filter. The MZI (426) determines the direction in which to receive data, whether from the left or the right. Monitoring detectors (434 and 435) monitor the state of the MZI. The receiver (440) includes a photodetector and electronic receiver circuitry (e.g., a trans-impedance amplifier and an ADC).

The step illustrated in FIG. 3ea involves tuning the drop filter (420). For the modulator (400), a heater (not shown in FIG. 3ea) may be placed near the drop filter to cause a wavelength shift when a signal is applied. Tuning the filter ensures that the desired wavelength is received from the bus waveguide. In this step, a linear ramp-shaped signal controls the heater-proximate drop filter (420), thereby causing a shift in the resonant frequency of the filter. As the filter is ramped, the controller monitors the output of the detector (413) or the detector (411) depending on the desired transmission direction. For example, if the desired direction is from left to right, the controller monitors the output of the detector (425) and/or the output of the detector (424). By determining the point where the output of the detector (425) is maximized and/or the output of the detector (424) is minimized, it can be inferred that all of the power received from the bus waveguide is at the desired wavelength. In contrast, if the desired direction is from right to left, the controller monitors the output of the detector (424) to be maximized and/or the output of the detector (425) to be minimized.

The step illustrated in FIG. 3eb involves tuning the MZI (426). This step ensures that 100% (or nearly 100%) of the optical power provided to the receiver is received from one direction or the other. This is to avoid receiving data from the wrong direction of the bus waveguide. In this step, a linear ramp signal controls the MZI (426), thereby causing a shift in the percentages of power received from the inputs of the MZI that are ultimately transmitted to the RX (440). As the MZI is ramped, the controller monitors the output of the detector (434) or detector (435). By determining the point where the output of the detector (435) is maximized and/or the output of the detector (434) is minimized, it can be inferred that all power is received from the desired direction.

Taking advantage of the resonant nature of the wavelength division multiplexing transmission described above, the inventors have further developed techniques involving dithering to enable a receiver to uniquely identify a particular transmitter. Dithering involves modulating a resonant component at a relatively slow frequency (e.g., between 1 KHz and 1000 KHz) to uniquely identify signals propagated through that component. In some embodiments, the slow frequency should be supported by a modulating element, such as a thermo-optic heater. Essentially, the component marks the signal with a signature in the form of a particular dithering frequency. Each component may be dithered at a slightly different frequency. Component identification becomes particularly important in architectures having multiple components in series. In some embodiments, detectors may rely on the dithering frequencies to identify which transmitter is transmitting a given piece of data. In one example, the dithered signal is used to lock a drop filter of the receiver to a particular modulator. It is important to note that the dithering signal may be applied to non-resonant elements associated with transmission of a particular wavelength (e.g., MZIs such as in component (406)).

FIG. 3fa illustrates a technique for locking a receiver to a particular transmitter using dithering, according to some embodiments. In this example, multiple transmitters and multiple receivers are coupled in series along the length of a bus waveguide (410). The transmitters are coupled to the bus waveguide via summation filters (408), and the receivers are coupled to the bus waveguide via drop filters (420). The architecture of the transmitters is similar to that illustrated in FIG. 3da, and the architecture of the receivers is similar to that illustrated in FIG. 3ea. In this case, the signals to be maximized/minimized by detectors (424 and 425) within the RX device are dithered. Analog circuits may be constructed to capture the signals at a particular dithering frequency, for example, using homodyne or heterodyne circuits, where a local oscillator may be generated locally by the RX device. Different TX-RX transmit pairs within the series will utilize different dithering frequencies. Care must be taken to ensure that the different dithering frequencies are not rational fractions of each other, for example f1/f2 are not rational fractions a/b, where a and b are integers. Thus, by utilizing signals at a particular dithering frequency associated with a particular TX-RX transmit pair, components within and between the TX-RX transmit pair can be locked to the correct pair (and not confused by signals from other TX-RX pairs). In some embodiments, the drop filter of the receiver can be locked to the modulator of a particular transmitter by dithering the modulator at some frequency and then having detectors (main and tap) within the RX device to maximize/minimize signals at that particular frequency. Furthermore, in some embodiments, multiple components within the same TX-RX transmit link can be dithered using the same dithering frequency, so that all detectors within the TX-RX transmit link need only generate a single dithering frequency to be locked to. In other embodiments, different components within a same TX-RX transmission link may be dithered at different frequencies so that detectors within the TX-RX link can distinguish error signals of different components along the link. The dithering frequencies may be slower than the frequency of the crystal oscillators (in MHz regimes) typically used to construct the PLL.

In some embodiments, FIR digital bandpass filters (not shown in FIG. 3fa) programmed to identify specific dithering frequencies may be coupled to the detector. In such embodiments, locking between the transmitter and receiver may involve programming the FIR digital bandpass filters to only accept signals that are dithered at specific frequencies.

FIG. 3fb illustrates an optical channel supporting communication between multiple transmitter-receiver pairs. A transmitter (TX1) and a receiver (RX1) form a pair, and data transmitted by TX1 is directed to RX1. A transmitter (TX2) and a receiver (RX2) form another pair, and data transmitted by TX2 is directed to RX2. A transmitter (TX3) and a receiver (RX3) form another pair, and data transmitted by TX3 is directed to RX3. A transmitter (TX4) and a receiver (RX4) form another pair, and data transmitted by TX4 is directed to RX4. Each TX-RX pair uses a unique dithering frequency (f1 for TX1-RX1, f2 for TX2-RX2, f3 for TX3-RX3, and f4 for TX4-RX4). Each pair can utilize unique wavelengths in the optical channels, namely λ1, λ2, λ3 and λ4.

IX. Redundancy

The inventors have recognized and understood that finite yields associated with microscale fabrication processes can negatively impact the scalability of photonic interposers. The yield associated with a fabrication process is the ratio of defect-free components divided by the total number of manufactured components. The yield of a fabrication process is typically less than 100% and is due to a variety of factors including, for example, equipment performance, system complexity, and operator skills.

Certain types of defects can impair the functionality of a photonic circuit. When light encounters one of these defects, partial or complete loss of optical power can occur. Other types of defects can impair the functionality of electronic circuitry and/or wiring that is part of the tile (e.g., a modulator driver or a trans-impedance amplifier). When an electrical signal encounters one of these defects, signal attenuation or complete loss can occur.

A. Fiber Attachment Redundancy

The limited yield implications of fiber attachment can be particularly severe. Fiber attachments enable photonic integrated circuits (e.g., photonic interposers) to communicate with the outside world using optical fibers. Fiber attachment can be performed using passive or active processes. In passive processes, the fiber is attached to the chip without any feedback as to whether or not the light is being coupled and to what extent. In active processes, the chip provides feedback, which can be used to improve optical alignment before the fiber is secured to the chip. Active processes provide higher coupling efficiencies than passive processes, but they are more expensive. Unfortunately, both types of processes have finite yields. Additionally, chip operators cannot determine whether a fiber attachment has been produced until the package is fully (or nearly fully) assembled. This is because fiber attachment is one of the last process steps in packaging a photonic integrated circuit.

Whether via edge bonding, vertical bonding, or using v-grooves, the yield in industrial situations is still ~95% when attaching multiple (16 or 32) fibers at once. The types of fiber attachments described herein refer to attaching a single fiber (e.g., a single-mode, polarization maintaining, or multi-core fiber) or an array of fibers (e.g., a v-groove fiber array or a ribbon of fibers). Applications that require many fibers, such as optically interconnected servers, require higher fiber attachment yields. If a particular system requires N attachment sites to be produced, the throughput rate of the system is , where p is the probability that an attachment site will yield. Even when p ~ 90%, the yield rate drops sharply to ~20% for N = 16. More fault-tolerant attachment strategies are required to increase the yield rate of the system. The current focus is on increasing the yield of the fiber attachment itself by introducing new packaging processes, such as better index-matching epoxies/adhesives or better active alignment during the attachment process. However, these processes are often inadequate.

The inventors have developed a method for increasing the throughput of fiber attachments involving fiber redundancy. This can be achieved by having more fiber attachments than are necessary to operate the photonic integrated circuit. A controller identifies which of all fiber attachments, or which subset of fiber attachments, provides better performance. These fibers are utilized during operation of the chip, while the other fibers remain unused. This process can be performed in real time, thus allowing the controller to continuously monitor the quality of the fiber attachments during operation.

FIG. 4aa illustrates a photonic integrated circuit (PIC) (900) having photonic circuits (902) and a plurality of fiber attachments. The PIC (900) may represent, for example, any of the photonic interposers described herein. In such embodiments, the photonic circuits (902) may include tiles, transceivers, and photonic interconnects as described above. However, fiber redundancy may be utilized with any type of PIC. At each attachment site, a fiber (908) is coupled to a waveguide (907) of the PIC via an optical chip-to-fiber coupler (906) (e.g., an edge coupler, v-groove, grating). As illustrated, instead of having only a single fiber attachment, an additional k-1 fiber attachments are provided (for a total of k fiber attachments). An optical switch (904) on the PIC selects which of the k fiber attachments will be used for operation of the PIC. A controller (903) monitors the performance of each fiber attachment and controls the operation of the optical switch (904).

Different schemes may be used to monitor the performance of the fiber attachments. In one example, photodetectors (909) coupled to the waveguides (907) using tap couplers monitor the optical power present in the waveguides (only one photodetector (909) is shown in FIG. 4aa). The photodetectors (909) provide information to the controller (909) representing the optical power present in the various waveguides (907). Based on this information, the controller (909) can determine which subset of the k fiber attachments (which may be one or more fiber attachments) provides the best performance. The controller (909) can then control the optical switch (904) to select the waveguide(s) corresponding to the best performing subset of fiber attachments. In another example, the photonic integrated circuits (902) may include a system for monitoring the quality of channels corresponding to the various fiber attachments. For example, the photonic integrated circuits (902) may monitor a bit error rate (BER), an eye diagram quality factor, power, and/or a signal-to-noise ratio (SNR) associated with each channel. In this example, the controller (909) may control the optical switches (904) to sequentially select one waveguide at a time, thereby allowing the photonic circuits (902) to individually monitor the quality of each channel. The photonic circuits (902) provide information to the controller (909) indicative of the quality of the various channels. Based on this information, the controller (909) may determine which subset of the k fiber attachments (which may be one or more fiber attachments) provides the best performance. The controller (909) may then control the optical switches (904) to select the waveguide(s) corresponding to the best performing subset of fiber attachments. In some embodiments where fiber attachment performance can be measured prior to final system assembly, the worse performing subset of fiber attachments need not be connected to other optical devices or connectors. In other embodiments where fiber attachment performance cannot be measured prior to final assembly, all fiber attachments can be performed and subset selection can be performed subsequently.

The redundancy scheme described with respect to FIG. 4aa can be utilized whether the PIC (900) is utilized as a transmitter or a receiver. FIG. 4ab is a block diagram illustrating a pair of PICs (900) interconnected using k fibers, some of which are provided solely for redundancy. One PIC operates as a transmitter; in this PIC, the photonic circuits (902) operate as TX photonic circuits. The other PIC operates as a receiver; in this PIC, the photonic circuits (902) operate as RX photonic circuits. Each of the controllers (909) monitors the quality of the fiber attachments and controls each of the optical switches (904) to select the waveguide(s) corresponding to the best performing subset of fiber attachments.

If the probability that an individual fiber attachment will operate properly is p, then the overall probability that at least one of the k fiber attachments will operate properly by exploiting fiber redundancy is equal to 1-(1-p) ^k . Since this quantity is always greater than p, it improves throughput. For example, consider a system that requires 16 functional fiber attachment sites to be produced. By utilizing redundant fiber attachments at each attachment site, the system throughput can be increased to close to 100% even when the success probability of the fiber attachment is low. The results are shown in Fig. 4ac. Fig. 4ac illustrates the overall system throughput (in percent) for a system having 16 fiber attachment sites as a function of the number of attachments at each site. Having a single attachment (1 on the x-axis) means that no redundant fiber attachments are utilized. Having N attachments (N on the x-axis) means that N-1 redundant fiber attachments are utilized. As can be seen from this figure, the overall system throughput approaches 100% as the number of attachments increases, regardless of the initial probability that the fiber attachments will function properly.

B. Tile Redundancy

The inventors further understand that not all tiles of a photonic interposer may be produced. Some of the tiles may, for example, have defective transmitters, receivers, interconnects and/or switches. This may negatively impact the performance of the network in that electronic chips mounted on a defective tile may become unavailable. Additionally, not all electronic chips mounted on a photonic interposer may be produced. To eliminate these problems, the inventors have developed a scheme involving tile redundancy.

FIG. 4b illustrates photonic interposers having multiple tiles, one of which is provided for redundancy. Electronic chips (911, 912, 913, 914, 915, and 916) are mounted on the photonic interposer (20) corresponding to each tile. Optionally, an additional electronic chip (917) may be placed on the redundant tile. The chip (917) may also be provided for redundancy in case one of the other electronic chips is not functioning properly. For example, the chip (917) may be a copy of one of the other chips. In this example, the tile corresponding to chip (914) is not produced. In response, the photonic interposer may be reconfigured to functionally swap the redundant tile and the non-producing tile. Utilizing the programmable interconnects described above, optical signals directed to the non-producing tile may be redirected to the redundant tile. Optionally, a duplicate chip (917) may be used instead of the chip (914).

In some embodiments, wafer-level testing can be used to determine whether tiles of a photonic wafer are yieldable. This approach allows operators to determine the quality of a wafer without having to individually test separate portions of the wafer. A disadvantage of this approach is that once a particular portion of a wafer is designed for a particular application, tiles of that wafer portion are ultimately packaged as part of a photonic interposer, whether or not they are yieldable.

In some embodiments, the performance of the tiles can be monitored in real time during operation. This can be accomplished using a power monitoring grid, an example of which is illustrated in FIG. 4c. The power monitoring grid includes a number of photodetectors (e.g., photodetector (909) of FIG. 4aa) positioned at various locations in the photonic interposer. The photodetectors can be coupled to various photonic components via tap couplers. Using the power monitoring grid, it can be determined, for example, that a particular tile is not operating as expected. Using this information, the system can decide to reconfigure itself to functionally swap that tile with one of the redundant tiles. This operation can be performed during operation of the photonic interposer.

X. Manufacturing of grid-based packages

The photonic interposers described herein require light to operate, whether the light is provided by lasers or other types of sources. Unfortunately, due to the poor optical emission rate of silicon, it is difficult to monolithically integrate lasers with a photonic interposer. Instead, it is often more practical to use an external laser (either on the same board as the interposer or in the same package) and direct the light emitted by the external laser into the chip. This can be done via edge coupling or surface coupling. Edge coupling involves coupling optical modes from a fiber to a waveguide through one of the side surfaces of the chip. In contrast, surface coupling involves coupling optical modes from a fiber to a waveguide through the top surface of the chip. To steer light from outside the plane of the top surface into waveguides that extend parallel to the top surface of the chip, grating couplers are often used. Grating couplers are planar structures formed on or just below the top surface of the photonic chip.

The inventors have recognized and understood that the presence of particles or other types of debris on the top surface of the chip can negatively affect the fiber-to-grating coupling efficiency. This is because the particles can create scattering. Unfortunately, particle-free operation is difficult to achieve due to the various fabrication steps that occur after the formation of the grating but before the fibers are attached to the top surface of the chip.

The inventors have developed fabrication processes that limit the accumulation of particles or other debris on the top surface of the photonic chip, leading to improved fiber-to-grating efficiency. In some embodiments, this can be accomplished by forming a temporary protective layer positioned so that the gratings are protected during process steps that are more likely to generate unwanted particles. Once these process steps are complete, the temporary protective layer can be removed, exposing the grating to air for subsequent fiber attachment. The temporary protective layers can be formed before or after the electronic chips (e.g., ASICs) are bonded to the photonic interposer. Examples of protective layers include photo-imageable dielectrics (e.g., polyimide or resist) and glass (e.g., with a UV-releasable adhesive). Other materials are also possible. Additionally, in some embodiments, particle-free processing can be accomplished by utilizing a custom molding process designed to encapsulate the electronic chip without ever contacting the grating coupler.

FIG. 5A is a schematic diagram illustrating a fiber coupled to a grating coupler formed on a photonic interposer according to some embodiments. A fiber (1120) is disposed over a grating coupler (1110) formed on a top surface of a photonic interposer (1130). The fiber (1120) is at a non-zero angle with respect to a surface of the photonic interposer (1130). In this example, the fiber is also at a non-zero angle with respect to an axis perpendicular to the top surface of the interposer, although in some embodiments the fiber may be parallel to the vertical axis. Light from a fiber core (1122) of the fiber (1120) is coupled to the grating coupler (1110). The grating then transmits the light to a waveguide (1121).

FIG. 5BA is a top view of a wafer (1130) patterned to form photonic circuits that may be utilized as photonic interposers, once diced from the wafer. Electronic chips (1210) are mounted on the photonic interposer(s). The electronic chips are encapsulated by an encapsulating material (1220), which may be formed using mold compounds. Regions (1230) include grating couplers formed on the top surface of the wafer. To allow for subsequent fiber attachment, these regions are not covered by the encapsulating material.

FIG. 5bb is a cross-sectional side view of a portion of the wafer of FIG. 5ba taken from the y-axis in the x-z plane. The drawing depicts a plurality of electronic chips mounted on a top surface of a photonic interposer. The electronic chips are encapsulated by an encapsulating material (1220). Regions (1230) are exposed to air.

FIG. 5ca illustrates the photonic interposer of FIG. 5bb after dicing. Regions (1230) are left exposed to air so that fibers can be attached in a subsequent step. Connections (1310) formed on the bottom surface of the photonic interposer allow for connection of the photonic interposer to a circuit board (1340). Examples of the connections (1310) include ball grid arrays (BGA), copper pillars, C4 bumps, pins, and the like.

FIG. 5cb is a cross-sectional side view of the package after a fiber (1120) is attached to the top surface of the interposer (1130). When the fiber is attached, the fiber core is optically coupled to the grating coupler. In this drawing, the interposer (1130) is mounted on a printed circuit board (PCB) (1340) via connectors (1310) that pass through an underfill (1330). A cap (1320), such as a heat spreader, is placed on top of the electronic chips. The fiber (1120) is coupled to the grating coupler on one side of the package via a steering optic component (1350), which steers light propagating within the fiber in a direction that is at a non-zero angle with respect to the top surface of the photonic interposer, such that the fiber mode couples to the grating.

Figures 5d, 5e, and 5f are flowcharts illustrating various processes for fabricating a packaged photonic interposer. These fabrication processes are designed to prevent (or at least limit) particle or debris accumulation relative to the fiber gratings, thereby enabling low-loss, high-efficiency fiber-to-grid bonding. As discussed in more detail below, the processes of Figures 5d and 5e involve temporary protective layers. The process of Figure 5f involves a custom molding process.

Referring first to FIG. 5D , the fabrication process begins at step 4A in a packaging facility, which involves obtaining a photonic interposer (1130) patterned with one or more grating couplers (e.g., the photonic interposer of FIG. 1Cb or any of the photonic interposers described herein) and covering regions (1230) (where the gratings are patterned) with a protective material (1438). As a result, the grating couplers are covered. The photonic interposer can be received from a semiconductor foundry into a packaging facility, where a wafer is patterned with photonic and electronic circuits including the grating couplers. Examples of materials that can be used for the protective material (1438) include a photo-imageable film (PIF) (e.g., polyimide or photoresist). In step 4B, electronic chips (1210) (e.g., ASICs, processors, memories, etc.) are placed on the photonic interposer. In step 4C, the electronic chips (1210) are encapsulated with an encapsulating material (1220) via a process such as mass reflow and wafer level mold underfill (WL MUF). It should be noted that the protective film applied in step 4A does not allow coverage of the mold compound on the grating couplers in step 4C, and further preserves the cleanliness of the grating couplers from any contaminants and particulates released during the subsequent backgrinding and CMP process step 4D. The encapsulation provides protection to the chips and enables subsequent formation of the TSV exposure process steps. In step 4D, the encapsulating material is removed from the top of the electronic chips via planarization (e.g., CMP) or backgrinding to enable attachment of the carrier mount (1638) which occurs in step 4E (after the flipping step). In step 4F, the connectors (1310) (e.g., BGA) are attached to the bottom surface of the photonic interposer after the TSV exposure process. It should be noted that attachment of the connectors (1310) to the interposer may generate particles or other debris. However, this attachment step occurs at a time when the grating couplers are covered by the passivation material (1438). As a result, any particles or debris generated during the attachment step do not affect the cleanliness of the top surface on which the grating couplers are patterned. In step 4G, the carrier mount (1638) is removed from the top of the electronic chips. In step 4H, a UV releasable adhesive tape (1330) (e.g., dicing tape) is applied. In step 4I, the passivation material (1438) is removed from the top surface of the photonic interposer, leaving the grating couplers exposed to air. Optionally, a cleaning step may be performed using a plasma process to ensure surface cleanliness for fiber attachment and optical coupling. In step 4J, the photonic interposer is separated into a plurality of systems, each including one or more electronic chips and one or more grating couplers, for example, by stealth dicing or a mechanical saw. In step 4K, the photonic interposer is attached to a circuit board (1340) by processes such as mass reflow, capillary underfill (CUF), and urea-formaldehyde (UF) resin curing. Additionally, caps (1320) are attached to the electronic chips, where the caps may act as heat spreaders. Additionally, an Open/Short (O/S) test is performed to ensure good electrical connection between the photonic interposer and the circuit board. Finally, a fiber (1120) is attached to the top surface of the interposer. As a result, the fiber is optically coupled to the grating coupler.

FIG. 5E is a flow chart illustrating an alternative method for fabricating a photonic package, according to some embodiments. The method of FIG. 5E is similar in some aspects to the method of FIG. 5D . The main difference is that the protective material (1538) is formed after attaching the chips to the photonic interposer and after the encapsulation step. Step 5A involves obtaining a photonic interposer (1130) patterned with one or more grating couplers and placing chips (1210) on the interposer. In step 5B, the electronic chips (1210) are encapsulated with an encapsulation material (1220) via processes such as mass reflow and wafer level mold underfill (WL MUF). As described above, the encapsulation provides protection for the chips and enables subsequent formation of TSV exposure process steps. In step 5C, a protective material (1538) (e.g., a glass cover having a UV-releasable adhesive) is placed over the areas of the interposer where the grating couplers are formed. Attachment of the protective glass preserves the cleanliness of the grating couplers from any contaminants and particles released during the subsequent backgrinding and CMP process step 5D. In step 5D, the top surface is planarized or background. In step 5E, the interposer is flipped and the connectors (1310) (e.g., BGAs) are attached to the bottom surface of the photonic interposer after the TSV exposure process. As noted above, attachment of the connectors (1310) to the interposer may generate particles or other debris. However, this attachment step occurs at a time when the grating couplers are covered by the protective material (1538), thereby preserving the cleanliness of the top surface where the grating couplers are patterned. In step 5F, the protective material (1538) is removed, thus exposing the grating couplers to air. Optionally, plasma cleaning is performed on the top surface of the photonic interposer. Subsequent steps are similar to those depicted in FIG. 5D, including fiber attachment.

FIG. 5f is a flow chart illustrating another alternative method for fabricating a photonic package, according to some embodiments. The method of FIG. 5f differs from the methods of FIGS. 5d and 5e in that no protective materials are used to cover the grating couplers. Instead, a custom designed molding process is performed to encapsulate the electronic chip while avoiding covering and contaminating the grating couplers with debris caused by the encapsulation step. Subsequent steps are similar to those described with respect to FIG. 5d.

In step 6A, chips (1210) are mounted on the interposer (1130). In step 6B, encapsulation material (1120) is formed using a custom molding process in a manner that avoids covering the regions (1230). As a result, contamination generated by the molding step that would otherwise affect the cleanliness of the grid couplers is prevented (or at least limited). Therefore, the process avoids leaving impurities on the top of the grid couplers. In step 6C, the top surface of the package is planarized or background. In step 6D, the package is mounted on a carrier mount (1638). In step 6E, after the TSV exposure process, the device is flipped and the connectors (1310) are attached to the bottom surface of the interposer. In step 6F, the carrier mount (1638) is removed. In step 6G, the interposer is diced. At step 6H, the fiber is attached to the top surface of the interposer to be coupled to the grating coupler.

XI. Power distribution

FIG. 5G is a cross-sectional side view of a photonic package mounted on a circuit board including a power delivery system according to some embodiments. The package of FIG. 5G includes a circuit board (1740), a socket (1730), a substrate (1720), a photonic interposer (1714), electronic chips (1712), a lid (1732), a cooling plate (1734), voltage regulator modules (VRMs) (1750), connectors (1752), and power buses (1754). The photonic interposer (1714) and the electronic chips (1712) mounted on the photonic interposer have similar characteristics to the interposers and chips described in detail above. The lid (1732) covers the electronic chips and is positioned in thermal contact with the electronic chips. The lid (1732) and a cooling plate (1734) positioned on top of the lid transfer heat generated by the electronic chips to the outside of the package. As can be seen in FIG. 5g, a photonic interposer (1714) is disposed on a substrate (1720) (e.g., an organic substrate), and the substrate (1720) is disposed on a socket (1730). The socket (1730) is additionally disposed on a top surface of a circuit board (1740).

The package of FIG. 5g relies on power buses (1754), VRMs (1750), and connectors (1752) to deliver power to the photonic interposer and electronic chips. As illustrated in FIG. 5ha, the VRM receives power from the power buses and provides regulated power outputs to the electronic components to avoid voltage fluctuations beyond an acceptable value caused by loads resulting from the electronic chips. The inventors have discovered that having the VRMs (1750) and power buses (1754) mounted on a bottom surface of the circuit board (1740) (on the opposite side of the circuit board relative to the interposer) allows for a reduction in the lateral extension of the circuit board (1740), thereby reducing power losses that would otherwise result from longer lateral paths for power delivery, as compared to implementations where the VRMs and power buses are disposed on the circuit board near the interposer. As a result, the design is more compact and easier to integrate with other electronic systems. In this configuration, the interconnects (1752) interconnect the VRMs and corresponding electronic chips by traversing multiple layers, namely the interposer (1714), the substrate (1720), the socket (1730) and the circuit board (1740). The interconnects (1752) involve a series of different types of vias, the nature of which depends on the substrate they traverse.

FIG. 5hb is a cross-sectional side view illustrating how power may be delivered from VRMs to electronic chips. In some embodiments, a VRM delivers power to a single electronic chip. In other embodiments, a VRM delivers power to multiple electronic chips. In FIG. 5hb, a single VRM is illustrated delivering power to four electronic chips via connectors (1752).

XII. Additional comments

While the various aspects and embodiments of the technology of the present application have been described above, it should be appreciated that various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. Accordingly, it should be understood that the foregoing embodiments are presented by way of example only, and that, within the scope of the appended claims and equivalents thereto, the embodiments of the present invention may be practiced otherwise than as specifically described. Furthermore, any combination of two or more of the features, systems, articles, materials, and/or methods described herein, provided that such features, systems, articles, materials, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

Additionally, as described, some aspects may be implemented as one or more methods. The operations performed as part of the methods may be sequenced in any suitable manner. Thus, although illustrated as sequential operations in the exemplary embodiments, embodiments may be constructed in which the operations are performed in a different order than described, which may include performing some of the operations concurrently.

All definitions as defined and used in this specification should be understood to take precedence over dictionary definitions, definitions in documents incorporated by reference, and/or the ordinary meaning of the defined terms.

As used in this specification and claims, the singular forms (including the indefinite articles "a" and "an") are to be understood to mean "at least one," unless the context clearly dictates otherwise.

The phrase "and/or," as used in this specification and claims, should be understood to mean "either or both" of the elements so conjoined, i.e., elements that exist in conjunction in some cases and in separate instances.

As used in this specification and the claims, the phrase “at least one,” in relation to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of each and every element specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows that elements other than the elements specifically identified in the list of elements to which the phrase “at least one” refers may optionally be present, whether or not related to the specifically identified elements.

The terms "approximately" and "about" may be used in some embodiments to mean within ±20% of the target value, in some embodiments within ±10% of the target value, in some embodiments within ±5% of the target value, and also in some embodiments within ±2% of the target value. The terms "approximately" and "about" may include the target value.

Claims (15)

As a photonic device,
photonic circuit;
A plurality of optical channels having a plurality of chip-to-fiber couplers and a plurality of waveguides coupled to each of the chip-to-fiber couplers;
An optical switch coupled between the plurality of optical channels and the optical circuit; and
Controller
, wherein the controller comprises:
Determining information representing performance associated with each of the plurality of optical channels;
Identifying a subset of said plurality of optical channels using information representing performance associated with each of said plurality of optical channels;
A photonic device configured to selectively couple a subset of said plurality of optical channels to said photonic circuit by controlling said optical switch. In the first paragraph,
A photonic device wherein said plurality of optical channels further include a plurality of photodetectors coupled to respective waveguides, and wherein determining information indicative of performance associated with each of said plurality of optical channels comprises determining an output of each of said plurality of photodetectors. In the second paragraph,
A photonic device wherein the plurality of photodetectors are coupled to the respective waveguides via tap couplers. In the first paragraph,
A photonic device, wherein determining information indicative of performance associated with each of said plurality of optical channels comprises determining a bit error rate (BER) associated with each of said plurality of optical channels. In the first paragraph,
The photonic circuit comprises a plurality of tiles patterned according to a template tile, each tile comprising:
telautograph;
receiving set;
a network of programmable optical connections; and
Electrical connections configured for vertical die-to-die connection with an electronic chip, said electrical connections being coupled to a network of said transmitter, said receiver and said programmable optical connections;
A photonic device comprising: In the first paragraph,
A photonic device wherein identifying a subset of the plurality of optical channels using said information comprises identifying a subset of the plurality of optical channels that exhibits the best performance among the optical channels. In the first paragraph,
The above chip-to-fiber couplers are photonic devices including edge couplers or grating couplers. In the first paragraph,
A photonic device, wherein the controller is further configured to control the photonic circuit to transmit data external to the photonic device using a subset of the plurality of optical channels selected by the optical switch. A method for transmitting data using a photonic device comprising an optical switch, a plurality of chip-to-fiber couplers, and a plurality of optical channels having a plurality of waveguides coupled to each of the chip-to-fiber couplers, the method comprising:
A step of determining information representing performance associated with each of the plurality of optical channels;
A step of identifying a subset of the plurality of optical channels using information representing performance associated with each of the plurality of optical channels;
a step of controlling the optical switch to select a subset of the plurality of optical channels; and
A step of transmitting said data outside of said photonic device using a subset of said plurality of optical channels selected by said optical switch.
A method comprising: In Article 9,
A method wherein the plurality of optical channels further include a plurality of photodetectors coupled to respective waveguides, and wherein the step of determining information indicative of performance associated with each of the plurality of optical channels includes the step of determining an output of each of the plurality of photodetectors. In Article 9,
A method, wherein the step of determining information indicative of performance associated with each of the plurality of optical channels comprises the step of determining a bit error rate (BER) associated with each of the plurality of optical channels. In Article 9,
A method wherein the step of identifying a subset of the plurality of optical channels using the above information comprises the step of identifying a subset of the plurality of optical channels exhibiting the best performance among the optical channels. As a photonic interposer,
A plurality of photonic tiles including overlapping tiles, each photonic tile comprising:
telautograph;
receiving set;
A network of programmable optical connections;
Electrical connections configured for vertical die-to-die connection with an electronic chip, said electrical connections being coupled to a network of said transmitter, said receiver and said programmable optical connections;
Monitoring photodetector; and
Controller
, wherein the controller comprises:
Using the output of each of the above monitoring photodetectors, information representing the performance of each of the plurality of photonic tiles is determined;
Among a plurality of tiles, a defective tile is identified by using information representing the performance of each of the plurality of photonic tiles;
A photonic interposer configured to functionally swap said defective tile with said duplicate tile. In Article 13,
A photonic interposer, wherein functionally swapping said defective tile with said duplicate tile comprises redirecting data directed to said defective tile to said duplicate tile. In Article 14,
A photonic interposer, wherein redirecting said data comprises programming a network of programmable photonic interconnects.