KR20240144674A - Display apparatus - Google Patents

Abstract

A display device is provided. The display device includes a substrate, a circuit layer, and an element layer. A display area of the substrate includes a main display area in which light-emitting areas are arranged in parallel with each other, and at least one sub-display area surrounded by the main display area. The circuit layer includes light-emitting pixel drivers electrically connected to light-emitting elements of the element layer, respectively, data wires transmitting data signals to the light-emitting pixel drivers, first dummy wires extending in a first direction intersecting the data wires, and second dummy wires extending parallel to the data wires and paired with the data wires, respectively. The second dummy wires include reset transmission wires extending from a non-display area of the substrate to the at least one sub-display area.

Description

DISPLAY APPARATUS

The present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation, and smart televisions.

The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, a light emitting display device, or the like. Here, the light emitting display device may include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device including an ultra-small light emitting element.

Organic light-emitting display devices display images using light-emitting elements, each of which includes a light-emitting layer of an organic light-emitting material. As such, organic light-emitting display devices implement image display using self-luminous elements, and thus can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

One side of the display device may be a display surface including a display area where an image is displayed and a non-display area surrounding the display area. The display area may have light-emitting areas arranged to emit light with respective brightnesses and colors.

Meanwhile, the display device can be provided in various designs to suit various electronic devices.

For example, a display device adapted for an electronic device including an optical device, such as a smartphone or tablet device, may include a hole that overlaps the optical device. Light entering through the hole can be detected by a camera sensor.

In this case, there is a problem that the ratio of the display area to the display surface decreases as the width of the non-display area increases due to the arrangement of the holes overlapping the optical device.

Accordingly, the problem to be solved by the present invention is to provide a display device that can be fitted into an electronic device including an optical device without a hole overlapping with the optical device, so that the ratio of the display area to the display surface can be maintained.

The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to embodiments for solving the above problem includes a display area including light-emitting areas, a substrate including a non-display area arranged around the display area, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer and including light-emitting elements respectively corresponding to the light-emitting areas. The display area includes a main display area in which the light-emitting areas are arranged parallel to each other, and at least one sub-display area surrounded by the main display area. The at least one sub-display area further includes light-transmitting areas arranged between the light-emitting areas. The circuit layer includes light-emitting pixel drivers electrically connected to the light-emitting elements of the element layer, data wires transmitting a data signal to the light-emitting pixel drivers, first dummy wires extending in a first direction intersecting the data wires, and second dummy wires extending parallel to the data wires and respectively paired with the data wires. The second dummy wires include reset transmission wires extending from the non-display area to the at least one sub-display area.

The display device may further include a display driving circuit that outputs data signals of the data wires. The circuit layer may further include data supply wires that are arranged in the non-display area and electrically connected to the display driving circuit. A bypass area on one side of the display area may include a central bypass middle area, a first bypass side area that is parallel to the bypass middle area in a first direction and contacts the non-display area, and a second bypass side area that is arranged between the bypass middle area and the first bypass side area. The data wires may include a first data wire arranged in the first bypass side area, and a second data wire arranged in the second bypass side area. The first dummy wires may include a first transmission bypass wire that is electrically connected to the first data wire. The second dummy wires may further include a second transmission bypass wire that is paired with the second data wire and electrically connected to the first transmission bypass wire. Among the data supply wires, the first data supply wire that transmits the data signal of the first data wire can be electrically connected to the first data wire through the first transmission bypass wire and the second transmission bypass wire. Among the data supply wires, the second data supply wire that transmits the data signal of the second data wire can be directly electrically connected to the second data wire.

The circuit layer may further include first power supply wiring and second power supply wiring, which respectively transmit first power and second power for driving the light-emitting elements. The first dummy wirings may further include first auxiliary wirings that are electrically connected to the second power supply wiring. The second dummy wirings may further include second auxiliary wirings that are electrically connected to the first auxiliary wirings and the second power supply wiring.

Two of the first auxiliary wires among the first auxiliary wires may extend from both sides of the first transmission bypass wire to the non-display area. One of the second auxiliary wires may extend from one side of the second transmission bypass wire to the non-display area.

Among the above light-emitting pixel drivers, one light-emitting pixel driver disposed in the main display area may include a first transistor generating a driving current for driving one of the light-emitting elements, a second transistor electrically connected between one of the data wires and a first electrode of the first transistor, a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor, a first initialization power wire transmitting a first initialization power, a fourth transistor electrically connected between the gate electrode of the first transistor, a fifth transistor electrically connected between the first power wire transmitting the first power and the first electrode of the first transistor, a sixth transistor electrically connected between the second electrode of the first transistor and the one light-emitting element, a second initialization power wire transmitting a second initialization power, a seventh transistor electrically connected between the one light-emitting element, and an eighth transistor electrically connected between a bias power wire transmitting a bias power and the first electrode of the first transistor.

The at least one sub-display area may overlap with at least one optical device disposed beneath the substrate.

Among the above light-emitting pixel drivers, another light-emitting pixel driver arranged in at least one sub-display area may be electrically connected to another light-emitting element among the light-emitting elements. The other light-emitting pixel driver may further include a reset unit that transmits reset power to the other light-emitting element based on a reset control signal.

The above reset unit may include a ninth transistor electrically connected between the reset power wiring and the other light-emitting element. A gate electrode of the ninth transistor may be electrically connected to the reset control wiring.

The circuit layer may further include a reset power supply wiring arranged in the non-display area and transmitting the reset power, and a reset control supply wiring arranged in the non-display area and transmitting the reset control signal. The reset transmission wirings may include a reset power transmission wiring electrically connecting between the reset power supply wiring and the reset power wiring, and a reset control transmission wiring electrically connecting between the reset control supply wiring and the reset control wiring.

Between two data wires that overlap with two adjacent light-emitting pixel drivers among the above data wires, two second dummy wires that are paired with the two data wires among the above second dummy wires and are adjacent to each other can be arranged.

The above second dummy wires may further include an offset wire adjacent to the reset control transmission wire and transmitting an offset signal having a polarity opposite to that of the reset control signal.

A display device according to embodiments for solving the above problem includes a display area including light-emitting areas, a substrate including a non-display area arranged around the display area, a circuit layer arranged on the substrate, and an element layer arranged on the circuit layer and including light-emitting elements respectively corresponding to the light-emitting areas. The display area includes a main display area in which the light-emitting areas are arranged in parallel with each other, and at least one sub-display area surrounded by the main display area and overlapping with at least one optical device arranged under the substrate. The circuit layer includes light-emitting pixel drivers electrically connected to the light-emitting elements of the element layer, data wires transmitting a data signal to the light-emitting pixel drivers, first dummy wires extending in a first direction intersecting the data wires, second dummy wires extending parallel to the data wires and respectively paired with the data wires, data supply wires electrically connected to a display driving circuit arranged in the non-display area and outputting data signals of the data wires, and first power supply wires and second power supply wires transmitting a first power source and a second power source for driving the light-emitting elements, respectively. A bypass region on one side of the display region includes a central bypass middle region, a first bypass side region that is parallel to the bypass middle region in a first direction and contacts the non-display region, and a second bypass side region that is arranged between the bypass middle region and the first bypass side region. The data wires include a first data wire arranged in the first bypass side region, and a second data wire arranged in the second bypass side region. The first dummy wires include a first transmission bypass wire that is electrically connected to the first data wire, and first auxiliary wires that are electrically connected to the second power supply wire. The second dummy wires include a second transmission bypass wire that is paired with the second data wire and electrically connected to the first transmission bypass wire, reset transmission wires that extend from the non-display region to the at least one sub-display region, and second auxiliary wires that are electrically connected to the first auxiliary wires and the second power supply wire.

Among the above light-emitting pixel drivers, one light-emitting pixel driver disposed in the main display area may include a first transistor generating a driving current for driving one of the light-emitting elements, a second transistor electrically connected between one of the data wires and a first electrode of the first transistor, a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor, a first initialization power wire transmitting a first initialization power, a fourth transistor electrically connected between the gate electrode of the first transistor, a fifth transistor electrically connected between the first power wire transmitting the first power and the first electrode of the first transistor, a sixth transistor electrically connected between the second electrode of the first transistor and the one light-emitting element, a second initialization power wire transmitting a second initialization power, a seventh transistor electrically connected between the one light-emitting element, and an eighth transistor electrically connected between a bias power wire transmitting a bias power and the first electrode of the first transistor.

Among the above light-emitting pixel drivers, another light-emitting pixel driver disposed in at least one sub-display area may be electrically connected to another light-emitting element among the light-emitting elements. The other light-emitting pixel driver may further include a reset unit that transmits reset power to the other light-emitting element based on a reset control signal. The circuit layer may further include a reset power supply wiring disposed in the non-display area and transmitting the reset power, and a reset control supply wiring disposed in the non-display area and transmitting the reset control signal. The reset transmission wirings may include a reset power transmission wiring electrically connecting between the reset power supply wiring and the reset power wiring, and a reset control transmission wiring electrically connecting between the reset control supply wiring and the reset control wiring.

Between two data wires that overlap each of two adjacent light-emitting pixel drivers among the above data wires, two second dummy wires that are paired with each of the two data wires among the above second dummy wires and are adjacent to each other may be arranged. The second dummy wires may further include an offset wire that is adjacent to the reset control transmission wire and transmits an offset signal having a polarity opposite to that of the reset control signal.

Specific details of other embodiments are included in the detailed description and drawings.

A display device according to embodiments includes a substrate, a circuit layer disposed on the substrate, and an element layer disposed on the circuit layer. The substrate includes a display area including light-emitting areas, and a non-display area disposed around the display area. The element layer includes light-emitting elements respectively corresponding to the light-emitting areas. The display area includes a main display area in which the light-emitting areas are arranged in parallel with each other, and at least one sub-display area surrounded by the main display area, and at least one sub-display area further includes light-transmitting areas disposed between the light-emitting areas.

The circuit layer includes light-emitting pixel drivers that are electrically connected to the light-emitting elements and arranged in parallel with each other, data wires that transmit data signals to the light-emitting pixel drivers, first dummy wires that extend in a first direction intersecting the data wires, and second dummy wires that extend in parallel with the data wires and are paired with the data wires, respectively.

The second dummy wires include reset transfer wires extending from the non-display area to at least one sub-display area.

Thus, according to embodiments, the display area of the substrate includes at least one sub-display area in which light-emitting areas and light-transmitting areas are arranged.

Since light can be incident under the substrate through the light-transmitting areas of at least one sub-display area, the optical device under the substrate can be operated relatively normally even if it overlaps with at least one sub-display area of the display area.

Accordingly, the display device according to the embodiments can be adapted to an electronic device including an optical device, since the optical device can be driven by at least one sub-display area without including a hole overlapping with the optical device.

The display device according to the embodiments includes reset transmission wires provided as part of the second dummy wires. Accordingly, since the reset transmission wires are not provided separately, the ratio of the area in which the light-emitting pixel drivers are arranged among the display area can be increased. In addition, since the reset transmission wires are part of the second dummy wires, the visibility of the reset transmission wires can be reduced.

The effects according to the embodiments are not limited to the contents exemplified above, and more diverse effects are included in the present specification.

FIG. 1 is a perspective view showing an electronic device according to embodiments.
Figure 2 is an exploded perspective view showing the electronic device of Figure 1.
Figure 3 is a plan view showing the display device of Figure 2.
Figure 4 is a cross-sectional view showing A-A' of Figure 3.
Figure 5 is a layout diagram showing part B of Figure 3.
Figure 6 is a cross-sectional view showing F-F' of Figure 5.
Fig. 7 is an equivalent circuit diagram of a main light-emitting pixel driver electrically connected to one light-emitting element arranged in one of the light-emitting areas arranged in the main display area.
FIG. 8 is a cross-sectional view showing the first transistor, the second transistor, the fourth transistor, and the sixth transistor of FIG. 7 and one light-emitting element.
Figure 9 is a layout diagram showing part C of Figure 3.
Fig. 10 is a cross-sectional view showing G-G' of Fig. 9.
FIG. 11 is an equivalent circuit diagram of a sub-emitting pixel driver electrically connected to one light-emitting element arranged in one of the light-emitting areas arranged in at least one sub-display area.
Fig. 12 is a layout diagram showing part D of Fig. 3.
Fig. 13 is a cross-sectional view showing H-H' of Fig. 12.
FIG. 14 is a layout diagram showing portion E of FIG. 3 according to one embodiment.
FIG. 15 is a layout diagram showing part E of FIG. 3 according to another embodiment.
Figure 16 is a waveform diagram showing the reset control signal of the reset control transmission wiring of Figure 15 and the offset signal of the offset wiring.

The advantages and features of the present invention, and the methods for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and these embodiments are provided only to make the disclosure of the present invention complete and to fully inform a person having ordinary skill in the art to which the present invention belongs of the scope of the invention, and the present invention is defined only by the scope of the claims.

When elements or layers are referred to as being "on" another element or layer, it includes both cases where the other element is directly on top of the other element or layer or intervening layers or other elements. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

Although the terms first, second, etc. are used to describe various components, it is to be understood that these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, it is to be understood that the first component referred to below may also be the second component within the technical concept of the present invention.

The individual features of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or implemented together in a related relationship.

Specific embodiments are described below with reference to the attached drawings.

Fig. 1 is a perspective view showing an electronic device according to embodiments. Fig. 2 is an exploded perspective view showing the electronic device of Fig. 1.

Referring to FIG. 1, an electronic device (10) according to embodiments is a device having a function of displaying an image on a display area. The electronic device (10) may provide portability. For example, the electronic device (10) may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc.

However, the electronic device (10) according to the embodiments is not limited to a portable electronic device, and may be a large device such as a television, a laptop, a monitor, a billboard, or an Internet of Things (IOT).

The electronic device (10) may include a cover window (11) and a lower cover (12) provided as a housing that protects a display device (100 in FIG. 2).

Referring to FIG. 2, the electronic device (10) according to the embodiments may further include a display device (100), a bracket (13), at least one optical device (18), and a main circuit board (14) accommodated between a cover window (11) and a lower cover (12).

Hereinafter, the first direction (DR1) may be a direction parallel to a short side of the electronic device (10) on a plane, i.e., a horizontal direction of the electronic device (10). The second direction (DR2) may be a direction parallel to a long side of the electronic device (10) on a plane, i.e., a vertical direction of the electronic device (10). The third direction (DR3) may be a thickness direction of the electronic device (10).

The electronic device (10) may be formed in a rectangular shape on a plane. For example, the electronic device (10) may have a rectangular shape on a plane having a short side in a first direction (DR1) and a long side in a second direction (DR2). An edge where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the electronic device (10) is not limited to a rectangle, and may be formed in another polygonal, circular, or oval shape.

An electronic device (10) may include a display surface on which a display area (DA) in which an image display is implemented is arranged.

The display device (100) may include a display area (DA) that emits light as a display surface of an electronic device (10), and a non-display area (NDA) arranged around the display area (DA). In addition, the display device (100) may further include a sub-area (SBA of FIG. 3) that protrudes from a portion adjacent to one short edge of the display area (DA) among the non-display area (NDA).

The display device (100) may further include a display driving circuit (200) arranged in a sub-area (SBA), a display circuit board (300) connected to an edge of the sub-area (SBA), a touch driving circuit (400) mounted on the display circuit board (300), and a cable (500) extending from one side of the display circuit board (300).

The display area (DA) may include a main display area (MDA) arranged over most of the display area (DA) and at least one sub display area (SBDA) surrounded by the main display area (MDA) and overlapping with at least one optical device (18).

A cover window (11) can be placed on the display device (100). As a result, one side of the display device (100) from which light is emitted can be covered by the cover window (11).

In other words, the cover window (11) can serve to protect the upper surface of the display device (100).

The cover window (11) may include a transparent light-transmitting portion and an opaque light-blocking portion.

The light-emitting portion may overlap with the display area (DA) of the display device (100) in the third direction (DR3), and the light-shielding portion may overlap with the non-display area (NDA) of the display device (100) in the third direction (DR3).

The cover window (11) may include an upper surface forming the upper surface of the electronic device (10), a left surface forming the left surface of the electronic device (10), and a right surface forming the right surface of the electronic device (10). The left surface of the cover window (11) may extend from the left side of the upper surface, and the right surface may extend from the right side of the upper surface.

The upper surface, left surface, and right surface of the cover window (11) may each include a light-transmitting portion and a light-shielding portion.

The light-emitting portion of the cover window (11) can be placed on most of each of the upper surface, the left surface, and the right surface of the cover window (11).

The light-shielding portion of the cover window (11) can be arranged at the upper edge and lower edge of the upper surface of the cover window (11), the upper edge, left edge, and lower edge of the left surface of the cover window (11), and the upper edge, right edge, and lower edge of the right surface of the cover window (11).

The bracket (13) can be placed at the bottom of the display device (100).

The bracket (13) may include plastic, metal, or both plastic and metal. The bracket (13) may include a first camera hole (CMH1) into which a camera sensor (16) is inserted, a battery hole (BH) for fixing a battery (19), a light-emitting hole (SH) into which at least one optical device (18) is inserted, and a cable hole (CAH) which is a passage for a cable (500) connected to a display circuit board (300).

A main circuit board (14) and a battery (19) can be placed at the bottom of the bracket (13). The main circuit board (14) can be a printed circuit board or a flexible printed circuit board.

A main processor (15), a camera device (16), a main connector (17) and at least one optical device (18) can be mounted on the main circuit board (14).

The camera device (16) may be placed on both the upper and lower surfaces of the main circuit board (14), the main processor (15) may be placed on the upper surface of the main circuit board (14), and the main connector (17) may be placed on the lower surface of the main circuit board (14).

The main processor (15) can control all functions of the electronic device (10).

For example, the main processor (15) can output digital video data to the display driving circuit (200) through the display circuit board (300) so that the display device (100) displays an image. In addition, the main processor (15) can receive touch data including the user's touch coordinates from the touch driving circuit (400), determine whether the user has touched or is in proximity, and then execute an operation corresponding to the user's touch input or proximity input. For example, the main processor (15) can execute an application or perform an operation indicated by an icon touched by the user.

The main processor (15) may be an application processor, a central processing unit, or a system chip made of an integrated circuit.

The camera device (16) processes image frames, such as still images or moving images, obtained by the image sensor in camera mode and outputs them to the main processor (15).

A cable (600) passing through the cable hole (CAH) of the bracket (13) can be connected to the main connector (17). As a result, the main circuit board (14) can be electrically connected to the display circuit board (300).

At least one optical device (18) may include a proximity sensor (18a), a light sensor (18b), an iris sensor (18c), and a second camera sensor (18d).

The proximity sensor (18a), the light sensor (18b), the iris sensor (18c), and the second camera sensor (18d) are arranged on the upper surface of the main circuit board (14) and can be arranged within the light-emitting hole (SH) of the bracket (13).

The proximity sensor (18a) is a sensor for detecting an object approaching the front surface of an electronic device (10). The proximity sensor (18a) may include a light source that outputs light and a light receiving unit that receives light reflected by an object. The proximity sensor (18a) generates a sensing signal corresponding to the amount of light reflected by the object, and the presence or absence of an object positioned close to the front surface of the electronic device (10) can be determined by the sensing signal of the proximity sensor (18a).

The light sensor (18b) is a sensor for detecting the brightness of the front surface of the electronic device (10). The light sensor (18b) may include a resistor whose resistance value changes depending on the brightness of incident light.

The iris sensor (18c) is a sensor for capturing a user's iris. Whether the user is a registered user can be verified based on whether the image captured by the iris sensor (18c) is identical to an iris image previously stored in memory.

The second camera sensor (18d) processes image frames, such as still images or moving images, obtained by the image sensor and outputs them to the main processor (710). The second camera sensor (18d) may be a CMOS image sensor or a CCD sensor. The number of pixels of the second camera sensor (18d) may be less than the number of pixels of the first camera sensor (720), and the size of the second camera sensor (18d) may be smaller than the size of the first camera sensor (720).

The battery (19) may be spaced apart from the main circuit board (14). That is, the battery (19) may not overlap the main circuit board (14) in the third direction (DR3). The battery (19) may be placed within the battery hole (BH) of the bracket (13) in the third direction (DR3).

In addition, the main circuit board (14) may be further equipped with a mobile communication module capable of transmitting and receiving a wireless signal with at least one of a base station, an external terminal, and a server on a mobile communication network. The wireless signal may include various forms of data according to transmission and reception of a voice signal, a video call signal, or text/multimedia message.

The lower cover (12) can be placed under the main circuit board (14) and the battery (19). The lower cover (12) can be fixed by being fastened to the bracket (13). The lower cover (12) can form the upper side, the lower side, and the lower surface of the electronic device (10). The lower cover (12) can include plastic, metal, or both plastic and metal.

The lower cover (12) may include a second camera hole (CMH2) through which the lower surface of the camera device (16) is exposed.

However, the locations of the light hole (SH), the first camera hole (CMH1), and the second camera hole (CMH2) are not limited to the city in Fig. 2.

Figure 3 is a plan view showing the display device of Figure 2.

The display device (100) may include a display area (DA) arranged on a display surface, a non-display area (NDA), and a sub-area (SBA) protruding from one side of the non-display area (NDA).

The display area (DA) can be placed over most of the display surface. The display area (DA) can be placed in the center of the display surface.

A display area (DA) may include a main display area (MDA) arranged over most of the display area (DA), and at least one sub display area (SBDA) surrounded by the main display area (MDA).

At least one sub-display area (SBDA) can overlap with at least one optical device (18 in FIG. 2).

Meanwhile, the display area (DA) may include a bypass area (DEA) positioned on one side adjacent to the sub area (SBA), and a general area (GA) positioned in the remaining area excluding the bypass area (DEA).

The bypass area (DEA) includes a bypass middle area (MDDA) positioned in the center of the first direction (DR1), a first bypass side area (SDA1) that is parallel to the bypass middle area (MDDA) in the first direction (DR1) and borders the non-display area (NDA), and a second bypass side area (SDA2) positioned between the bypass middle area (MDDA) and the first bypass side area (SDA1).

The first bypass side area (SDA1) can be positioned adjacent to the bent edge of the substrate (110) compared to the bypass middle area (MDDA) and the second bypass side area (SDA2).

The first bypass side area (SDA1) and the second bypass side area (SDA2) can be positioned between each of the two sides of the first direction (DR1) of the bypass middle area (MDDA) and the non-display area (NDA).

The general area (GA) may include a general middle area (GMA) connected to a bypass middle area (MDDA) of the bypass area (DEA) in the second direction (DR2), a first general side area (GSA1) connected to a first side area (SDA1) of the bypass area (DEA) in the second direction (DR2), and a second general side area (GSA2) connected to a second side area (SDA2) of the bypass area (DEA) in the second direction (DR2).

A non-display area (NDA) may be positioned outside of a display area (DA). The non-display area (NDA) may be an edge area of a display surface.

The sub-area (SBA) can protrude in the second direction (DR2) from a part of the non-display area (NDA) adjacent to the short side of the display area (DA).

As a part of the sub-area (SBA) is deformed into a curved shape, another part of the sub-area (SBA) can overlap the display area (DA) and the non-display area (NDA) in the third direction (DR3).

The display device (100) may include an upper surface facing the upper surface of the cover window (11), a left surface facing the left surface of the cover window (11), and a right surface facing the right surface of the cover window (11). The left surface of the display device (100) may extend from the left side of the upper surface, and the right surface may extend from the right side of the upper surface.

Each of the upper surface, left surface, and right surface of the display device (100) may include a display area (DA) and a non-display area (NDA).

The display area (DA) can be placed on most of each of the upper surface, the left surface, and the right surface of the display device (100).

The non-display area (NDA) may be positioned at the upper edge and lower edge of the upper surface of the display device (100), the upper edge, left edge, and lower edge of the left surface of the display device (100), and the upper edge, right edge, and lower edge of the right surface of the display device (100).

A display driving circuit (200) may be mounted in a sub-area (SBA) of a display device (100), and a display circuit board (300) may be attached.

One end of the display circuit board (300) can be attached to pads positioned on the lower edge of the sub-area (SBA) of the display device (100) using an anisotropic conductive film.

The display circuit board (300) may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that maintains a flat shape, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

The display driving circuit (200) can output a data signal (Vdata of FIGS. 7 and 11) based on control signals and power voltages supplied from the display circuit board (300).

The display driving circuit (200) is provided as an integrated circuit (IC) and may be mounted on the sub-area (SBA) of the display device (100) in a COG (chip on glass) manner, a COP (chip on plastic) manner, or an ultrasonic manner. However, this is merely an example, and one embodiment is not limited thereto. For example, the display driving circuit (200) may be mounted on a display circuit board (300).

According to one embodiment, a sub-touch driving circuit (400) may be further mounted in the sub-area (SBA) of the display device (100).

Alternatively, as illustrated in FIG. 2, the touch driving circuit (400) may be mounted on the display circuit board (300).

The touch driving circuit (400) can be electrically connected to the touch sensor layer (150 in FIG. 4) of the display device (100).

The touch driving circuit (400) can determine whether a user touches or approaches the touch sensor layer (150) by applying a touch driving signal to the driving wires of the touch sensor layer (150) and detecting changes in charge of electrostatic capacitances based on the touch detection signal received from the detection wires. The user's touch refers to a case where an object, such as a user's finger or a pen, directly contacts the upper surface of a cover window (11) placed on the touch sensor layer. The user's proximity refers to a case where an object, such as a user's finger or a pen, hovers above the upper surface of the cover window (11). The touch driving circuit (400) can output touch data including the user's touch coordinates to the main processor (15).

Figure 4 is a cross-sectional view showing A-A' of Figure 3.

Referring to FIG. 4, a display device (100) according to embodiments may include a substrate (110), a circuit layer (120) disposed on the substrate (110), and an element layer (130) disposed on the circuit layer (120).

In addition, the display device (100) according to the embodiments may further include a sealing layer (140) covering the element layer (130), a touch sensor layer (150) disposed on the sealing layer (140), and a polarizing layer (160) disposed on the touch sensor layer (150).

The substrate (110) may be made of an insulating material such as a polymer resin. For example, the substrate (110) may be made of polyimide. The substrate (110) may be a flexible substrate capable of bending, folding, rolling, etc.

Alternatively, the substrate (110) may be made of an insulating material such as glass.

The substrate (110) may include a display area (DA), a non-display area (NDA), and a sub area (SBA).

The element layer (130) may include light-emitting elements (LE of FIG. 6) respectively arranged in light-emitting areas (EA of FIG. 5 and FIG. 9) of the display area (DA).

The circuit layer (120) may include light-emitting pixel drivers (EPD of FIG. 7, EPD' of FIG. 11) that are electrically connected to the light-emitting elements (LEs) of the element layer (130).

The sealing layer (140) covers the element layer (130) and can extend to the non-display area (NDA) to come into contact with the circuit layer (120). The sealing layer (140) can include a structure in which two or more inorganic films and at least one organic film are alternately laminated.

The touch sensor layer (150) may be disposed on the sealing layer (140) and correspond to the main area (MA). The touch sensor layer (150) may include touch electrodes for detecting the touch of a person or an object.

The polarizing layer (160) is intended to prevent a decrease in image visibility due to external light reflection by blocking external light reflected from the touch sensor layer (150), sealing layer (140), element layer (130), and circuit layer (120) and their interfaces.

A cover window (11) of an electronic device (10) may be placed on a polarizing layer (160). The cover window (11) may be attached to the polarizing layer (160) by a transparent adhesive material such as an optically clear adhesive (OCA) film or an optically clear resin (OCR).

The cover window (11) may be an inorganic material such as glass, or an organic material such as plastic or a polymer material.

By means of this cover window (11), the touch sensor layer (150), sealing layer (140), element layer (130), and circuit layer (120) can be protected from electrical and physical shocks on the display surface.

Fig. 5 is a layout diagram showing part B of Fig. 3. Fig. 6 is a cross-sectional view showing F-F' of Fig. 5.

The display area (DA) of the display device (100) according to the embodiments may include light-emitting areas (EA). In addition, the display area (DA) may further include a non-light-emitting area (NEA of FIG. 6) arranged in a space between the light-emitting areas (EA).

Referring to FIGS. 5 and 6, in the main display area (MDA) which is arranged in most of the display areas (DA), the light-emitting areas (EA) can be arranged in parallel with each other.

The light-emitting areas (EA) may have a rhombus-shaped planar shape or a rectangular planar shape. However, this is merely an example, and the planar shape of the light-emitting areas (EA) according to one embodiment is not limited to the illustration of FIG. 5. That is, the light-emitting areas (EA) may have a polygonal shape, such as a square, a pentagon, a hexagon, or a circular or elliptical planar shape including a curved edge.

The light-emitting areas (EA) may include first light-emitting areas (EA1) that emit light of a first color by a predetermined wavelength band, second light-emitting areas (EA2) that emit light of a second color by a lower wavelength band than the first color, and third light-emitting areas (EA3) that emit light of a third color by a lower wavelength band than the second color.

For example, the first color may be red with a wavelength band of about 600 nm to 750 nm. The second color may be green with a wavelength band of about 480 nm to 560 nm. The third color may be blue with a wavelength band of about 370 nm to 460 nm.

The first light-emitting areas (EA1) and the third light-emitting areas (EA3) can be arranged alternately in at least one of the first direction (DR1) and the second direction (DR2).

The second light-emitting areas (EA2) can be arranged parallel to each other in at least one of the first direction (DR1) and the second direction (DR2).

And, the second light-emitting areas (EA2) can be adjacent to the first light-emitting areas (EA1) and the third light-emitting areas (EA3) in diagonal directions (DR4, DR5) intersecting the first direction (DR1) and the second direction (DR2).

Among these light-emitting areas (EA), pixels (PX) displaying respective brightness and colors can be provided by the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) that are adjacent to each other.

In other words, pixels (PX) can be basic units that display various colors, including white, at a given brightness.

Each of the pixels (PX) can include at least one first light-emitting area (EA1), at least one second light-emitting area (EA2), and at least one third light-emitting area (EA3) that are adjacent to each other. Accordingly, each of the pixels (PX) can display various colors through mixing of light emitted from the first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) that are adjacent to each other.

As illustrated in FIG. 6, the element layer (130) may include light-emitting elements (LEs) respectively arranged in light-emitting areas (EA).

The light emitting element (LE) may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. Alternatively, the light emitting element (LE) may be an inorganic light emitting element having a light emitting layer made of an inorganic semiconductor. Alternatively, the light emitting element (LE) may be a quantum dot light emitting element having a quantum dot light emitting layer. Alternatively, the light emitting element (LE) may be a micro light emitting diode.

Each of the light emitting elements (LEs) may include an anode electrode (131) and a cathode electrode (134) that face each other, and a light emitting layer (133) disposed therebetween.

That is, the element layer (130) may include anode electrodes (131) each corresponding to the light-emitting areas (EA), pixel-defining layers (132) corresponding to the non-light-emitting areas (NEA) and covering the edge of the anode electrode (131), light-emitting layers (133) each disposed on the anode electrodes (131), and cathode electrodes (134) disposed on the light-emitting layers (133) and the pixel-defining layers (132).

Alternatively, each of the light emitting elements (LEs) may further include a first common layer (135) disposed between the anode electrode (131) and the light emitting layer (133), and a second common layer (136) disposed between the light emitting layer (133) and the cathode electrode (134).

An anode electrode (131) can be placed in each of the light-emitting areas (EA).

The anode electrodes (131) of the light-emitting areas (EA) may be electrically connected to the light-emitting pixel drivers (EPD, EPD') of the circuit layer (120), respectively. These anode electrodes (131) may be referred to as pixel electrodes.

The pixel definition layer (132) can be placed in the non-emitting area (NEA) and cover the edge of the anode electrode (131).

The light-emitting layer (133) may be placed on the anode electrode (131). The light-emitting layer (133) may be made of an organic light-emitting material that converts electron-hole pairs into light.

The cathode electrode (134) may be disposed on the light-emitting layers (133) of the light-emitting areas (EA) and the pixel definition layer (132). That is, the cathode electrode (134) may be disposed entirely over the light-emitting areas (EA) and the non-light-emitting area (NEA). This cathode electrode (134) may be referred to as a common electrode.

The sealing layer (140) can be placed on the circuit layer (120) and cover the element layer (130).

The sealing layer (140) may include a first sealing layer (141) disposed on the element layer (130) and made of an inorganic insulating material, a second sealing layer (142) disposed on the first sealing layer (141), overlapping the element layer (130), and made of an organic insulating material, and a third sealing layer (143) disposed on the first sealing layer (141), covering the second sealing layer (142), and made of an inorganic insulating material.

Fig. 7 is an equivalent circuit diagram of a main light-emitting pixel driver electrically connected to one light-emitting element arranged in one of the light-emitting areas arranged in the main display area.

Referring to FIG. 7, the light-emitting pixel driver units (EPDs, EPD' in FIG. 11) of the circuit layer (120) are electrically connected to the light-emitting elements (LEs) of the element layer (130), respectively.

That is, the anode electrode (131) of the light-emitting element (LE) is electrically connected to the light-emitting pixel driver (EPD, EPD'), and a second power supply (ELVSS) having a lower voltage level than the first power supply (ELVDD) can be applied to the cathode electrode (134) of the light-emitting element (LE).

A capacitor (Cel) connected in parallel with the light emitting element (LE) represents a parasitic capacitance between the anode electrode (131) and the cathode electrode (134).

The circuit layer (120) may further include a first power line (VDL) that transmits a first power supply (ELVDD), a first initialization power line (VIL) that transmits a first initialization power supply (VINT), a second initialization power line (VAIL) that transmits a second initialization power supply (VAINT), and a bias power line (VBL) that transmits a bias power supply (VBS).

In addition, the circuit layer (120) may further include a scan write wiring (GWL) for transmitting a scan write signal (GW), a scan initialization wiring (GIL) for transmitting a scan initialization signal (GI), an emission control wiring (ECL) for transmitting an emission control signal (EM), a gate control wiring (GCL) for transmitting a gate control signal (GC), and a bias control wiring (GBL) for transmitting a bias control signal (GB).

Each of the light-emitting pixel drivers (EPDs) (hereinafter referred to as “main light-emitting pixel drivers (EPDs)”) electrically connected to the light-emitting elements (LEs) arranged in the light-emitting areas (EA) of the main display area (MDA) may include a first transistor (T1) that generates a driving current for driving the light-emitting elements (LEs), two or more transistors (T2 to T8) electrically connected to the first transistor (T1), and at least one capacitor (PC1).

The first transistor (T1) is connected in series with the light emitting element (LE) between the first power line (VDL) and the second power line (VSL). That is, the first electrode (e.g., the source electrode) of the first transistor (T1) can be electrically connected to the first power line (VDL) through the fifth transistor (T5). And, the second electrode (e.g., the drain electrode) of the first transistor (T1) can be electrically connected to the anode electrode (131) of the light emitting element (LE) through the sixth transistor (T6).

The first electrode of the first transistor (T1) can be electrically connected to the data line (DL) through the second transistor (T2).

The gate electrode of the first transistor (T1) can be electrically connected to the first power line (VDL) through the first capacitor (PC1). That is, the first capacitor (PC1) can be electrically connected between the gate electrode of the first transistor (T1) and the first power line (VDL).

Accordingly, the potential of the gate electrode of the first transistor (T1) can be maintained by the first power supply (ELVDD) through the first power supply line (VDL).

Accordingly, when the data signal (Vdata) of the data line (DL) is transmitted to the first electrode of the first transistor (T1) through the turned-on second transistor (T2), a voltage difference corresponding to the first power supply (ELVDD) and the data signal (Vdata) can be generated between the gate electrode of the first transistor (T1) and the first electrode of the first transistor (T1).

At this time, when the voltage difference between the gate electrode of the first transistor (T1) and the first electrode of the first transistor (T1), i.e., the gate-source voltage difference, becomes greater than the threshold voltage, the first transistor (T1) is turned on, so that a current can be generated between the drain and source of the first transistor (T1) corresponding to the data signal (Vdata).

And, when the fifth transistor (T5) and the sixth transistor (T6) are turned on, the first transistor (T1) can be connected in series with the light-emitting element (LE) between the first power line (VDL) and the second power line (VSL). Accordingly, the drain-source current of the first transistor (T1) corresponding to the data signal (Vdata) can be supplied as a driving current of the light-emitting element (LE).

Thereby, the light emitting element (LE) can emit light with a brightness corresponding to the data signal (Vdata).

The second transistor (T2) can be connected between the first electrode of the first transistor (T1) and the data line (DL). The second transistor (T3) can be turned on by a scan write signal (GW) of a scan write line (GWL).

A third transistor (T3) can be connected between the gate electrode of the first transistor (T1) and the second electrode of the first transistor (T1). The third transistor (T3) can be turned on by a gate control signal (GC) of a gate control line (GCL).

The fourth transistor (T4) can be connected between the gate electrode of the first transistor (T1) and the first initialization power line (VIL). The fourth transistor (T4) can be turned on by a scan initialization signal (GI) of the scan initialization line (GIL).

The third transistor (T3) and the fourth transistor (T4) can be provided as N-type MOSFETs.

The fifth transistor (T5) can be connected between the first electrode of the first transistor (T1) and the first power line (VDL).

The sixth transistor (T6) can be connected between the second electrode of the first transistor (T1) and the anode electrode of the light emitting element (LE).

The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the emission control signal (EC) of the emission control wiring (ECL).

The seventh transistor (T7) can be connected between the anode electrode of the light emitting element (LE) and the second initialization power line (VAIL). The seventh transistor (T7) can be turned on by a bias control signal (GB) of a bias control line (GBL).

The eighth transistor (T8) can be connected between the first electrode of the first transistor (T1) and the bias power wiring (VBL).

The eighth transistor (T8) can be turned on by the bias control signal (GB) of the bias control wiring (GBL).

Of the first to eighth transistors (T1 to T8), the remaining transistors (T1, T2, T5 to T8), excluding the third transistor (T3) and the fourth transistor (T4), can be provided as P-type MOSFETs.

FIG. 8 is a cross-sectional view showing the first transistor, the second transistor, the fourth transistor, and the sixth transistor of FIG. 7 and one light-emitting element.

Referring to FIG. 8, the circuit layer (120) includes a buffer layer (121) covering a first light-blocking layer (LB1) on a substrate (110), a first semiconductor layer (CH1, S1, D1, CH2, S2, D2, CH6, S6, D6) arranged on the buffer layer (121), a first gate insulating layer (122) covering the first semiconductor layer (CH1, S1, D1, CH2, S2, D2, CH6, S6, D6), a first gate conductive layer (G1, G2, G6) arranged on the first gate insulating layer (122), a second gate insulating layer (123) covering the first gate conductive layer (G1, G2, G6), a second gate conductive layer (CPE, LB2) arranged on the second gate insulating layer (123), a first interlayer insulating layer (124) covering the second gate conductive layer (CPE, LB2), and a first interlayer insulating layer. A second semiconductor layer (CH4, S4, D4) disposed on an insulating layer (124), a third gate insulating layer (125) covering the second semiconductor layer (CH4, S4, D4), a third gate conductive layer (G4) disposed on the third gate insulating layer (125), a second interlayer insulating layer (126) covering the third gate conductive layer (G4), a first source-drain conductive layer (ANDE1, DCE1, GCNE, VIL) disposed on the second interlayer insulating layer (126), a first planarization layer (127) covering the first source-drain conductive layer (ANDE1, DCE1, GCNE, VIL), a second source-drain conductive layer (ANDE2, DCE2) disposed on the first planarization layer (127), a second planarization layer (128) covering the second source-drain conductive layer (ANDE2, DCE2), and a third gate insulating layer (128) disposed on the second planarization layer (128). It may include a source-drain challenge layer (ANDE3, DL).

The first transistor (T1) may include a channel portion (CH1), a source portion (S1), and a drain portion (D1) formed of a first semiconductor layer on a buffer layer (121), and a gate electrode (G1) disposed on a first gate insulating layer (122) and overlapping the channel portion (CH1).

The channel portion (CH1) of the first transistor (T1) may overlap with the first light-shielding layer (LB1) on the substrate (110).

The second transistor (T2) may include a channel portion (CH2), a source portion (S2), and a drain portion (D2) formed of a first semiconductor layer on a buffer layer (121), and a gate electrode (G2) disposed on a first gate insulating layer (122) and overlapping the channel portion (CH2).

The sixth transistor (T6) may include a channel portion (CH6), a source portion (S6), and a drain portion (D6) formed of a first semiconductor layer on a buffer layer (121), and a gate electrode (G6) disposed on a first gate insulating layer (122) and overlapping the channel portion (CH6).

The source portion (S2) of the second transistor (T2) can be electrically connected to the data wiring (DL) through the first data connection electrode (DCE1) and the second data connection electrode (DCE2).

A first data connection electrode (DCE1) is disposed on a second interlayer insulating layer (126) and can be electrically connected to a source portion (S2) of a second transistor (T2) through a first data connection hole (DCH1) penetrating the second interlayer insulating layer (126), the third gate insulating layer (125), the first interlayer insulating layer (124), the second gate insulating layer (123), and the first gate insulating layer (122).

The second data connection electrode (DCE2) is disposed on the first planarization layer (127) and can be electrically connected to the first data connection electrode (DCE2) through a second data connection hole (DCH2) penetrating the first planarization layer (127).

The data wiring (DL) is arranged on the second planarization layer (128) and can be electrically connected to the second data connection electrode (DCE2) through a third data connection hole (DCH3) penetrating the second planarization layer (128).

The drain portion (D2) of the second transistor (T2) can be connected to the source portion (S1) of the first transistor (T1).

The drain portion (D1) of the first transistor (T1) can be connected to the source portion (S6) of the sixth transistor (T6).

The drain portion (D6) of the sixth transistor (T6) can be electrically connected to the anode electrode (131) through the first anode connection electrode (ANDE1), the second anode connection electrode (ANDE2), and the third anode connection electrode (ANDE3).

The first anode connection electrode (ANDE1) is disposed on the second interlayer insulating layer (126) and can be electrically connected to the drain portion (D6) of the sixth transistor (T6) through a first anode connection hole (ANCH1) penetrating the second interlayer insulating layer (126), the third gate insulating layer (125), the first interlayer insulating layer (124), the second gate insulating layer (123), and the first gate insulating layer (122).

The second anode connection electrode (ANDE2) is disposed on the first planarization layer (127) and can be electrically connected to the first anode connection electrode (ANDE1) through a second anode connection hole (ANCH2) penetrating the first planarization layer (127).

The third anode connection electrode (ANDE3) is disposed on the second planarization layer (128) and can be electrically connected to the second anode connection electrode (ANDE2) through a third anode connection hole (ANCH3) penetrating the second planarization layer (128).

The anode electrode (131) is placed on the third flattening layer (129) and can be electrically connected to the third anode connection electrode (ANDE3) through the fourth anode connection hole (ANCH4) penetrating the third flattening layer (129).

The first capacitor (PC1) can be provided by an overlapping area between a capacitor electrode (CPE) disposed on the second gate insulating layer (123) and the gate electrode (G1) of the first transistor (T1).

The fourth transistor (T4) may include a channel portion (CH4), a source portion (S4), and a drain portion (D4) formed of a second semiconductor layer on a first interlayer insulating layer (124), and a gate electrode (G4) disposed on a third gate insulating layer (125) and overlapping the channel portion (CH4).

The channel portion (CH4) of the fourth transistor (T4) may overlap with the second light-shielding layer (LB2) on the second gate insulating layer (123).

The source portion (S4) of the fourth transistor (T4) can be electrically connected to the first initialization power wiring (VIL) on the second interlayer insulating layer (127) through a hole penetrating the second interlayer insulating layer (127) and the third gate insulating layer (125).

The drain portion (D4) of the fourth transistor (T4) can be electrically connected to the gate electrode (G1) of the first transistor (T1) through the gate connection electrode (GCNE) on the second interlayer insulating layer (127).

The gate connection electrode (GCNE) can be electrically connected to the drain portion (D4) of the fourth transistor (T4) through the first gate connection hole (GCH1) penetrating the second interlayer insulating layer (127) and the third gate insulating layer (125).

The gate connection electrode (GCNE) can be electrically connected to the gate electrode (G1) of the first transistor (T1) through a second gate connection hole (GCH2) penetrating the second interlayer insulating layer (127), the third gate insulating layer (125), the first interlayer insulating layer (124), and the second gate insulating layer (123).

Meanwhile, the third transistor (T3) has a structure similar to that of the fourth transistor (T4), and the fifth transistor (T5) and the seventh transistor (T7) have structures similar to that of the second transistor (T2) and the sixth transistor (T6), so redundant descriptions are omitted below.

Fig. 9 is a layout diagram showing portion C of Fig. 3. Fig. 10 is a cross-sectional view showing G-G' of Fig. 9.

The display area (DA) of the display device (100) according to the embodiments may include not only a main display area (MDA), but also at least one sub display area (SBDA) overlapping with the optical devices (18).

Referring to FIG. 9, at least one sub-display area (SBDA) according to embodiments may further include transmissive areas (TRSA) arranged between the emitting areas (EA).

That is, at least one sub-display area (SBDA) may include light-emitting areas (EA) for displaying images and light-transmitting areas (TRSA) for transmitting light of the optical devices (18).

That is, at least one optical device (18) arranged under the substrate (110) overlaps at least one sub-display area (SBDA) including light-transmitting areas (TRSA), and light of the optical device (18) can transmit through the display device (100) through the light-transmitting areas (TRSA). Accordingly, even if the display device (100) according to the embodiments does not include a hole for arranging the optical device (18), the function of the optical device (10) can be implemented relatively normally.

Accordingly, the ratio of the display area (DA) among the display surfaces of the display device (100) can be prevented from being reduced due to the arrangement of the optical device (18), so that the display quality and aesthetics of the display device (100) can be improved.

Each of the light transmitting areas (TRSA) can be adjacent to at least one pixel (PX) in each of the first direction (DR1) and the second direction (DR2).

The width of the light-transmitting area (TRSA) in the first direction (DR1) may be similar to the width of the pixel (PX) in the first direction (DR1), and the width of the light-transmitting area (TRSA) in the second direction (DR1) may be a multiple of the width of the pixel (PX) in the first direction (DR1).

In this case, the light-transmitting areas (TRSA) may be arranged alternately with two or more pixels (PX) in the second direction (DR2). And, the light-transmitting areas (TRSA) may be arranged alternately with at least one pixel (PX) in the first direction (DR1).

To improve the light transmittance of the transmissive area (TRSA), the light emitting pixels (LEs) and the light emitting pixel drivers (EPDs) electrically connected to them do not overlap with the transmissive area (TRSA).

Referring to FIG. 10, the display device (100) according to the embodiments may further include a light transmitting hole (TRH) overlapping with the light transmitting area (TRSA).

To reduce optical loss, a light transmitting hole (TRH) can penetrate the element layer (130) and the circuit layer (120).

In this case, the first sealing layer (141) of the sealing layer (140) can come into contact with the substrate (110) through the transparent hole (TRH).

FIG. 11 is an equivalent circuit diagram of a sub-emitting pixel driver electrically connected to one light-emitting element arranged in one of the light-emitting areas arranged in at least one sub-display area.

Referring to FIG. 11, each of the light-emitting pixel drivers (EPD') electrically connected to the light-emitting elements (LE) arranged in the light-emitting areas (EA) of at least one sub display area (SBDA) (hereinafter, referred to as "sub light-emitting pixel drivers (EPD')") further includes a reset unit (RSTP), and is therefore substantially the same as the main light-emitting pixel driver (EPD), and therefore, a redundant description thereof will be omitted herein.

In the case of light emitting elements (LEs) arranged in at least one sub-display area (SBDA), leakage current may occur due to light incident or emitted by at least one optical device (18), thereby exhibiting different brightness characteristics from the light emitting elements (LEs) of the main display area (MDA).

To prevent this, the sub-emitting pixel driver (EPD') may further include a reset unit (RSTP) that transmits a reset power supply (VRST) of a reset power supply line (VRSL) to the light-emitting element (LE) based on a reset control signal (RSC) of a reset control line (RSCL).

That is, the reset part (RSTP) is electrically connected to the anode electrode (131) of the light-emitting element (LE) together with the sixth transistor (T6) and the seventh transistor (T7), and the potential of the anode electrode (131) can be adjusted to the reset power supply (VRST) according to the reset control signal (RSC).

For example, the reset circuit (RSTP) may include a ninth transistor (T9) electrically connected between the reset power wiring and the light emitting element (LE).

The gate electrode of the ninth transistor (T9) can be electrically connected to the reset control wiring (RSCL).

Due to this reset portion (RSTP), the potential of the anode electrode (131) of the light emitting element (LE) can be adjusted by the reset power supply (VRST). Therefore, the difference in brightness between at least one sub display area (SBDA) and the main display area (MDA) due to light of at least one optical device (18) can be prevented.

Meanwhile, according to embodiments, at least one sub display area (SBDA) is surrounded by the main display area (MDA). Therefore, the display device (100) according to embodiments needs to have a reset transmission line arranged in the main display area (MDA) to transmit a reset power supply (VRST) and a reset control signal (RSC) to at least one sub display area (SBDA).

As described below, according to embodiments, the reset transmission wire may be provided as part of the dummy wires.

Fig. 12 is a layout diagram showing portion D of Fig. 3. Fig. 13 is a cross-sectional view showing H-H' of Fig. 12.

As illustrated in FIG. 3 above, the display area (DA) may include a bypass area (DEA) positioned on one side of the second direction (DR2) adjacent to the sub-area (SBA).

The bypass area (DEA) may include a bypass middle area (MDDA) positioned in the center of the first direction (DR1), a first bypass side area (SDA1) that is parallel to the bypass middle area (MDDA) in the first direction (DR1) and borders the non-display area (NDA), and a second bypass side area (SDA2) positioned between the bypass middle area (MDDA) and the first bypass side area (SDA1).

Referring to FIG. 12, a circuit layer (120) of a display device (100) according to embodiments includes light-emitting pixel drivers (EPD, EPD') electrically connected to light-emitting elements (LE) of element layers (130) respectively disposed in light-emitting areas (EA), data lines (DL) transmitting data signals (Vdata) to the light-emitting pixel drivers (EPD, EPD'), first dummy lines (DML1) extending in a first direction (DR1) intersecting the data lines (DL), and second dummy lines (DML2) extending parallel to the data lines (DL) and paired with the data lines (DL), respectively.

The data wires (DL) and the second dummy wire (DML2) can be extended in the second direction (DR2).

According to embodiments, the circuit layer (120) may further include data supply lines (DSPL) disposed in the non-display area (NDA) and electrically connected to the display driving circuit (200).

Data supply lines (DSPL) electrically connect between the display driver circuit (200) and the data lines (DL).

The data wires (DLs) may include a first data wire (DL1) arranged in a first bypass side area (SDA1), and a second data wire (DL2) arranged in a second bypass side area (SDA2).

The first dummy wires (DML1) may include a first transmission bypass wire (TDEL1) electrically connected to a first data wire (DL1) of the first bypass side area (SDA1).

The second dummy wires (DML2) may be paired with the second data wires (DL2) of the second bypass side area (SDA2) and may include a second transmission bypass wire (TDEL2) electrically connected to the first transmission bypass wire (TDEL1).

The data supply lines (DSPLs) may include a first data supply line (DSPL1) that transmits a data signal of a first data line (DL1), and a second data supply line (DSPL2) that transmits a data signal of a second data line (DL2).

The first data supply wire (DSPL1) can be electrically connected to the second transmission bypass wire (TDEL2).

The first transmission bypass wire (TDEL1) can be electrically connected to the second transmission bypass wire (TDEL2) through the first bypass connection hole (DECH1) and can be electrically connected to the first data wire (DL1) through the second bypass connection hole (DECH2).

Referring to FIG. 13, the second dummy wires (DML2) including the second transmission bypass wire (TDEL2) and the second auxiliary wire (ASL2) can be arranged as the third source-drain conductive layer on the second planarization layer (128), similar to the first data wire (DL1) and the second data wire (DL2).

The first dummy wires (DML1) including the first transmission bypass wire (TDEL1) can be arranged as a conductive layer under the second planarization layer (128).

For example, the first dummy wiring (DML1) including the first transmission bypass wiring (TDEL1) may be arranged as a first source-drain conductive layer on the second interlayer insulating layer (126) and covered with a first planarization layer (127).

In this case, the first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) can penetrate the second flattening layer (128) and the first flattening layer (127).

In this way, according to embodiments, the first data wire (DL1) of the first bypass side area (SDA1) can be electrically connected to the first data supply wire (DSPL1) extended to the second bypass side area (SDA2) through the first transmission bypass wire (TDEL1) and the second transmission bypass wire (TDEL2) arranged in the bypass area (DEA) of the display area (DA).

In other words, even if the first data supply wire (DSPL1) extends only to the second bypass side area (SDA2) relatively adjacent to the sub area (SBA), similar to the second data supply wire (DSPL2), an electrical connection between the first data wire (DL1) and the first data supply wire (DSPL1) can be implemented through the first transmission bypass wire (TDEL1) and the second transmission bypass wire (TDEL2).

Accordingly, since the first data supply wire (DSPL1) does not extend relatively long from the sub-area (SBA) to reach the first bypass side area (SDA1) adjacent to the bent edge of the substrate (110), and the first data supply wire (DSPL1) is not arranged in a part of the non-display area (NDA) between the bent edge of the substrate (110) and the first bypass side area (SDA1), the width of the non-display area (NDA) can be reduced.

The second data supply wire (DSPL2) can be extended to the second bypass side area (SDA2) and directly electrically connected to the second data wire (DL2).

The data lines (DL) may further include a third data line (DL3) arranged in a bypass middle area (MDDA). And, the data supply lines (DSPL) may further include a third data supply line (DSPL3) that transmits a data signal of the third data line (DL3).

The third data supply wire (DSPL3) is extended to the bypass middle area (MDDA) and can be directly electrically connected to the third data wire (DL3).

The first transmission bypass wire (TDEL1) extends from the second transmission bypass wire (TDEL2) to the first data wire (DL1).

The second transmission bypass wire (TDEL2) extends from the first data supply wire (DSPL1) in the non-display area (NDA) to the first transmission bypass wire (TDEL1).

In this way, as the first transmission bypass wire (TDEL1) and the second transmission bypass wire (TDEL2) are arranged in a limited manner in the bypass area (DEA), the ends of the first transmission bypass wire (TDEL1) and the ends of the second transmission bypass wire (TDEL2) are arranged with a predetermined regularity. As a result, the visibility of the first transmission bypass wire (TDEL1) and the second transmission bypass wire (TDEL2) can be improved.

To prevent this, the first dummy wires (DML1) may further include first auxiliary wires (ASL1) in addition to the first transmission bypass wire (TDEL1). And, the second dummy wires (DML2) may further include second auxiliary wires (ASL2) in addition to the second transmission bypass wire (TDEL2).

Two of the first auxiliary wires (ASL1) may be extended from both ends of the first transmission bypass wire (TDEL1) to the non-display area (NDA).

One of the second auxiliary wires (ASL2) may extend from one end of the second transmission bypass wire (TDEL2) in a direction away from the sub area (SBA) to the non-display area (NDA).

Accordingly, some of the second data wires (DL2) may be paired with the second transmission bypass wire (TDEL2), and other parts may be paired with one second auxiliary wire (ASL2) extending from one end of the second transmission bypass wire (TDEL2).

Since the second transmission bypass wire (TDEL2) is placed only in the second bypass side area (SDA2), the first data wire (DL1) of the first bypass side area (SDA1) can be paired with the second auxiliary wire (ASL2) as a whole.

Additionally, the third data wire (DL3) of the bypass middle area (MDDA) can be paired with the second auxiliary wire (ASL2) as a whole.

The circuit layer (120) may further include a first power supply line (VDSPL) and a second power supply line (VSSPL) that respectively transmit a first power supply (ELVDD) and a second power supply (ELVSS) for driving the light emitting elements (LE).

The first power supply wire (VDSPL) and the second power supply wire (VSSPL) can be placed in the non-display area (NDA) and extended to the sub area (SBA).

The first power supply wiring (VDSPL) can be electrically connected to the first power pad for transmitting the first power (ELVDD) among the signal pads arranged in the second sub-area (SB2).

The second power supply wiring (VSSPL) can be electrically connected to a second power pad for transmitting the second power (ELVSS) among the signal pads arranged in the second sub-area (SB2).

The first auxiliary wires (ASL1) can be electrically connected to the second power supply wire (VSSPL).

The second auxiliary wires (ASL2) can be electrically connected to the first auxiliary wires (ASL1) and the second power supply wire (VSSPL).

According to embodiments, the circuit layer (120) may be arranged in the same layer as the data lines (DL) and the second dummy lines (DML2), and may further include a second power auxiliary line (VSAL) that transmits the second power (ELVSS).

According to embodiments, the display device (100) may have a built-in scanning function that detects the curvature of an object in contact with the screen based on a difference in the amount of light reflected from the screen.

To this end, the display device (100) may further include light detection elements dispersed across the display area (DA) and a scanning driving circuit that periodically collects light detection signals of the light detection elements.

The light-sensitive elements can be arranged in light-sensitive areas (ODAs) distributed across a non-emissive area (NEA).

In this case, the circuit layer (120) may further include photodetector pixel drivers (DPDs) electrically connected to the photodetector elements, and readout wirings (ROLs) electrically connected to the photodetector pixel drivers (DPDs).

The lead-out wires (ROL) can extend in a second direction (DR2) parallel to the data wires (DL).

Meanwhile, according to embodiments, the circuit layer (120) may further include a reset power supply line (VRSSPL) and a reset control supply line (RSCSPL) that extend from the sub-area (SBA) and are arranged in the non-display area (NDA) and transmit a reset power supply (VRST) and a reset control signal (RSC), respectively.

And, the second dummy wires (DML2) include reset transmission wires (RSTL of FIGS. 14 and 15) extending from the reset power supply wire (VRSSPL) and the reset control supply wire (RSCSPL) of the non-display area (NDA) to at least one sub-display area (SBDA). That is, the reset transmission wires (RSTL) arranged in the main display area (MDA) and transmitting the reset power supply (VRST) and the reset control signal (RSC) can be provided as part of the second dummy wires (DML2).

FIG. 14 is a layout diagram showing portion E of FIG. 3 according to one embodiment.

Referring to FIG. 14, a circuit layer (120) of a display device (100) according to one embodiment includes second dummy wires (DML2) that are paired with data wires (DL), and the second dummy wires (DML2) include second bypass wires (TDEL2) and second auxiliary wires (ASL2), as well as reset wires (RSTL) that extend from a non-display area (NDA) to at least one sub-display area (SBDA). The reset wires (RSTL) may be arranged in the main display area (MDA).

The circuit layer (120) may further include a reset power line (VRSL) and a reset control line (RSCL) arranged in at least one sub display area (SBDA).

The reset power wiring (VRSL) may include a reset power main wiring (VRSML) positioned adjacent to at least a portion of an edge of the sub display area (SBDA), and reset power sub wirings (VRSSL) extending in a first direction (DR1) from the reset power main wiring (VRSML).

The reset control wiring (RSCL) may include a reset control main wiring (RSCML) positioned adjacent to at least a portion of an edge of a sub display area (SBDA), and reset control sub wirings (RSCSL) extending in a first direction (DR1) from the reset control main wiring (RSCML).

For example, the reset power main line (VRSML) and the reset control main line (RSCML) may be arranged along different portions of the edge of the sub display area (SBDA) and may face each other in the first direction (DR1).

The reset power sub-wires (VRSSL) and the reset control sub-wires (RSCSL) may overlap with the sub-emitting pixel drivers (EPD').

The reset power transmission line (VRSTL), which is provided as part of the second dummy wires (DML2), can electrically connect between the reset power supply line (VRSSPL) of the non-display area (NDA) and the reset power line (VRSL). For example, the reset power main line (VRSML) can extend to the reset power transmission line (VRSTL) in the first direction (DR1), and the reset power transmission line (VRSTL) can be electrically connected to the reset power main line (VRSML).

The reset control transmission line (RSCTL), which is provided as another part of the second dummy wires (DML2), can be electrically connected between the reset control supply wire (RSCSPL) of the non-display area (NDA) and the reset control wire (RSCL). For example, the reset control main wire (RSCML) can be extended to the reset control transmission wire (RSCTL) in the first direction (DR1), and the reset control transmission wire (RSCTL) can be electrically connected to the reset control main wire (RSCML).

As described above, according to one embodiment, in order to transmit the reset power (VRST) and the reset control signal (RSC) to the reset part (RSTP) of the sub-emitting pixel driver (EPD') disposed in at least one sub-display area (SBDA), the reset transmission wires (RSTL) disposed in the main display area (MDA) may be provided as some of the second dummy wires (DML2) including the second transmission bypass wire (TDEL2).

That is, since the reset transfer wires (RSTL) are provided as part of the second dummy wires (DML2) rather than as a separate wiring pattern, the visibility of the reset transfer wires (RSTL) may be reduced. In addition, since a part of the display area (DA) is not allocated to the arrangement of the reset transfer wires (RSTL), the ratio of the area in the display area (DA) where the light-emitting pixel drivers (EPD, EPD') are arranged may increase, which may be advantageous for high resolution.

Meanwhile, according to one embodiment, the reset unit (RSTP) may operate irregularly depending on whether at least one optical device (18) is driven.

That is, the reset control signal (RSC) of the turn-on level can be applied to the reset section (RSTP) irregularly. Accordingly, the polarity of the reset control signal (RSC) can be changed from time to time regardless of the video frame period.

However, since the reset transfer wires (RSTL) are arranged in the main display area (MDA), the light-emitting areas (EA) or light-emitting pixel drivers (EPD) adjacent to the reset control transfer wires (RSCTL) may be affected by the coupling of the reset control signal (RSC). As a result, the luminance characteristics of the light-emitting areas (EA) adjacent to the reset control transfer wires (RSCTL) may be different from those of other light-emitting areas (EA) in the vicinity, which may result in a spot defect.

Accordingly, another embodiment is provided to mitigate a failure caused by a reset control signal (RSC) of a reset control transfer line (RSCTL).

Fig. 15 is a layout diagram showing part E of Fig. 3 according to another embodiment. Fig. 16 is a waveform diagram showing a reset control signal of the reset control transmission wiring of Fig. 15 and an offset signal of the offset wiring.

Referring to FIG. 15, a display device (100) according to another embodiment is substantially the same as the embodiment of FIG. 14, except that the circuit layer (120) is arranged in a non-display area (NDA) and further includes a cancellation signal supply wire (DSTSPL) that transmits a cancellation signal (DST of FIG. 16) having a polarity opposite to that of a reset control signal (RSC), and further includes a cancellation wire (DSTTL) in which second dummy wires (DML2) are adjacent to the reset control transmission wire (RSCTL) and electrically connected to the cancellation signal supply wire (DSTSPL), and therefore, a redundant description thereof is omitted herein.

According to another embodiment, two data wires (DL) that overlap each other with two adjacent light-emitting pixel drivers (EPD, EPD') among the data wires (DL) may be arranged, respectively, with two data wires (DL) among the second dummy wires (DML2) that are paired with each other and are adjacent to each other.

Accordingly, the adjacent reset control transfer wires (RSCTL) and offset wires (DSTTL) can be provided as some of the second dummy wires (DML2).

Referring to FIG. 16, the offset signal (DST) transmitted to the offset signal supply wiring (DSTSPL) and the offset wiring (DSTTL) may have a polarity opposite to that of the reset control signal (RST).

In this way, the reset control signal (RSC) of the reset control transmission line (RSCTL) and the offset signal (DST) of the offset wire (DSTTL) can interfere with each other and be offset. Accordingly, the coupling influence of the reset control signal (RSC) on the light-emitting areas (EA) or light-emitting pixel drivers (EPDs) adjacent to the reset control transmission line (RSCTL) in the main display area (MDA) can be alleviated.

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

10: Electronic devices 100: Display devices
11: Cover window 12: Bottom cover
13: Bracket 14: Main circuit board
200: Display driving circuit 300: Display circuit board
400: Touch driving circuit
DA: Display area NDA: Non-display area
SBA: Sub-area
MDA: Main display area SBDA: Sub display area
DEA: Bypass Area MDDA: Bypass Middle Area
SDA1, SDA2: 1st and 2nd bypass side areas
GA: General Area GMA: General Middle Area
GSA1, GSA2: 1st and 2nd general side areas
110: substrate 120: circuit layer
130: Light-emitting element layer 140: Sealing layer
150: Touch sensor layer 160: Polarizing layer
EA: Emitting area NEA: Non-emitting area
PX: Pixel EPD: Main Emitting Pixel Driver
TRSA: Transmitting area TRH: Transmitting hole
EPD': Sub-emitting pixel driver RSTP: Reset unit
RSC: Reset control signal RSCL: Reset control wiring
VRST: Reset Power VRSL: Reset Power Wiring
DL1, DL2, DL3: 1st, 2nd, 3rd data lines
DSPL1, DSPL2, DSPL3: 1st, 2nd, 3rd data supply wiring
TDEL1, TDEL2: 1st and 2nd transmission bypass wiring
DML1, DML2: 1st, 1st dummy wiring
ASL1, ASL2: 1st and 2nd auxiliary wiring
VDSPL, VSSPL: Primary and secondary power supply wiring
RSCSPL: Reset control supply wiring VRSSPL: Reset power supply wiring
RSCTL: Reset control transfer wiring VRSTL: Reset power transfer wiring
DSTTL: Offset wiring DST: Offset signal

Claims (15)

A substrate including a display area including luminous areas and a non-display area arranged around the display area;
A circuit layer disposed on the above substrate; and
A device layer is disposed on the circuit layer and includes light-emitting devices respectively corresponding to the light-emitting areas,
The above display area includes a main display area in which the light-emitting areas are arranged in parallel with each other, and at least one sub display area surrounded by the main display area,
wherein said at least one sub-display area further includes light-transmitting areas arranged between said light-emitting areas,
The above circuit layer is,
Light-emitting pixel driver units electrically connected to the light-emitting elements of the above-described element layer, respectively;
Data wires for transmitting data signals to the above light-emitting pixel drivers;
First dummy wires extending in a first direction intersecting the above data wires; and
Including second dummy wires extending parallel to the above data wires and paired with each of the above data wires,
A display device wherein the second dummy wires include reset transmission wires extending from the non-display area to the at least one sub-display area. In the first paragraph,
Further comprising a display driving circuit that outputs data signals of the above data wires,
The above circuit layer further includes data supply wires arranged in the non-display area and electrically connected to the display driving circuit,
The bypass region on one side of the above display region includes a central bypass middle region, a first bypass side region that is parallel to the bypass middle region in the first direction and contacts the non-display region, and a second bypass side region that is arranged between the bypass middle region and the first bypass side region.
The above data wires include a first data wire arranged in the first bypass side region, and a second data wire arranged in the second bypass side region,
The above first dummy wires include a first transmission bypass wire electrically connected to the first data wire,
The second dummy wires further include a second transmission bypass wire that is paired with the second data wire and electrically connected to the first transmission bypass wire,
Among the above data supply wires, the first data supply wire that transmits the data signal of the first data wire is electrically connected to the first data wire through the first transmission bypass wire and the second transmission bypass wire,
A display device in which a second data supply wire, which transmits a data signal of the second data wire among the above data supply wires, is directly electrically connected to the second data wire. In the second paragraph,
The circuit layer further includes a first power supply wire and a second power supply wire, which respectively transmit a first power supply and a second power supply for driving the light-emitting elements.
The above first dummy wires further include first auxiliary wires electrically connected to the second power supply wires,
A display device wherein the second dummy wires further include second auxiliary wires electrically connected to the first auxiliary wires and the second power supply wires. In the third paragraph,
Two of the first auxiliary wires among the above first auxiliary wires extend from both sides of the first transmission bypass wire to the non-display area,
A display device in which one of the second auxiliary wires extends from one side of the second transmission bypass wire to the non-display area. In the third paragraph,
Among the above light-emitting pixel drivers, one light-emitting pixel driver arranged in the main display area is
A first transistor for generating a driving current for driving one of the light-emitting elements;
A second transistor electrically connected between one of the data wires and the first electrode of the first transistor;
A third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor;
A fourth transistor electrically connected between a first initialization power wiring for transmitting a first initialization power and the gate electrode of the first transistor;
A fifth transistor electrically connected between the first power wire transmitting the first power and the first electrode of the first transistor;
A sixth transistor electrically connected between the second electrode of the first transistor and the one light-emitting element;
A second initialization power wire transmitting the second initialization power, and a seventh transistor electrically connected between said one light-emitting element; and
A display device comprising a bias power wiring for transmitting bias power, and an eighth transistor electrically connected between the first electrode of the first transistor. In clause 5,
A display device wherein at least one of the sub-display areas overlaps at least one of the optical devices disposed under the substrate. In Article 6,
Among the above light-emitting pixel drivers, another light-emitting pixel driver arranged in at least one sub-display area is
electrically connected to another light emitting element among the above light emitting elements,
A display device further comprising a reset section for transmitting reset power to the other light emitting element based on a reset control signal. In Article 7,
The above reset unit includes a ninth transistor electrically connected between the reset power wiring and the other light emitting element,
A display device in which the gate electrode of the ninth transistor is electrically connected to the reset control wiring. In Article 7,
The above circuit layer is,
Reset power supply wiring arranged in the above non-display area and transmitting the reset power; and
Further comprising a reset control supply wiring arranged in the non-display area and transmitting the reset control signal;
The above reset transmission wires are,
A reset power transmission wiring electrically connecting between the above reset power supply wiring and the above reset power wiring; and
A display device including a reset control transmission wiring electrically connecting between the reset control supply wiring and the reset control wiring. In Article 9,
A display device in which two second dummy wires, which are paired with the two data wires among the second dummy wires and are adjacent to each other, are arranged between two data wires that overlap with two adjacent light-emitting pixel drivers among the above data wires. In Article 10,
A display device wherein the second dummy wires further include an offset wire adjacent to the reset control transmission wire and transmitting an offset signal having a polarity opposite to that of the reset control signal. A substrate including a display area including luminous areas and a non-display area arranged around the display area;
A circuit layer disposed on the above substrate; and
A device layer is disposed on the circuit layer and includes light-emitting devices respectively corresponding to the light-emitting areas,
The above display area is,
A main display area in which the above light-emitting areas are arranged parallel to each other; and
comprising at least one sub-display area surrounded by the main display area and overlapping at least one optical device disposed under the substrate;
The above circuit layer is,
Light-emitting pixel driver units electrically connected to the light-emitting elements of the above-described element layer, respectively;
Data wires for transmitting data signals to the above light-emitting pixel drivers;
First dummy wires extending in a first direction intersecting the above data wires;
Second dummy wires extending parallel to the above data wires and respectively paired with the above data wires;
Data supply wires arranged in the non-display area and electrically connected to a display driving circuit that outputs data signals of the data wires; and
It includes a first power supply wire and a second power supply wire that respectively transmit a first power supply and a second power supply for driving the above light-emitting elements,
The bypass region on one side of the above display region includes a central bypass middle region, a first bypass side region that is parallel to the bypass middle region in the first direction and contacts the non-display region, and a second bypass side region that is arranged between the bypass middle region and the first bypass side region.
The above data wires include a first data wire arranged in the first bypass side region, and a second data wire arranged in the second bypass side region,
The above first dummy wires are,
a first transmission bypass wire electrically connected to the first data wire; and
Including first auxiliary wires electrically connected to the second power supply wires,
The above second dummy wires
A second transmission bypass wire paired with the second data wire and electrically connected to the first transmission bypass wire;
Reset transmission wires extending from the non-display area to at least one sub-display area; and
A display device including second auxiliary wires electrically connected to the first auxiliary wires and the second power supply wires. In Article 12,
Among the above light-emitting pixel drivers, one light-emitting pixel driver arranged in the main display area is
A first transistor for generating a driving current for driving one of the light-emitting elements;
A second transistor electrically connected between one of the data wires and the first electrode of the first transistor;
A third transistor electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor;
A fourth transistor electrically connected between a first initialization power wiring for transmitting a first initialization power and the gate electrode of the first transistor;
A fifth transistor electrically connected between the first power wire transmitting the first power and the first electrode of the first transistor;
A sixth transistor electrically connected between the second electrode of the first transistor and the one light-emitting element;
A second initialization power wire transmitting the second initialization power, and a seventh transistor electrically connected between said one light-emitting element; and
A display device comprising a bias power wiring for transmitting bias power, and an eighth transistor electrically connected between the first electrode of the first transistor. In Article 13,
Among the above light-emitting pixel drivers, another light-emitting pixel driver arranged in at least one sub-display area is
electrically connected to another light emitting element among the above light emitting elements,
Further comprising a reset section for transmitting reset power to the other light emitting element based on a reset control signal,
The above circuit layer is,
Reset power supply wiring arranged in the above non-display area and transmitting the reset power; and
Further comprising a reset control supply wiring arranged in the non-display area and transmitting the reset control signal;
The above reset transmission wires are,
A reset power transmission wiring electrically connecting between the above reset power supply wiring and the above reset power wiring; and
A display device including a reset control transmission wiring electrically connecting between the reset control supply wiring and the reset control wiring. In Article 14,
Between the two data wires that overlap each of the two adjacent light-emitting pixel drivers among the above data wires, two second dummy wires that are paired with each of the two data wires among the above second dummy wires and are adjacent to each other are arranged.
A display device wherein the second dummy wires further include an offset wire adjacent to the reset control transmission wire and transmitting an offset signal having a polarity opposite to that of the reset control signal.

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