KR20240118633A - Memory device and an operation method thereof - Google Patents

Abstract

A memory device and method of operating the same are disclosed. A memory device according to an embodiment includes a memory bank unit including a plurality of memory banks, an operation unit including a plurality of PIM blocks, and a memory that supplies a row address and a column address to the memory bank unit. It includes a controller, and the memory bank includes an array of memory cells arranged in a plurality of rows and a plurality of columns, a row buffer that stores data in a row corresponding to a row address among the plurality of rows, and data stored in the row buffer. Among them, it includes a selection unit for selecting first data and second data corresponding to the column address, and a data path between the selection unit and the PIM block so that each of the first data and second data can be independently transmitted to the PIM block. data path) can be connected.

Description

Memory device and method of operation thereof {MEMORY DEVICE AND AN OPERATION METHOD THEREOF}

Embodiments relate to memory devices and methods of operating the same.

The use of Deep Neural Network (DNN) is leading to an industrial revolution based on AI (Artificial Intelligence). Convolution Neural Network (CNN), one of the deep neural networks, is widely used in various application fields such as image and signal processing, object recognition, and computer vision that mimic the human optic nerve. A convolutional neural network can be configured to perform a MAC operation (Multiple and Accumulation) that repeats multiplication and addition using a very large number of matrices. When executing a convolutional neural network application using general-purpose processors, the amount of computation is very large, but simple operations such as the dot product of two vectors and the MAC (Multiplication and Accumulation) operation, which accumulates and adds the values, are difficult to perform. This can be performed through Processing In Memory (PIM).

The background technology described above is possessed or acquired by the inventor in the process of deriving the disclosure of the present application, and cannot necessarily be said to be known technology disclosed to the general public before this application.

A memory device according to an embodiment includes a memory bank unit including a plurality of memory banks; and an operation unit including a plurality of PIM blocks, wherein the memory bank includes: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer storing data of a row corresponding to a row address among the plurality of rows; and a selection unit for selecting first data and second data corresponding to a column address from among the data stored in the row buffer, through a first data path connected between the selection unit and the PIM block. First data may be transmitted to the PIM block, and the second data may be transmitted to the PIM block through a second data path connected between the selection unit and the PIM block.

The column address includes a first sub-column address and a second sub-column address, a first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address. Group bits may be assigned.

The selection unit includes a first selector that selects the first data based on the first sub-column address; and a second selector that selects the second data based on the second sub-column address.

The first selector and the PIM block may be connected to the first data path, and the second selector and the PIM block may be connected to the second data path.

The PIM block receives the first data as a first operand from the first selector, receives the second data as a second operand from the second selector, and performs an operation between the first operand and the second operand. can be performed.

The first operand and the second operand may be arranged as a pair in the data of the row corresponding to the row address.

The PIM block may receive the first operand and the second operand simultaneously.

A memory device according to an embodiment includes a third multiplexer that receives the first row group bits or the second row group bits as a control signal and outputs the first data or the second data to the outside of the memory device. may further include.

The PIM block includes registers; and a fourth multiplexer that selects one of the data stored in the register and the first data output from the selection unit as a first operand.

The PIM block includes a fifth multiplexer that selects one of data stored in the register and second data output from the selection unit as a second operand; and an operator that performs an operation between the first operand and the second operand.

The memory bank unit may include a plurality of dynamic random access memory (DRAM) banks.

A memory device according to an embodiment includes a sixth multiplexer that receives first data corresponding to each of the plurality of memory banks and transmits a first operand to the PIM block; and a seventh multiplexer that receives second data corresponding to each of the plurality of memory banks from the plurality of memory banks and transmits a second operand to the PIM block.

A method of operating a memory device including a memory bank and a PIM block according to an embodiment includes receiving a row address and a column address; storing row data corresponding to the row address in a row buffer of the memory bank; selecting first data and second data corresponding to the column address from data stored in the row buffer; transferring the first data to the PIM block through a first data path connected between the memory bank and the PIM block; and transmitting the second data to the PIM block through a second data path connected between the memory bank and the PIM block.

The column address includes a first sub-column address and a second sub-column address, a first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address. Group bits may be assigned.

The selecting step includes selecting the first data based on the first sub-column address; and selecting the second data based on the second sub-column address.

A method of operating a memory device according to an embodiment includes receiving the first data as a first operand from the PIM block; In the PIM block, receiving the second data as a second operand; and performing an operation between the first operand and the second operand in the PIM block.

The first operand and the second operand may be arranged as a pair in the data of the row corresponding to the row address.

The PIM block may receive the first operand and the second operand simultaneously.

A method of operating a memory device according to an embodiment further includes receiving the first column group bit or the second column group bit as a control signal and outputting the first data or the second data to the outside of the memory device. It can be included.

The memory bank may include a plurality of dynamic random access memory (DRAM) banks.

A memory device according to an embodiment includes an operator including a logic circuit that performs data operations; Memory cells arranged in a plurality of rows and a plurality of columns; a row buffer storing row data of the memory cells; a first path connecting the row buffer and the operator; a second path independent of the first path connecting the row buffer and the operator; and a selection unit that selects first data stored in the row buffer and transmits it to the first path, and selects second data different from the first data stored in the row buffer and transmits it to the second path. .

A memory device according to an embodiment includes a first multiplexer connected to the first path; a second multiplexer connected to the second path; and a register connected to the first multiplexer and the second multiplexer.

The register may be connected to the first path and not connected to the second path.

The memory device according to one embodiment may further include a multiplexer connected to the first path and the second path and outputting the first data or the second data to the outside of the memory device.

The selection unit may include a first row decoder that selects the first data and a second row decoder that selects the second data.

FIG. 1 is a block diagram of a memory device according to an embodiment.
FIG. 2A is a diagram for explaining the operation of several compared memory systems.
Figure 2b is a schematic block diagram of a memory bank connected to a PIM block according to one embodiment.
Figure 2c is a circuit diagram showing an example of a DRAM cell according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating the structure of a column address for simultaneously inputting a pair of operands into an operator according to an embodiment.
FIG. 4A is a diagram illustrating operations when a memory device receives a PIM command, according to an embodiment.
FIG. 4B is a diagram for explaining operations when a memory device receives a regular command according to an embodiment.
FIG. 5A is a diagram illustrating an example of a memory device including a PIM block according to an embodiment.
FIG. 5B is a diagram illustrating an example of a memory device in which a plurality of memory banks and a PIM block are connected, according to an embodiment.
FIG. 6 is a flowchart illustrating a method of operating a memory device according to an embodiment.

Specific structural or functional descriptions disclosed in this specification are merely illustrative for the purpose of explaining embodiments according to technical concepts, and actual implementations may have various other appearances and are limited only to the embodiments described in this specification. It doesn't work.

Terms such as first or second may be used to describe various components, but these terms should be understood only for the purpose of distinguishing one component from another component. For example, a first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between. Expressions that describe the relationship between components, such as “between” and “immediately between” or “neighboring to” and “directly adjacent to”, should be interpreted similarly.

Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to designate the presence of implemented features, numbers, steps, operations, components, parts, or combinations thereof, but are not intended to indicate the presence of one or more other features or numbers. It should be understood that this does not preclude the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art. Terms as defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings they have in the context of the related technology, and unless clearly defined in this specification, should not be interpreted in an idealized or overly formal sense. No.

Embodiments may be implemented in various types of products such as personal computers, laptop computers, tablet computers, smart phones, televisions, smart home appliances, intelligent vehicles, kiosks, and wearable devices. Hereinafter, embodiments will be described in detail with reference to the attached drawings. The same reference numerals in each drawing indicate the same members.

FIG. 1 is a block diagram of a memory device according to an embodiment.

Referring to FIG. 1, as shown in FIG. 1, an embodiment of the present disclosure provides a Processing In Memory (PIM) memory system. The memory system supports additional computing resources to be incorporated into memory device 110. The memory system includes a memory device 110 coupled to a host processor 150, such as a graphics processing unit (GPU) or a central processing unit (CPU). The memory device 110 can accelerate elementwise calculations between vectors and can be applied to AI (Artificial Intelligence) and HPC (High-Performance Computing) applications, and the memory system can be used in servers and mobile devices. It can be applied to .

In one embodiment, memory device 110 includes memory die 120. The host processor 150 may include a host memory controller 160 (or host controller) to interface with the memory device 110. However, the present disclosure is not limited to this. For example, the host memory controller 160 may be separate from the host processor 150 (e.g., as a separate die or the same die as the host processor 160). Alternatively, the memory device 110 may include a memory controller, and the memory die 120 may be connected to the memory controller through an internal memory bus.

Host memory controller 160 may be configured to coordinate execution of instructions from host processor 150. Instructions can include both regular instructions and PIM instructions. For example, regular instructions (e.g., traditional load (read) and store (write) functions rather than in-memory function instructions) may be transmitted by the host memory controller 160 and executed in a conventional manner. . For example, regular instructions include an instruction to store data received through an external bus in the memory die 120 and an instruction to retrieve data from the memory die 120 and transmit the data to the host processor 150 through an external bus. may include.

In some embodiments, regular instructions and PIM instructions may include storing data in a specific location of the memory die 120 (eg, a specific page of a specific bank). These data may include two different operands, where each operand may include multiple values (e.g., floating point or integer values).

An aspect of an embodiment of the present disclosure relates to the use of in-memory computing (IMC), and the memory system according to an embodiment includes a memory bank unit 121 and an operation unit 123 inside the memory die 120. may include. Some comparable memory systems (e.g., process near memory (PNM)) include operators external to the memory die (e.g., an arithmetic logic unit (ALU)), in which the operators do not pass through an external bus, but rather have access to data stored on the memory die. It is shared by the memory banks of the memory die so that operations (e.g., arithmetic operations) can be performed.

Some aspects of embodiments of the present disclosure relate to accelerating memory boundary operations by integrating the operation unit 123 into the memory bank unit 121 of the memory die 120. For example, the operation unit 123 may be on the same physical semiconductor die as the memory bank unit 121 holding data. The calculation unit 123 and the PIM block may be associated so that computing can be performed on data stored in the memory bank.

Before describing the structure of a memory system according to an embodiment, several compared memory systems will be described with reference to FIG. 2A.

Referring to Figure 2A, some compared memory systems may include a multiplexer 281, a register 283, a multiplexer 285, and an operator 287. The multiplexer 281 may select a subset of columns from among the row data stored in the row buffer and supply it to the register 283, and the register 283 may be connected to the first operand input of the operator 287.

The memory system of FIG. 2A may perform a first vector operation between two operands of the register 283 or a second vector operation between an operand of the register 283 and an operand of a memory bank.

The index of the register 283 operates as predefined in the instruction register in the PIM block, but the address where the operand in the memory bank is located can be input by the host memory controller 160. . Therefore, only one operation block size (e.g., operand unit) can be moved from the memory bank to the PIM block.

For example, to perform a first vector operation, in the first phase (or step, cycle), the register 283 loads the first operand and two In the second step, the first and second operands may be input to the operator 287. In the case of the second operand, it can be selected as an input to the operator 287 through the multiplexer 285.

To perform the second vector operation, in the first step, the register 283 loads the first operand, and in the second step, the first operand and the second operand stored in the row buffer are used by the operator 287. It can be entered as input. In other words, in the memory system of FIG. 2A, because vector operations are performed in two stages, only half of the performance (utilization) of the operator may be used.

Figure 2b is a schematic block diagram of a memory bank connected to a PIM block according to one embodiment. The content described with reference to FIG. 1 can be applied equally to FIG. 2C, and overlapping content can be omitted.

Referring to FIG. 2B, the memory bank 210 according to one embodiment may include a cell array 220, a row buffer 230, and a selection unit 240. Hereinafter used '. wealth', '. Terms such as 'unit' refer to a unit that processes a function or operation, and can be implemented through hardware, software, or a combination of hardware and software.

The memory bank 210 may include an array of memory cells (hereinafter referred to as cell array 220) arranged in rows and columns (or pages and columns). For example, the memory bank 210 may include DRAM cells arranged in n rows (or pages) and m columns (where n and m are natural numbers). A plurality of bit lines (e.g., B1 to Bm) (bitlines) extend along the column direction, and a plurality of row enable lines (e.g., R1 to Rn) (row enable lines) extend along the row direction of the array. and can cross bit lines. Each bit line can be connected to every cell in that column (for example, every cell in the ith column of the array is connected to bit line Bi). Likewise, each row enable line (e.g., R1 through Rn) can be connected to each memory cell in the corresponding row (e.g., the jth row of an array or all cells in a page are connected to a row enable line (Rj)). . A row of memory cells in memory bank 210 may also be referred to as a memory page.

Figure 2c is a circuit diagram showing an example of a DRAM cell according to an embodiment of the present invention.

Referring to Figure 2C, each DRAM memory cell typically has a capacitor 212 for storing data voltages (e.g., bit values, where each capacitor can store a voltage representing a 0 bit or a voltage representing a 1 bit). It can be modeled as including a switch 214 for transmitting the data voltage to the capacitor 212) and a capacitor 212. The particular DRAM cell shown in Figure 2C may be in the ith column and jth row of the array. Accordingly, the switch 214 of the DRAM cell shown in FIG. 2B may be connected between the ith bit line Bi and one terminal of the capacitor 212, and the other terminal of the capacitor 212 may be connected to ground. As shown in FIG. 2C, the gate electrode of the switch 214 of the DRAM cell is connected to the j-th row enable line (Rj), so that when the switch 214 is turned on, the capacitor 212 is connected to the bit line ( Bi) can be connected. However, memory cells according to one embodiment are not limited to DRAM memory cells. Depending on the design, various types of memory cells can be adopted.

Referring again to FIG. 2B, the memory bank 210 includes a row decoder (not shown) connected to row enable lines (e.g., R1 to Rn), and the row decoder is, for example, connected to the host memory controller 160. It may be configured to supply a row enable signal to a specified one of the row enable lines corresponding to the row address supplied from. When writing or reading data to a specific row of a memory cell, the row decoder may supply a row enable signal to the row enable line corresponding to the specific row. When writing data, a voltage corresponding to the data to be written may be supplied to a bit line (eg, B1 to Bm) while a specific row is enabled.

Similarly, when reading data from a specific row of the cell array 220, voltages corresponding to the voltages stored in the capacitor 212 are transmitted along the bit lines (e.g., B1 to Bm) and stored in the row buffer 230. can be read by Row buffer 230 may be connected to a corresponding one of the bit lines. For example, in one embodiment, cell array 220 may include 8,192 corresponding bit lines (e.g., bit lines B1 through B8192) coupled to 8,192 column and 8,192 corresponding row buffers 230. (For example, each page can store 8,192 bits or 8 Kibit of data). The row buffer 230 can store data read from the current row (or page) until it is erased by a “precharge” command.

The selection unit 240 may include a plurality of selectors. The selector is a device that selects data corresponding to a column address from among the data stored in the row buffer 230, and may be, for example, a multiplexer. However, the selector is not limited to a multiplexer, and the selector may include various devices that can select specific data from a plurality of data. Below, for convenience of explanation, the description will be based on the selection unit 240 composed of a first multiplexer and a second multiplexer. Furthermore, the selection unit 240 may also be referred to as a column decoder.

The selection unit 240 may be used to select a subset of the data string using the first multiplexer and the second multiplexer, and to perform computing on the data, the read data is in- It can be fed into a memory computing (IMC) module.

As will be described in detail below, the selection unit 240 according to one embodiment may be used to control the data flow for a plurality (e.g., two) inputs of the operator 270 (e.g., the operator 270 ) as the first and second operands for ). The selection unit may select a plurality of data (eg, first data and second data) corresponding to a column address from among the data stored in the row buffer 230. The operator 270 performs an operation (eg, a vector multiplication operation), and the operation result may be written back to the cell array 220 or transmitted to the host processor through the IO module. For example, the operator 270 may include a floating point unit (FPU), an ALU, an adder, or a multiplier.

The memory device according to one embodiment allows the operands to receive only one bank address without the need to receive multiple (e.g., two) bank addresses in the memory bank 210 separately multiple times (e.g., twice). Can operate in sets (e.g. pairs). By using multiple data paths between the memory bank 210 and the PIM block 260, multiple operands can be simultaneously input to the input of the operator 270 and calculated at once. Below, the structure of a column address for operands to operate as a set (e.g., a pair) will be described with reference to FIG. 3.

FIG. 3 is a diagram illustrating the structure of a column address for simultaneously inputting a set of operands to an operator according to an embodiment.

In order to simultaneously use a plurality of operands (e.g., two) in a memory bank (e.g., 210 in FIG. 2A), a plurality of operands (e.g., two) for the operands to be used in the PIM operation are required by the memory controller (e.g., 140 in FIG. 1). For example: You must be able to receive two (2) column addresses at once. Below, for convenience of explanation, the description will be based on a memory device that processes two operands simultaneously.

When performing a vector operation between the first operand of the memory bank and the second operand of the memory bank, if the row address and the column address within the row address are received from the memory controller, acceleration performance is improved because the operand address is received twice. may be difficult to see. To solve this problem, the column address according to one embodiment may pre-divide a plurality of column data existing in the same row into a plurality of groups (e.g., two).

Referring to FIG. 3, the column address supplied from the memory controller is divided into a first sub-column address and a second sub-column address, and the column data corresponding to each can be used as two operands of the PIM block operation. The first sub-column address and the second sub-column address may be referred to as Column Address 0 and Column Address 1, respectively.

A first column group bit may be assigned to the first sub-column address, and a second column group bit may be assigned to the second sub-column address. For example, '0' may be assigned to the first sub-column address as a first column group bit, and '1' may be assigned to the second sub-column address as a second column group bit.

For example, after the column address is divided into a first sub-column address and a second sub-column address, a first column group bit may be added to a specific position (e.g., most significant bit) of the first sub-column address, and a second column group bit may be added. A second row group bit may be added to a specific position (e.g., most significant bit) of the sub-row address.

For example, if the nth row size is 4,056 bits and the column size is 256 bits, there can be 16 columns in one row. Columns 0 to 7 can be used as inputs for the first data path, and columns 8 to 15 can be used as inputs for the second data path.

After the column address is divided into the first sub-column address and the second sub-column address, the first sub-column address enters the input of the first multiplexer of the selection section, and the second sub-column address enters the input of the second multiplexer of the selection section. You can. The first data (e.g., column 0 data) corresponding to the first sub-column address can be paired with the second data (e.g., column 8 data) corresponding to the second sub-column address and used as an operand of a vector operation. there is. Likewise, (1,9), (2, 10) … (7, 15) can be used as a pair as operands for vector operations (in (a,b), a refers to data in column a and b refers to data in column b). As above, in order to use a column data pair included in the same row as an operand, two operands to be used for the operation can be placed in one row. Through this, the Row Buffer Hit Ratio can be increased, which may lead to additional performance improvement by reducing the time of repeated PRE-ACT.

In FIG. 3 , for convenience of explanation, the description is based on a memory device that processes two operands simultaneously, but the memory device according to an embodiment is not limited thereto and can process a plurality of operands (e.g., two) simultaneously. there is.

For this purpose, the column address supplied from the memory controller is divided into the first sub-column address to the n-th sub-column address (n is a natural number of 2 or more), and the corresponding column data is used as n operands of the PIM block operation. You can. The first to nth sub-column addresses may be referred to as Column Address 0 to Column Address n, respectively.

After the column address is divided into the first sub-column address to the n-th sub-column address, the first sub-column address enters the input of the first multiplexer of the selection section, and the n-th sub-column address enters the input of the n-th multiplexer of the selection section. You can. The first data corresponding to the first sub-column address to the n-th data corresponding to the n-th sub-column address can be used as an operand of a vector operation as one set.

FIG. 4A is a diagram illustrating operations when a memory device receives a PIM command, according to an embodiment.

Referring to FIG. 4A, a memory device (e.g., memory device 110 of FIG. 1) according to an embodiment receives a PIM instruction from a host processor (e.g., host processor 150 of FIG. 1) and executes the corresponding instruction. execution can be adjusted.

The memory device may receive the row address and allocate the first sub-row address and the second sub-row address to the first multiplexer 240 and the second multiplexer 250, respectively.

The first multiplexer 240 may select first data corresponding to the first sub-column address among the row data included in the row buffer 230, and the second multiplexer 250 may select the first data corresponding to the first sub-column address from among the row data included in the row buffer 230. Among the row data, the second data corresponding to the second sub-column address can be selected. Hereinafter, the first multiplexer 240 may be referred to as a first selector, and the second multiplexer 250 may be referred to as a second selector.

The first multiplexer 240 and the PIM block 260 may be connected to the first data path 201, and the second multiplexer 250 and the PIM block 260 may be connected to the second data path 203. More specifically, the first multiplexer 240 and the operator 270 of the PIM block 260 are connected to the first data path 201, so that the first data is used as the first operand in the operator 270 of the first multiplexer 240. ), and the second multiplexer 250 and the operator 270 of the PIM block 260 are connected to the second data path 203, so that the second data is transmitted from the second multiplexer 250 as the second operand. It may be transmitted to the calculator 270. In other words, the memory device according to one embodiment receives one column address and simultaneously and independently transfers the first and second operands to the operator 270, thereby reducing the memory internal bandwidth as shown in FIG. 2C. It can be used twice as much as memory devices.

FIG. 4B is a diagram illustrating an operation of a memory device when receiving a regular command, according to an embodiment.

Referring to FIG. 4B, a memory device (e.g., memory device 110 of FIG. 1) according to an embodiment receives a regular instruction from a host processor (e.g., host processor 150 of FIG. 1) and executes the corresponding instruction. execution can be adjusted.

The memory device may receive the row address and allocate the first sub-row address and the second sub-row address to the first multiplexer 240 and the second multiplexer 250, respectively. The first multiplexer 240 may select first data corresponding to the first sub-column address among the row data included in the row buffer 230, and the second multiplexer 250 may select the first data corresponding to the first sub-column address from among the row data included in the row buffer 230. Among the row data, the second data corresponding to the second sub-column address can be selected.

The memory device according to one embodiment may further include a third multiplexer 280 for data movement with external channels. The third multiplexer 280 may receive the first row group bits or the second row group bits as a control signal and output the first data or second data to the outside of the memory device. For example, when the third multiplexer 280 receives the first row group bits as a control signal, it can output the first data to the outside of the memory device, and when it receives the second row group bits as a control signal, The second data may be output to the outside of the memory device.

FIG. 5A is a diagram illustrating an example of a memory device including a PIM block according to an embodiment. Contents described with reference to FIGS. 4A to 4B can be applied equally to FIG. 5A and overlapping content can be omitted.

Referring to FIG. 5A, the PIM block according to one embodiment may include a register 310, a fourth multiplexer 320, a fifth multiplexer 330, and an operator 340.

The memory system according to one embodiment may perform a vector operation between two operands of a memory bank as described above. Furthermore, the memory system can perform operations between matrices and vectors. Because the sizes of matrices and vectors are different, operations between matrices and vectors cannot be performed at once. Accordingly, the memory system according to one embodiment can perform operations between matrices and vectors by storing vectors in the register 310 and transferring them one by one from the register 310 to the operator 340.

A first operation between two operands of the register 310 (e.g., an operation between vectors) and a second operation between an operand of the register 310 and an operand of a memory bank (e.g., an operation between a matrix and a vector) may also be performed. You can. For example, to perform the first vector operation, the operator 340 may receive the first and second operands of the register 310 through the fourth multiplexer 320. To perform the second operation, operator 340 may receive the first operand of the register 310 through the fourth multiplexer 320 and the second operand of the row buffer through the fifth multiplexer 330. You can.

FIG. 5B is a diagram illustrating an example of a memory device in which a plurality of memory banks and a PIM block are connected, according to an embodiment. Contents described with reference to FIGS. 4A to 4B can be applied equally to FIG. 5B, and overlapping content can be omitted.

Referring to FIG. 5B, the first multiplexer 240-1 and the second multiplexer 250-1 of the memory bank 210-1 may be connected to the sixth multiplexer 510 and the seventh multiplexer 520, respectively. Likewise, the first multiplexer 240-n and the second multiplexer 250-n of the memory bank 210-n may be connected to the sixth multiplexer 510 and the seventh multiplexer 520, respectively.

The frequency of the PIM block 260 may be increased by connecting a plurality of memory banks 210-1 to 210-n with the PIM block 260, and through this, operations (e.g., inter-vector operations, matrix and It can accelerate inter-vector operations or inter-matrix operations.

It is necessary to increase the amount of data input in accordance with the frequency of the PIM block 260, but since it is difficult to increase the frequency of the memory core, the amount of input sent from the memory banks 210-1 to 210-n to the PIM block 260 is increased. Parallelism can be increased.

FIG. 6 is a flowchart illustrating a method of operating a memory device according to an embodiment.

For convenience of explanation, steps 610 to 640 are described as being performed using the memory device 110 shown in FIG. 1 . However, these steps 610-640 may be used via any other suitable electronic device and within any suitable system.

Furthermore, although the operations of FIG. 6 may be performed in the order and manner shown, the order of some operations may be changed or some operations may be omitted without departing from the spirit and scope of the illustrated embodiment. Multiple operations shown in Figure 6 may be performed in parallel or simultaneously.

In step 610, the memory device 110 according to one embodiment may receive a row address and a column address. The column address includes a first sub-column address and a second sub-column address, and a first column group bit may be assigned to the first sub-column address, and a second column group bit may be assigned to the second sub-column address.

In step 620, the memory device 110 according to an embodiment may store data of the row corresponding to the row address in the row buffer of the memory bank.

In step 630, the memory device 110 according to an embodiment may select first data and second data corresponding to the column address from data stored in the row buffer. The memory device 110 may select first data based on the first sub-row address and select second data based on the second sub-row address.

In step 640, the memory device 110 according to an embodiment may transmit first data to the PIM block through a first data path connected between the memory bank and the PIM block.

In step 650, the memory device 110 according to an embodiment may transmit second data to the PIM block through a second data path connected between the memory bank and the PIM block.

The first data and the second data can be transmitted to the PIM block at the same time. The PIM block may receive first data as a first operand, receive second data as a second operand, and perform an operation between the first and second operands.

The embodiments described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, the devices, methods, and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, and a field programmable gate (FPGA). It may be implemented using a general-purpose computer or a special-purpose computer, such as an array, programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and software applications that run on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include a plurality of processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include computer programs, code, instructions, or combinations thereof, that configure a processing unit to operate as desired, or that operate independently or collectively. You can command. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. , or may be permanently or temporarily embodied in a transmitted signal wave. Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on a computer-readable recording medium.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. Computer-readable media may include program instructions, data files, data structures, etc., singly or in combination. Program instructions recorded on the medium may be specially designed and configured for the embodiment or may be known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -Includes optical media (magneto-optical media) and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc. Examples of program instructions include machine language code, such as that produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

Although the embodiments have been described with limited drawings as described above, those skilled in the art can apply various technical modifications and variations based on the above. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (26)

A memory bank section including a plurality of memory banks; and
A computational unit comprising multiple PIM blocks;
Including,
The above memory bank
An array of memory cells arranged in multiple rows and multiple columns;
A row buffer for storing data of a row corresponding to a row address among the above plurality of rows; and
A selection unit that selects the first data and the second data corresponding to the column address among the data stored in the above row buffer.
Including,
A memory device, wherein the first data is transferred to the PIM block through a first data path connected between the selection unit and the PIM block, and the second data is transferred to the PIM block through a second data path connected between the selection unit and the PIM block.
According to paragraph 1,
The above column address is
Includes a first sub-column address and a second sub-column address,
A first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address.
According to paragraph 2,
The selection section
a first selector that selects the first data based on the first sub-column address; and
A second selector for selecting the second data based on the second sub-column address.
A memory device containing.
According to paragraph 3,
The first selector and the PIM block are connected to the first data path, and the second selector and the PIM block are connected to the second data path.
According to paragraph 3,
The PIM block is
Receiving the first data as a first operand from the first selector, receiving the second data as a second operand from the second selector, and performing an operation between the first operand and the second operand, memory device.
According to clause 5,
In the data of the row corresponding to the above row address,
A memory device in which the first operand and the second operand are arranged as a pair.
According to clause 5,
The PIM block is
A memory device that simultaneously receives the first operand and the second operand.
According to paragraph 2,
A third multiplexer that receives the first row group bits or the second row group bits as a control signal and outputs the first data or the second data to the outside of the memory device.
A memory device further comprising:
According to paragraph 1,
The PIM block is
register; and
A fourth multiplexer that selects one of the data stored in the register and the first data output from the selection unit as the first operand.
A memory device containing a.
According to clause 9,
The PIM block is
a fifth multiplexer that selects one of the data stored in the register and the second data output from the selection unit as a second operand; and
An operator that performs an operation between the first operand and the second operand
A memory device containing.
According to paragraph 1,
The memory bank unit is
A memory device comprising a plurality of dynamic random access memory (DRAM) banks.
According to paragraph 1,
a sixth multiplexer that receives first data corresponding to each of the plurality of memory banks from the plurality of memory banks and transmits a first operand to the PIM block; and
A seventh multiplexer that receives second data corresponding to each of the plurality of memory banks from the plurality of memory banks and delivers a second operand to the PIM block
A memory device further comprising:
In a method of operating a memory device including a memory bank and a PIM block,
Receiving a row address and a column address;
storing row data corresponding to the row address in a row buffer of the memory bank;
selecting first data and second data corresponding to the column address from data stored in the row buffer;
transferring the first data to the PIM block through a first data path connected between the memory bank and the PIM block; and
Passing the second data to the PIM block through a second data path connected between the memory bank and the PIM block.
A method of operating a memory device comprising:
According to clause 13,
The above column address is
Includes a first sub-column address and a second sub-column address,
A method of operating a memory device, wherein a first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address.
According to clause 14,
The above selection steps are
selecting the first data based on the first sub-column address; and
Selecting the second data based on the second sub-column address
A method of operating a memory device, including.
According to clause 15,
In the PIM block, receiving the first data as a first operand;
In the PIM block, receiving the second data as a second operand; and
In the PIM block, performing an operation between the first operand and the second operand.
A method of operating a memory device further comprising:
According to clause 16,
The data of the row corresponding to the above row address includes
A method of operating a memory device in which the first operand and the second operand are arranged as a pair.
According to clause 16,
The PIM block is
A method of operating a memory device, receiving the first operand and the second operand simultaneously.
According to clause 14,
Receiving the first column group bit or the second column group bit as a control signal and outputting the first data or the second data to the outside of the memory device.
A method of operating a memory device further comprising:
According to clause 13,
The memory bank is
A method of operating a memory device comprising a plurality of dynamic random access memory (DRAM) banks.
A computer program combined with hardware and stored in a medium to execute the method of any one of claims 13 to 20.
an operator including logic circuits that perform data operations;
Memory cells arranged in a plurality of rows and a plurality of columns;
a row buffer storing row data of the memory cells;
a first path connecting the row buffer and the operator;
a second path independent of the first path connecting the row buffer and the operator; and
A selection unit that selects first data stored in the row buffer and transmits it to the first path, and selects second data different from the first data stored in the row buffer and transmits it to the second path.
A memory device containing a.
According to clause 22,
a first multiplexer connected to the first path;
a second multiplexer connected to the second path; and
Registers connected to the first multiplexer and the second multiplexer
A memory device further comprising
According to clause 23,
The register is coupled to the first path and not coupled to the second path.
According to clause 22,
The memory device further includes a multiplexer connected to the first path and the second path and outputting the first data or the second data to the outside of the memory device.
According to clause 22,
The selection unit includes a first row decoder that selects the first data and a second row decoder that selects the second data.

Images