KR20240097129A - Display apparatus - Google Patents

Abstract

A display device according to an embodiment of the present specification includes a substrate including a display area on which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of sub-pixels disposed in the display area on the substrate and connected to each of the plurality of sub-pixels. is disposed in each of the plurality of sub-pixels on the first low-potential power wiring and the substrate, and includes a plurality of light-emitting elements including an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer, and the cathode is a plurality of first 1 Can be electrically connected to at least some of the low-potential power wiring.

Description

DISPLAY APPARATUS}

This specification relates to a display device, and more specifically, to a display device that can improve heat generation and reduced lifespan by minimizing voltage loss.

Currently, as we enter the full-fledged information age, the field of display devices that visually display electrical information signals is developing rapidly, and research is continuing to develop performance such as thinner, lighter, and lower power consumption for various display devices.

Among these various display devices, organic light emitting display devices are self-emissive display devices, and unlike liquid crystal displays, they do not require a separate light source and can be manufactured in a lightweight and thin form. In addition, organic light emitting display devices are not only advantageous in terms of power consumption due to low voltage driving, but also have excellent color rendering, response speed, viewing angle, and contrast ratio (CR), and are being studied as next-generation displays.

The problem that this specification aims to solve is to provide a display device that minimizes voltage loss by minimizing the distance that current moves through the cathode.

Another problem that the present specification aims to solve is to provide a display device with improved heat generation and reduced lifespan by reducing the power voltage of low-potential power wiring.

Another problem that this specification aims to solve is to provide a display device that can implement a narrow bezel by minimizing the bezel area.

The tasks of this specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present specification includes a substrate including a display area on which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of sub-pixels disposed in the display area on the substrate and connected to each of the plurality of sub-pixels. is disposed in each of the plurality of sub-pixels on the first low-potential power wiring and the substrate, and includes a plurality of light-emitting elements including an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer, and the cathode is a plurality of first 1 Can be electrically connected to at least some of the low-potential power wiring.

A display device according to another embodiment of the present specification includes a substrate including a display area and a non-display area on which a plurality of sub-pixels are arranged, a plurality of first low-potential power lines disposed in the display area and connected to each of the plurality of sub-pixels. and a plurality of light emitting elements disposed in each of the plurality of sub-pixels, including an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer, wherein the cathode is disposed on at least a portion of the plurality of first low-potential power wirings. It may extend to directly contact and be electrically connected to the first low-potential power wiring.

Specific details of other embodiments are included in the detailed description and drawings.

According to an embodiment of the present specification, since the cathode and a plurality of low-potential power wirings are directly connected within the display area, the travel distance of the current moving through the cathode can be minimized.

According to an embodiment of the present specification, when driving a display device, the voltage loss of the low-potential power wiring is minimized and the power voltage of the low-potential power wiring is reduced, so that the display device can be driven with low power.

According to an embodiment of the present specification, the low-potential power wiring disposed along the outside of the non-display area can be omitted, so the bezel can be minimized.

The effects according to the present specification are not limited to the contents exemplified above, and further various effects are included within the present specification.

1 is a plan view of a display device according to an embodiment of the present specification.
Figure 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification.
FIG. 3A is an enlarged plan view of a display device according to an embodiment of the present specification.
FIG. 3B is a cross-sectional view taken along line AA' of FIG. 1 and BB' of FIG. 3A.
4 is a plan view of a display device according to another embodiment of the present specification.
FIG. 5A is a plan view of a display device according to another embodiment of the present specification.
FIG. 5B is a cross-sectional view taken along line C-C' of FIG. 5A.
Figure 6 is a cross-sectional view of a display device according to another embodiment of the present specification.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present specification is complete and are within the scope of common knowledge in the technical field to which the present specification pertains. It is provided to fully inform those who have the scope of the invention.

The shape, area, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present specification, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. In cases where a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other elements.

Additionally, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical idea of the present specification.

Like reference numerals refer to like elements throughout the specification.

The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

Each feature of the various embodiments of the present specification can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, the present specification will be described with reference to the drawings.

1 is a plan view of a display device according to an embodiment of the present specification. For convenience of explanation, in FIG. 1, among the various components of the display device 100, a substrate 110, a display area (AA), a non-display area (NA), a plurality of sub-pixels (SP), and a first low-potential power supply wiring are shown. (AL1) and the second low-potential power supply wiring (AL2) are shown.

Referring to FIG. 1 , the display device 100 according to an embodiment of the present specification includes a display area (AA) and a non-display area (NA).

The substrate 110 is a support member for supporting other components of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. Additionally, the substrate 110 may be made of a polymer or plastic such as polyimide (PI), or may be made of a material with flexibility.

The display area AA is disposed in the center of the substrate 110 and may be an area where an image is displayed in the display device 100. A display element and various driving elements for driving the display element may be disposed in the display area AA. For example, the display element may include at least one light-emitting element, and the driving element may include a transistor, a capacitor, and a wiring for driving the display element, but are not limited thereto.

A plurality of pixels including a plurality of sub-pixels SP may be disposed in the display area AA. A pixel is the minimum unit that constitutes a screen, and each of the plurality of pixels may include a light emitting element and a driving element. At this time, the driving element may include a switching transistor, a driving transistor, etc. The driving element may be electrically connected to signal lines such as gate lines and data lines connected to the gate driver and data driver disposed in the non-display area (NA), but is not limited thereto.

Each of the plurality of pixels may include a plurality of sub-pixels (SP) that emit light of different wavelengths. For example, the plurality of sub-pixels SP may include at least three of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, but is not limited thereto.

The non-display area (NA) may be disposed in a peripheral area of the substrate 110 . The non-display area (NA) may be an area where images are not displayed. The non-display area (NA) may be arranged to surround the display area (AA). Various components for driving a plurality of pixels arranged in the display area AA may be disposed in the non-display area NA. For example, a driver IC, a driver circuit, a signal wire, a flexible film, etc. that supply signals for driving a plurality of pixels may be disposed. At this time, the driving IC may include a gate driver (or gate driving circuit), a data driver (or data driving circuit), etc. Gate drivers and data drivers can be implemented with thin film transistors (TFTs). The driving IC and driving circuit are GIP (Gate In Panel) method, COF (Chip On Film) method, TAB (Tape Automated Bonding) method, TCP (Tape Carrier Package) method, COG (Chip On Glass) method, or substrate 110. It may be arranged in an integrated manner, but is not limited to this.

Meanwhile, although not shown in FIG. 1, a plurality of pads may be disposed in the non-display area (NA). For example, a plurality of pads may be disposed on the lower end of the substrate 110. Additionally, a driving IC, a driving circuit, or a flexible film may be connected to the plurality of pads. Accordingly, the plurality of pads can drive the display device 100 by receiving various driving signals and supplying the driving signals to the plurality of pixels.

The plurality of pads include, for example, a data pad for supplying a data voltage to the sub-pixel (SP), a high-potential power pad for supplying a high-potential voltage to the anode of the light-emitting device, and a low-potential voltage to the cathode of the light-emitting device. It may include, but is not limited to, a low-potential power pad for supplying power.

A plurality of first low-potential power supply lines AL1 are disposed in the display area AA on the substrate 110 . The plurality of first low-potential power lines AL1 may be connected to each of the plurality of sub-pixels SP to supply a low-potential voltage to the cathodes of the plurality of sub-pixels SP. For example, as shown in FIG. 1, the plurality of first low-potential power wires AL1 extend from the display area AA to the non-display area NA and are connected to a plurality of pads disposed on the lower part of the substrate 110. You can. Accordingly, the plurality of first low-potential power lines AL1 may receive low-potential voltages from a plurality of pads and may supply the low-potential voltages to the plurality of sub-pixels SP, but are not limited thereto.

Meanwhile, in FIG. 1, only four first low-potential power wires (AL1) are shown for convenience of explanation, but the first low-potential power wires (AL1) may be provided in plural numbers to correspond to a plurality of sub-pixels (SP). You can.

A second low-potential power line AL2 is disposed in the non-display area NA on the substrate 110 along the outer edge of the display area AA. The second low-potential power wiring (AL2) may be connected to a plurality of first low-potential power wiring (AL1). Referring to FIG. 1, a plurality of first low-potential power wires (AL1) and a second low-potential power wire (AL2) may be connected to the upper part of the substrate 110, and may be connected to a plurality of pads at the lower end of the substrate 110. Each may be connected, but is not limited to this.

Referring to FIG. 1 , the width of the second low-potential power wiring (AL2) may be wider than the width of the first low-potential power wiring (AL1). In this case, the second low-potential power wiring (AL2) may have a lower resistance value than the first low-potential power wiring (AL1) for the same voltage, but is not limited thereto.

Hereinafter, a pixel circuit among the plurality of sub-pixels SP will be described in more detail with reference to FIG. 2 .

Figure 2 is a circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification. FIG. 2 exemplarily shows a pixel circuit among the plurality of sub-pixels SP of FIG. 1 .

Referring to FIG. 2, the pixel circuit includes first to sixth transistors (T1, T2, T3, T4, T5, T6) and a capacitor (Cst).

The first transistor T1 is connected to the second scan wire and can be controlled by the second scan voltage SCAN2 supplied through the second scan wire. The first transistor T1 may be electrically connected between the data line supplying the data voltage Vdata and the capacitor Cst. When the second scan voltage SCAN2 at the turn-on level is applied through the second scan line, the first transistor T1 transfers the data voltage Vdata from the data line to the capacitor Cst. This first transistor T1 may be referred to as a switching transistor that controls the timing at which the data voltage Vdata is applied to the capacitor Cst.

The second transistor T2 may be electrically connected between the high-potential power wiring supplied with the high-potential power supply voltage EVDD and the fifth transistor T5. And the gate electrode of the second transistor (T2) may be electrically connected to the capacitor (Cst). The second transistor T2 may be referred to as a driving transistor that controls the brightness of the light-emitting device 120 by controlling the current flowing to the light-emitting device 120 according to the voltage applied to the gate electrode.

The third transistor T3 can be controlled by the first scan voltage SCAN1 supplied through the first scan line. The third transistor T3 may be electrically connected between the gate electrode and the drain electrode or between the gate electrode and the source electrode of the second transistor T2, depending on the type of the third transistor T3.

In an embodiment, the second transistor T2, which is a driving transistor, must control the current flowing to the light emitting device 120 according to the data voltage Vdata applied to the sub-pixel SP, but is disposed in each sub-pixel SP. A deviation in the threshold voltage of the second transistor T2 may cause a deviation in luminance of the light emitting devices 120 disposed in each sub-pixel SP.

As the third transistor T3 is disposed in the pixel circuit, the threshold voltage of the second transistor T2 may be compensated. At this time, the third transistor T3 may be referred to as a compensation transistor. For example, when the first scan voltage (SCAN1) that turns on the third transistor (T3) is applied, the voltage obtained by subtracting the threshold voltage of the second transistor (T2) from the high potential power supply voltage (EVDD) is 2 is applied to the gate electrode of the transistor (T2). The data voltage (Vdata) is applied to the capacitor (Cst) while the high-potential power supply voltage (EVDD) with the reduced threshold voltage is applied to the gate electrode of the second transistor (T2), thereby reducing the threshold voltage of the second transistor (T2). Voltage can be compensated.

In FIG. 2, the third transistor T3 is shown as receiving different scan voltages (SCAN1, SCAN2) from different scan lines than the first transistor T1. However, the third transistor T3 and the first transistor T1 may be connected to the same scan wire and receive the same scan voltage (SCAN1 or SCAN2), but is not limited thereto.

The fourth transistor T4 may be electrically connected to the capacitor Cst and an initialization signal line to which the initialization voltage Vini is supplied. The fourth transistor T4 can be controlled by the emission control voltage (EM) supplied through the emission control signal line. When the light emission control voltage (EM) at the turn-on level is applied through the light emission control signal wire, the fourth transistor (T4) initializes the voltage of the capacitor (Cst) or sets the data voltage (Vdata) applied to the capacitor (Cst). It can be slowly discharged and a current according to the data voltage (Vdata) can flow through the light emitting device 120.

The fifth transistor T5 is electrically connected between the second transistor T2 and the light emitting device 120 and can be controlled by the emission control voltage EM supplied through the emission control signal line. The fifth transistor (T5) turns on with the data voltage (Vdata) applied to the capacitor (Cst) and the high-potential power supply voltage (EVDD) with a compensated threshold voltage applied to the gate electrode of the second transistor (T2). When the light emission control voltage (EM) at the -on level is applied, it is turned on to allow current to flow through the light emitting device 120.

The sixth transistor (T6) is electrically connected between the initialization signal wire to which the initialization voltage (Vini) is supplied and the anode of the light emitting device 120, and is activated by the first scan voltage (SCAN1) supplied through the first scan wire. It can be controlled. When the first scan voltage (SCAN1) at the turn-on level is applied through the first scan wire, the sixth transistor (T6) is connected to the anode of the light emitting device 120 or the second transistor (T2) with an initialization voltage (Vini). The node between the fifth transistor T5 can be initialized.

The capacitor Cst may be a storage capacitor Cst that stores the voltage applied to the gate electrode of the second transistor T2, which is a driving transistor. Here, the capacitor Cst is electrically connected between the gate electrode of the second transistor T2 and the anode of the light emitting device 120. Accordingly, the capacitor Cst can store the difference between the voltage of the gate electrode of the second transistor T2 and the voltage supplied to the anode of the light emitting device 120.

Hereinafter, the sub-pixel SP of the display device 100 according to an embodiment of the present specification will be described in more detail with reference to FIGS. 3A and 3B.

FIG. 3A is an enlarged plan view of a display device according to an embodiment of the present specification. FIG. 3B is a cross-sectional view taken along A-A' in FIG. 1 and a cross-sectional view taken along B-B' in FIG. 3A. 3A and 3B, the display device 100 according to an embodiment of the present specification includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, and a passivation layer ( 114), planarization layer 115, bank 116, high potential power supply wiring (PL), plurality of scan wiring (SL), data wiring (DL), first low potential power supply wiring (AL1), second low potential wiring It includes a power wiring (AL2), an initialization signal wiring (IL), a light emission control signal wiring (EL), a fifth transistor (T5), a light emitting element 120, and a connection electrode (CE). In FIG. 3A , for convenience of explanation, only the anode 121 of the light emitting device 120 is shown, and the anode 121 is hatched to indicate a plurality of sub-pixels (SP). And in FIG. 3B, for convenience of explanation, only the fifth transistor T5 among the plurality of transistors T1, T2, T3, T4, T5, and T6 and the capacitor Cst of the pixel circuit is shown.

Referring to FIG. 3A, the plurality of sub-pixels (SP) are individual units that emit light, and a light-emitting element 120 is disposed in each of the plurality of sub-pixels (SP). The plurality of sub-pixels SP include a first sub-pixel (SP1), a second sub-pixel (SP2), and a third sub-pixel (SP3) that emit light of different colors. For example, the first sub-pixel SP1 may be a blue sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a red sub-pixel, but are not limited thereto.

In an embodiment, the plurality of first sub-pixels SP1 may be arranged in a plurality of columns. That is, the plurality of first sub-pixels SP1 may be arranged in the same column. Additionally, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be arranged between each of the plurality of columns in which the plurality of first sub-pixels SP1 are arranged. For example, a plurality of first sub-pixels (SP1) may be arranged in one column, and a plurality of second sub-pixels (SP2) and third sub-pixels (SP3) may be arranged in an adjacent column. Additionally, the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 may be alternately arranged in the same column. However, in this specification, the plurality of sub-pixels (SP) are described as including the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), but the plurality of sub-pixels (SP) The arrangement, number, and color combination may vary depending on the design, but is not limited thereto.

In an embodiment, the plurality of first low-potential power wires AL1 may be arranged to extend in the column direction between the plurality of sub-pixels SP. The plurality of first low-potential power supply wires (AL1) are wires that transmit the low-potential power supply voltage (EVSS) to each of the plurality of sub-pixels (SP). The plurality of first low-potential power wiring lines AL1 are disposed between the plurality of sub-pixels SP. For example, each of the plurality of first low-potential power lines AL1 is between the first sub-pixel SP1 and the second sub-pixel SP2 and between the first sub-pixel SP1 and the third sub-pixel SP3. It may be placed in, but is not limited to.

In an embodiment, the plurality of high-potential power wiring lines PL may be arranged to extend in the same column direction as the plurality of first low-potential power wiring lines AL1. The plurality of high-potential power supply wires (PL) are wires that transmit the high-potential power supply voltage (EVDD) to each of the plurality of sub-pixels (SP). A plurality of high-potential power wiring lines (PL) may be arranged adjacent to a plurality of low-potential power wiring lines (AL1). Some of the plurality of high-potential power lines PL may be arranged to overlap the first sub-pixel SP1. Another part of the plurality of high-potential power lines PL may be arranged to overlap the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 arranged in the same column, but is not limited thereto.

In an embodiment, the plurality of data wires DL may be arranged to extend in the same column direction as the plurality of first low potential power wires AL1 and the plurality of high potential power wires PL. The plurality of data lines DL are lines that transmit the data voltage Vdata to each of the plurality of sub-pixels SP. The plurality of data wires DL may be arranged adjacent to the plurality of high potential power wires PL. Some of the plurality of data lines DL may be arranged to overlap the first sub-pixel SP1. Another part of the plurality of data lines DL may be arranged to overlap the plurality of second sub-pixels SP2 and the plurality of third sub-pixels SP3 arranged in the same column, but is not limited thereto.

In an embodiment, the plurality of scan lines SL may be arranged to extend in the row direction. The plurality of scan wires (SL) are wires that transmit scan voltages (SCAN1, SCAN2) to each of the plurality of sub-pixels (SP). The plurality of scan wires SL include a first scan wire SL1 and a second scan wire SL2. The first scan line SL1 is arranged to extend in the row direction between the second sub-pixel SP2 and the third sub-pixel SP3, and the second scan line SL2 extends horizontally across the third sub-pixel SP3. It can be arranged to extend in the row direction.

In an embodiment, the plurality of initialization signal wires IL may be arranged between the plurality of sub-pixels SP in a form extending in the same row direction as the plurality of scan wires SL. The plurality of initialization signal wires IL are wires that transmit the initialization voltage Vini to each of the plurality of sub-pixels SP. Each of the plurality of initialization signal lines IL may be disposed between the second sub-pixel SP2 and the third sub-pixel SP3. A plurality of initialization signal wires IL may be disposed between the first scan wire SL1 and the second scan wire SL2.

In an embodiment, the plurality of emission control signal wires EL may be arranged to extend in the row direction in the same manner as the plurality of scan wires SL. The plurality of emission control signal wires (EL) are wires that transmit the emission control voltage (EM) to each of the plurality of sub-pixels (SP). The plurality of emission control signal wires EL may be arranged adjacent to the plurality of second scan wires SL2. A plurality of emission control signal wires EL may be arranged to extend in the row direction across the third sub-pixel SP3. A second scan wire (SL2) may be disposed between the plurality of emission control signal wires (EL) and the plurality of initialization signal wires (IL).

Referring to FIG. 3B , the substrate 110 is a support member for supporting other components of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. Additionally, the substrate 110 may be made of a polymer or plastic such as polyimide (PI), or may be made of a material with flexibility.

A buffer layer 111 is disposed on the substrate 110. The buffer layer 111 can reduce penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of, for example, a single layer or a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of transistor, but is not limited thereto.

The fifth transistor T5 is disposed on the buffer layer 111. The fifth transistor T5 includes an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

The active layer (ACT) may be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the active layer (ACT) is formed of an oxide semiconductor, the active layer (ACT) consists of a channel region, a source region, and a drain region, and the source region and drain region may be conductive regions, but are limited to this. It doesn't work.

A gate insulating layer 112 is disposed on the active layer (ACT). The gate insulating layer 112 is an insulating layer for insulating the active layer (ACT) and the gate electrode (GE), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is limited thereto. It doesn't work.

A gate electrode (GE) is disposed on the gate insulating layer 112. The gate electrode (GE) may be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, it is not limited to this.

An interlayer insulating layer 113 is disposed on the gate electrode GE. Contact holes are formed in the interlayer insulating layer 113 to connect the source electrode (SE) and the drain electrode (DE) to the active layer (ACT). The interlayer insulating layer 113 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode (SE) and a drain electrode (DE) are disposed on the interlayer insulating layer 113. The source electrode (SE) and drain electrode (DE) arranged to be spaced apart from each other may be electrically connected to the active layer (ACT). The source electrode (SE) and drain electrode (DE) are made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or It may be composed of an alloy, but is not limited thereto.

A first low-potential power line (AL1), a high-potential power line (PL), and a data line (DL) are disposed on the interlayer insulating layer 113 in the display area (AA). Additionally, a second low-potential power supply line AL2 is disposed on the interlayer insulating layer 113 in the non-display area NA. The first low-potential power supply wiring (AL1), the second low-potential power supply wiring (AL2), the high-potential power supply wiring (PL), and the data wiring (DL) are disposed on the same layer as the source electrode (SE) and the drain electrode (DE). may be made of the same conductive material, but is not limited thereto. For example, the first low-potential power wiring (AL1), the second low-potential power wiring (AL2), the high-potential power wiring (PL), and the data wiring (DL) are made of a conductive material, for example, copper (Cu), It may be made of aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

A passivation layer ( 114) is placed. The passivation layer 114 is an insulating layer to protect the structure below the passivation layer 114. For example, the passivation layer 114 may be composed of a single layer or a multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Additionally, the passivation layer 114 may be omitted depending on the embodiment.

A planarization layer 115 is disposed on the passivation layer 114. The planarization layer 115 is an insulating layer that planarizes the upper part of the substrate 110. The planarization layer 115 may be made of an organic material, for example, a single layer or a double layer of polyimide or photo acryl, but is not limited thereto.

A plurality of light emitting devices 120 are disposed in each of the plurality of sub-pixels SP on the planarization layer 115. The light emitting device 120 includes an anode 121, an organic layer 122, and a cathode 123.

An anode 121 is disposed on the planarization layer 115 in the display area AA. The anode 121 is electrically connected to a transistor of the pixel circuit, for example, the second transistor T2 and the fifth transistor T5, and can receive a driving current. Since the anode 121 supplies holes to the organic layer 122, it may be made of a conductive material with a high work function.

A connection electrode (CE) is disposed on the planarization layer 115 in the non-display area (NA). The connection electrode CE is a connecting member for electrically connecting the cathode 123 and the second low-potential power wiring AL2, and may be made of the same material as the anode 121 and disposed on the same layer. However, the connection electrode (CE) may be omitted, but is not limited thereto.

The anode 121 and the connection electrode (CE) may be formed of a transparent conductive material such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), but are not limited thereto. No.

Meanwhile, the display device 100 may be implemented in a top emission or bottom emission method. In the case of the top emission method, a metal material with excellent reflection efficiency is placed at the bottom of the anode 121 so that the light emitted from the organic layer 122 is reflected by the anode 121 and heads upward, that is, toward the cathode 123. For example, a reflective layer made of a material such as aluminum (Al) or silver (Ag) may be added. Conversely, when the display device 100 is a bottom emission type, the anode 121 may be made only of a transparent conductive material. Hereinafter, the description will be made assuming that the display device 100 according to an embodiment of the present invention is a top emission type.

A bank 116 is disposed on the anode 121 and the planarization layer 115. The bank 116 is an insulating layer disposed between the plurality of sub-pixels SP to distinguish the plurality of sub-pixels SP. Bank 116 includes an opening exposing a portion of anode 121. The bank 116 may be an organic insulating material disposed to cover the end or edge of the anode 121. The bank 116 may be made of, for example, polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

An organic layer 122 is disposed on the anode 121 and the bank 116. The organic layer 122 includes a light emitting layer. The light emitting layer is an organic layer for emitting light of a specific color. Different light emitting layers may be disposed in each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3), and a plurality of sub-pixels may be provided. The same light emitting layer may be disposed throughout the pixel SP. For example, when different light-emitting layers are disposed in each of the plurality of sub-pixels SP1, a blue light-emitting layer is disposed in the first sub-pixel SP1, a green light-emitting layer is disposed in the second sub-pixel SP2, and a green light-emitting layer is disposed in the second sub-pixel SP2. 3 A red light emitting layer may be disposed in the sub-pixel SP3. Additionally, the light emitting layers of the plurality of sub-pixels SP may be connected to each other to form a single layer across the plurality of sub-pixels SP. For example, the light emitting layer may be disposed throughout the plurality of sub-pixels SP. , light from the light emitting layer may be converted into light of various colors through a separate light conversion layer, color filter, etc.

Additionally, a plurality of light emitting layers that emit light of the same color may be stacked in one sub-pixel SP. For example, two blue light-emitting layers are stacked in the first sub-pixel (SP1), two green light-emitting layers are stacked in the second sub-pixel (SP2), and two red light-emitting layers are stacked in the third sub-pixel (SP3). It can be. In this case, a charge generation layer (CGL) is disposed between each of the plurality of light-emitting layers, so that electrons or holes can be smoothly supplied to each of the plurality of light-emitting layers. That is, the charge generation layer may be disposed between two blue light-emitting layers, between two green light-emitting layers, and between two red light-emitting layers.

Additionally, a plurality of light-emitting layers that emit light of different colors may be stacked in one sub-pixel SP. For example, a blue emission layer and a yellow-green emission layer may be stacked on all of the plurality of sub-pixels (SP), thereby implementing white light in all of the plurality of sub-pixels (SP). In this case, a charge generation layer may be disposed between the blue emission layer and the yellow-green emission layer.

Meanwhile, although not shown in FIG. 3B, the organic layer may further include a common layer disposed to improve the luminous efficiency of the light-emitting layer. For example, the common layer may be formed as one layer across a plurality of sub-pixels (SP). That is, the common layers of each of the plurality of sub-pixels (SP) may be connected to each other and formed as one body. The common layer may include, but is not limited to, the above-described charge generation layer, hole injection layer, hole transport layer, electron transport layer, and electron injection layer.

A cathode 123 is disposed on the organic layer 122. Since the cathode 123 supplies electrons to the organic layer 122, it may be made of a conductive material with a low work function. The cathode 123 may be formed as one layer over a plurality of sub-pixels (SP). That is, the cathodes 123 of each of the plurality of sub-pixels (SP) may be connected to each other and formed as one body.

The cathode 123 may be connected to the first low-potential power line AL1. As an example, the cathode 123 may directly contact at least a portion of the upper surface of the plurality of first low-potential power wires AL1 exposed through the contact hole of the bank 116 and the planarization layer 115. As another example, the cathode 123 may be electrically connected to each of the plurality of first low-potential power lines AL1 through contact holes in the bank 116 and the planarization layer 115. For example, the cathode 123 may be electrically connected to the first low-potential power line AL1 with an auxiliary electrode interposed therebetween. The cathode 123 can receive a low-potential power supply voltage (EVSS) by being connected to the first low-potential power supply line (AL1).

The cathode 123 is formed of, for example, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), a metal alloy such as MgAg, or a ytterbium (Yb) alloy. It may be, and a metal doping layer may be further included, but is not limited thereto.

In the display device 100 according to an embodiment of the present specification, a plurality of first low-potential power wires (AL1) connected to the second low-potential power wire (AL2) are disposed in the display area (AA). Accordingly, the low-potential power supply voltage for driving the plurality of sub-pixels SP can be minimized.

Specifically, in the display device 100 according to an embodiment of the present specification, the first low-potential power line AL1 is disposed in each of the plurality of sub-pixels SP in the display area AA. Additionally, each of the plurality of first low-potential power wires (AL1) is connected to the second low-potential power wire (AL2). Accordingly, compared to the case where the plurality of first low-potential power wires AL1 are not disposed, the resistance of the second low-potential power wire AL2 may be reduced, and the resistance of the second low-potential power wire AL2 may be reduced to drive the plurality of sub-pixels SP. 2 The low-potential power supply voltage required for the low-potential power wiring (AL2) can be minimized. Therefore, in the display device 100 according to an embodiment of the present specification, a plurality of first low-potential power wires AL1 connected to the second low-potential power wire AL2 are disposed in the display area AA, so that a plurality of first low-potential power wires AL1 connected to the second low-potential power wire AL2 are disposed in the display area AA. The low-potential power supply voltage for driving the sub-pixel SP can be minimized, and heat generation and deterioration of the lifespan of the display device 100 can be improved.

In the display device 100 according to an embodiment of the present specification, the cathode 123 and the first low-potential power line AL1 are directly connected within the display area AA, so the current moving through the cathode 123 is Travel distance can be minimized.

In an embodiment, when the cathode is connected only to the low-potential power wiring disposed along the outside of the non-display area, the current moving from the plurality of light-emitting elements in the display area to the low-potential power wiring is connected to the cathode extending to the non-display area. It moves to the low-potential power wiring arranged along the outside of the non-display area. At this time, the cathode is arranged to have a large area so that it can be shared by a plurality of light-emitting devices, so a large sheet resistance is generated due to the cathode. Accordingly, there was a problem of loss of low-potential power supply voltage due to the large surface resistance of the cathode.

On the other hand, in the display device 100 according to an embodiment of the present specification, the cathode 123 and the first low-potential power line AL1 are directly connected within the display area AA. Accordingly, the current moving through the cathode 123 may move to a plurality of first low-potential power lines AL1 directly connected to the cathode 123 within the display area AA. Accordingly, compared to the case where the cathode 123 is connected only to a low-potential power wiring disposed on the outside of the display device 100, the movement distance of the current moving through the cathode 123 and the sheet resistance of the cathode 123 Voltage loss can be minimized.

In the display device 100 according to an embodiment of the present specification, the cathode 123 and the plurality of first low-potential power wires AL1 are directly connected within the display area AA without passing through other components, so that the cathode ( 123), the voltage loss can be further minimized. Therefore, in the display device 100 according to an embodiment of the present specification, the cathode 123 and the first low-potential power line AL1 are directly connected within the display area AA, so that the cathode 123 moving through the cathode 123 The distance the current moves can be minimized, and the voltage loss of the display device 100 can be minimized.

In the display device 100 according to an embodiment of the present specification, heat generation and reduction in lifespan of the display device 100 can be improved by reducing the power supply voltage of the low-potential power wiring.

In an embodiment, when the cathode is connected only to the low-potential power wiring disposed on the outside of the display device, a loss of the low-potential power supply voltage may occur due to the large surface resistance of the cathode, and accordingly, the low-potential power wiring also has a larger load. A low potential power supply voltage is required. Accordingly, as the power supply voltage increases, there is a problem in that the amount of heat generated and the lifespan of the display device decreases.

On the other hand, in the display device 100 according to an embodiment of the present specification, the moving distance of the current moving through the cathode 123 can be minimized, and thus the voltage loss of the low-potential power wiring can be minimized. Accordingly, the power voltage required for low-potential power wiring can also be reduced, so heat generation and reduction in lifespan of the display device 100 can be improved. Therefore, in the display device 100 according to an embodiment of the present specification, heat generation and reduced lifespan of the display device 100 can be improved by reducing the power voltage of the low-potential power wiring, and thus a low-power display device can be provided. .

4 is a plan view of a display device according to another embodiment of the present specification. The display device 400 of FIG. 4 is different from the display device 100 of FIGS. 1 to 3B only in that the second low-potential power wiring AL2 is omitted, and other configurations are substantially the same, so duplicate description is required. is omitted.

Referring to FIG. 4 , the first low-potential power line AL1 may be disposed only in the display area AA among the display area AA and the non-display area NA. Specifically, except for one end of the first low-potential power wiring AL1 extending to the lower part of the substrate 110, the first low-potential power wiring AL1 is not disposed in other non-display areas NA. In other words, the meaning that the first low-potential power wire AL1 is disposed only in the display area AA also includes the case where the first low-potential power wire AL1 passes through a portion of the non-display area NA. For example, most of the plurality of first low-potential power wires (AL1) may be disposed only in the display area (AA), but one end of the plurality of first low-potential power wires (AL1) is located in the non-display area (NA). It may extend to the bottom of the phosphorus substrate 110 and be connected to another component for receiving electrical signals.

In the display device 400 according to another embodiment of the present specification, the low-potential power wiring disposed along the outer edge of the non-display area (NA) is omitted, thereby minimizing the bezel.

Specifically, in the display device 400 according to another embodiment of the present specification, the cathode 123 and the first low-potential power line AL1 are directly connected within the display area AA, so that the non-display area NA A low-potential voltage can be supplied to the cathode 123 even if the separate low-potential power wiring disposed along the perimeter is omitted. In addition, since the bezel can be removed as much as the space where the low-potential power wiring separately arranged outside the non-display area (NA) is omitted, the bezel can be minimized and a narrow bezel can be implemented. Therefore, in the display device 400 according to another embodiment of the present specification, the low-potential power wiring disposed along the outside of the non-display area (NA) is omitted, thereby minimizing the bezel and implementing a narrow bezel. A display device 400 may be provided.

FIG. 5A is a plan view of a display device according to another embodiment of the present specification. FIG. 5B is a cross-sectional view taken along line C-C' of FIG. 5A. The display device 500 of FIGS. 5A and 5B is different from the display device 100 of FIGS. 1 to 3B only in that the first low-potential power line AL1 is connected to the dummy sub-pixel DSP. Since other configurations are substantially the same, redundant description will be omitted.

Referring to FIG. 5A , the outermost sub-pixel (SP) of the plurality of sub-pixels (SP) arranged in the display area (AA) is a dummy sub-pixel (DSP) in which a dummy light-emitting element is disposed. For example, the dummy sub-pixel (DSP) may be disposed on both the top, bottom, left and right sides at the outermost edge of the display area (AA). However, the dummy sub-pixel (DSP) may be defined as being disposed in the non-display area (NA) rather than the display area (AA).

A plurality of dummy sub-pixels (DSP) are provided to minimize defects due to loading effects in the outermost sub-pixel (SP) among the plurality of sub-pixels (SP) during the formation of the plurality of sub-pixels (SP). It is an extra configuration arranged in the same structure as the sub-pixel (SP) of .

Meanwhile, since the dummy sub-pixel (DSP) is an extra element disposed during the manufacturing process of the display device 100, it has no special function after the manufacturing process of the display device 100 is completed and may be configured not to emit light. Accordingly, in FIG. 5B, it is shown that the organic layer 122 for light emission is not disposed in the dummy sub-pixel (DSP), but the dummy sub-pixel (DSP) has the same configuration as the light-emitting device 120 of the plurality of sub-pixels (SP). The anode 121, the organic layer 122, and the cathode 123 may all be disposed, but the present invention is not limited thereto.

Referring to FIG. 5B, the cathode 123 is electrically connected to the first low-potential power line AL1 connected to the dummy sub-pixel DSP among the plurality of first low-potential power lines AL1 disposed in the display area AA. It can be connected to . That is, the cathode 123 is electrically connected only to the first low-potential power wire (AL1) connected to the dummy sub-pixel (DSP) among the plurality of first low-potential power wires (AL1) and connected to the remaining sub-pixels (SP). It may not be connected to the first low-potential power wiring (AL1).

At this time, the first low-potential power line (AL1) connected to the dummy sub-pixel (DSP) may be disposed with a wider width than the first low-potential power line (AL1) connected to the remaining sub-pixels (SP). Since the dummy sub-pixel (DSP) has no special function after the manufacturing process of the display device 100 is completed, the dummy sub-pixel (DSP) has a data line (DL) or high potential placed in the remaining sub-pixels (SP). The power wiring (PL) may not be placed. Accordingly, in the dummy sub-pixel (DSP), the width of the first low-potential power supply line (AL1) may be increased to the extent that the data line (DL) or the high-potential power supply line (PL) is omitted, but is not limited thereto.

Meanwhile, in FIG. 5B, the cathode 123 of the dummy sub-pixel (DSP) is shown as being directly connected to the first low-potential power supply line (AL1) through a contact hole in the bank 116 and the planarization layer 115. However, since the organic layer 122 can be omitted in the dummy sub-pixel (DSP), the cathode 123 of the dummy sub-pixel (DSP) and the first low-potential power line (AL1) are electrically connected through the anode 121. It may be possible. In this case, even without forming a contact hole in the bank 116 and the planarization layer 115, the cathode 123 of the dummy sub-pixel (DSP) and the first low-potential power supply line (AL1) can be connected using only the existing configuration of the dummy sub-pixel (DSP). ) can be electrically connected, so it can be more advantageous in terms of saving the process. In addition, the space for forming a contact hole in the bank 116 and the planarization layer 115 will be omitted so that the cathode 123 of the dummy sub-pixel (DSP) and the first low-potential power line (AL1) can be electrically connected. Therefore, it can be advantageous in terms of miniaturization of the display device 500.

In the display device 500 according to another embodiment of the present specification, the cathode 123 is connected only to the first low-potential power wire (AL1) connected to the dummy sub-pixel (DSP) among the plurality of first low-potential power wires (AL1). are electrically connected. Accordingly, the reliability of the electrical connection between the cathode 123 and the plurality of first low-potential power wiring lines AL1 can be improved.

Specifically, various wirings and electrodes are disposed around the first low-potential power wiring connected to the plurality of sub-pixels to be connected to the plurality of sub-pixels. Accordingly, the maximum size of the first low-potential power wiring connected to a plurality of sub-pixels may inevitably be limited. In addition, in the process of forming contact holes in the bank and the planarization layer so that the cathode and the first low-potential power wiring can be electrically connected due to size limitations of the first low-potential power wiring, a contact hole is formed on the first low-potential power wiring. Mis-alignment, which cannot be formed accurately, may occur. Additionally, as the number of sub-pixels increases, the probability of such misalignment may increase.

Accordingly, in the display device 500 according to another embodiment of the present specification, the cathode 123 is a first low-potential power line (AL1) connected to the dummy sub-pixel (DSP) among the plurality of first low-potential power lines (AL1). ) is electrically connected only to That is, the cathode 123 is electrically connected only to the first low-potential power supply line AL1 of the dummy sub-pixel (DSP), which has less restrictions on the arrangement size. Accordingly, since a contact hole can be formed on the larger first low-potential power wiring (AL1), the occurrence of misalignment in the process of forming a contact hole on the first low-potential power wiring (AL1) can be minimized. there is. In addition, since the dummy sub-pixel (DSP) is disposed only at the outermost edge of the display area, when the cathode 123 is electrically connected only to the dummy sub-pixel (DSP), the alignment of the entire display area (AA) is completely Alignment control may be easier compared to control. Accordingly, the occurrence of misalignment in the process of forming a contact hole on the first low-potential power wiring (AL1) can be minimized, and the electrical connection between the cathode 123 and the plurality of first low-potential power wiring (AL1) can be improved. Reliability can be improved. Therefore, in the display device 500 according to another embodiment of the present specification, the cathode 123 is a first low-potential power line (AL1) connected to the dummy sub-pixel (DSP) among the plurality of first low-potential power lines (AL1). ), the reliability of the electrical connection between the cathode 123 and the plurality of first low-potential power wires AL1 can be improved.

Figure 6 is a cross-sectional view of a display device according to another embodiment of the present specification. The display device 600 of FIG. 6 is different from the display device 100 of FIGS. 1 to 3B only in that the first low-potential power wiring AL1 is disposed on the same layer as the touch electrode TE. , Other configurations are substantially the same, so redundant description is omitted.

Referring to FIG. 6, an encapsulation portion 130 is disposed on the cathode 123 of the light emitting device 120. The encapsulation portion 130 is disposed on the light-emitting device 120 to protect the light-emitting device 120 from moisture penetrating into the light-emitting device 120 .

The encapsulation portion 130 includes a first inorganic encapsulation layer 131, an organic encapsulation layer 132, and a second inorganic encapsulation layer 133.

The first inorganic encapsulation layer 131 is disposed on the cathode 123. And, the organic encapsulation layer 132 may be disposed on the first inorganic encapsulation layer 131. Additionally, the second inorganic encapsulation layer 133 may be disposed on the organic encapsulation layer 132. The first inorganic encapsulation layer 131 and the second inorganic encapsulation layer 133 of the encapsulation portion 130 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The organic encapsulation layer 132 of the encapsulation portion 130 is made of, for example, acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin ( It can be formed from organic materials such as polyimide resin. However, this is only an example and does not limit the embodiments of the present specification.

A touch sensing unit is disposed on the sealing unit 130. The touch sensing unit includes a first touch insulating layer 117, a touch electrode (TE), and a second touch insulating layer 118. Accordingly, the display device 600 may be a display device of a TOE (Touch Sensor on Encapsulation Layer) structure in which a touch sensor metal such as a touch electrode (TE) is disposed on the encapsulation portion 130, but is not limited thereto.

The first touch insulating layer 117 is disposed on the second inorganic encapsulation layer 133 of the encapsulation portion 130. The first touch insulating layer 117 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

A plurality of touch electrodes (TE) are disposed on the first touch insulating layer 117. The touch electrode (TE) may be an electrode made of a transparent metal or an electrode made of an opaque metal, but is not limited thereto. In FIG. 6, the touch electrode TE is shown as being disposed on the top of the light emitting device 120. When the touch electrode TE is made of an opaque metal, the touch electrode TE may not be disposed on the light emitting device 120 .

A second touch insulating layer 118 is disposed on the touch electrode TE. The second touch insulating layer 118 may be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

Meanwhile, although not shown in FIG. 6, for example, a plurality of touch sensing electrodes may be further disposed on the second touch insulating layer 118. In this case, the plurality of touch electrodes (TE) are bridge electrodes and may be connected to the plurality of touch sensing electrodes through contact holes formed in the second touch insulating layer, but the specific configuration of the touch electrodes (TE) is not limited thereto.

Referring to FIG. 6 , a first low-potential power line AL1 is disposed on the first touch insulating layer 117. The first low-potential power line AL1 is disposed on the same layer as the touch electrode TE on the first touch insulating layer 117. The first low-potential power wiring AL1 is made of the same material as the touch electrode TE. That is, the first low-potential power line AL1 may be formed through the same process as the touch electrode TE.

The first low-potential power line AL1 is disposed to be spaced apart from the touch electrode TE. The first low-potential power wiring AL1 is disposed on the same layer as the touch electrode TE and is spaced apart from the touch electrode TE. Accordingly, the first low-potential power line AL1 and the touch electrode TE may function as separate configurations.

Referring to FIG. 6 , the first low-potential power wiring AL1 is electrically connected to the cathode 123 through a contact hole formed in the first touch insulating layer 117 and the sealing portion 130. Accordingly, the first low-potential power line AL1 may be electrically connected to the cathode 123 on the same layer as the first touch insulating layer 117.

In the display device 600 according to another embodiment of the present specification, the first low-potential power line AL1 is disposed on the same layer as the touch electrode TE. Accordingly, the arrangement space for directly connecting the cathode 123 and the first low-potential power line AL1 within the display area AA can be minimized.

Specifically, in the display device 600 according to another embodiment of the present specification, in order to minimize voltage loss of the display device 100 and reduce the power supply voltage of the low-potential power wiring, the cathode 123 and the first low-potential power supply are connected to each other. The wire (AL1) is directly connected within the display area (AA). At this time, the first low-potential power wiring (AL1) is disposed on the same layer as the touch electrode (TE) and is electrically connected to the cathode 123 through the contact hole formed in the first touch insulating layer 117 and the sealing portion 130. It is connected to Accordingly, since the first low-potential power wire (AL1) is disposed on the upper part of the cathode, a contact hole can be placed, so that a contact hole is placed to electrically connect the cathode 123 and the first low-potential power wire (AL1). Additional space may not be needed. In addition, the arrangement of the first low-potential power wiring AL1 like this utilizes the previously placed touch electrode TE, so it can be more advantageous in terms of saving the manufacturing process. Accordingly, in the display device 600 according to another embodiment of the present specification, the first low-potential power line AL1 is disposed on the same layer as the touch electrode TE, so that the cathode 123 within the display area AA The arrangement space for directly connecting the first low-potential power wiring AL1 can be minimized.

A display device according to embodiments of the present specification may be described as follows.

A display device according to an embodiment of the present specification includes a substrate including a display area on which a plurality of sub-pixels are arranged and a non-display area surrounding the display area, and a plurality of sub-pixels disposed in the display area on the substrate and connected to each of the plurality of sub-pixels. is disposed in each of the plurality of sub-pixels on the first low-potential power wiring and the substrate, and includes a plurality of light-emitting elements including an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer, and the cathode is a plurality of first 1 Can be electrically connected to at least some of the low-potential power wiring.

According to another feature of the present specification, it further includes a planarization layer disposed between the first low-potential power wiring and the anode and a bank disposed to cover the end of the anode between the plurality of sub-pixels, and the cathode is of the bank and the planarization layer. It may be electrically connected to the first low-potential power wiring through the contact hole.

According to another feature of the present specification, the cathode may directly contact at least a portion of the upper surface of the first low-potential power wiring exposed through the contact hole of the bank and the planarization layer.

According to another feature of the present specification, a plurality of first low-potential power wirings may be disposed between a plurality of sub-pixels.

According to another feature of the present specification, the non-display area may further include a second low-potential power wire disposed along the outer edge of the display area and connected to a plurality of first low-potential power wires.

According to another feature of the present specification, the width of the second low-potential power wiring may be wider than the width of the first low-potential power wiring.

According to another feature of the present specification, among the plurality of sub-pixels, the sub-pixel disposed at the outermost part of the display area is a dummy sub-pixel in which a dummy light-emitting element is disposed, and the cathode is one of the plurality of first low-potential power wirings. It may be electrically connected to a first low-potential power line connected to the dummy sub-pixel.

According to another feature of the present specification, the cathode may be electrically connected only to the first low-potential power wire connected to the dummy sub-pixel among the plurality of first low-potential power wires.

According to another feature of the present specification, it further includes a touch insulating layer disposed on the plurality of light emitting elements and a touch electrode disposed on the touch insulating layer, and the first low potential power wiring is the same as the touch electrode on the touch insulating layer. Can be placed on a layer.

According to another feature of the present specification, the first low-potential power wiring may be electrically connected to the cathode through a contact hole in the touch insulating layer.

According to another feature of the present specification, it further includes an encapsulation layer disposed between the plurality of light emitting elements and the touch insulating layer, and the first low-potential power wiring is electrically connected to the cathode through a contact hole in the touch insulating layer and the encapsulation layer. can be connected

According to another feature of the present specification, the first low-potential power wiring may be arranged to be spaced apart from the touch electrode.

According to another feature of the present specification, the first low-potential power wiring may be made of the same material as the touch electrode.

According to another feature of the present specification, a substrate including a display area and a non-display area on which a plurality of sub-pixels are arranged, a plurality of first low-potential power wirings disposed in the display area and connected to each of the plurality of sub-pixels, and a plurality of It is disposed in each sub-pixel, and includes a plurality of light emitting elements including an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer, wherein the cathode extends on at least a portion of the plurality of first low-potential power wirings. It may be electrically connected in direct contact with the first low-potential power wiring.

According to another feature of the present specification, it further includes a planarization layer disposed between the first low-potential power wiring and the anode and a bank disposed between the anode and the cathode to cover the end of the anode, and the cathode is in the bank and the planarization layer. It may extend onto at least a portion of the first low-potential power wiring through the formed contact hole and be electrically connected to the first low-potential power wiring.

According to another feature of the present specification, the non-display area further includes a second low-potential power wire disposed along the outer edge of the display area, and the second low-potential power wire may be connected to a plurality of first low-potential power wires. there is.

According to another feature of the present specification, the width of the second low-potential power wiring may be wider than the width of the first low-potential power wiring.

According to another feature of the present specification, the display area further includes a dummy sub-pixel disposed along the outermost edge of the display area, and the cathode is a first low-potential power supply connected to the dummy sub-pixel among the plurality of first low-potential power wires. It can only be electrically connected to wiring.

According to another feature of the present specification, it further includes a touch insulating layer disposed on the plurality of light emitting elements and a touch electrode disposed on the touch insulating layer, wherein the first low-potential power wiring is disposed on the same layer as the touch electrode, It may be arranged to be spaced apart from the touch electrode.

Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present specification. . Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present specification, but are for illustrative purposes, and the scope of the technical idea of the present specification is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of this specification should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of this specification.

100, 400, 500, 600: display device 110: substrate
111: buffer layer 112: gate insulating layer
113: interlayer insulating layer 114: passivation layer
115: planarization layer 116: bank
117: first touch insulating layer 118: second touch insulating layer
120: light emitting device 121: anode
122: organic layer 123: cathode
130: Encapsulation part 131: First inorganic encapsulation layer
132: Organic encapsulation layer 133: Second inorganic encapsulation layer
AA: Display area NA: Non-display area
SP: Sub-pixel SP1: First sub-pixel
SP2: 2nd sub-pixel SP3: 3rd sub-pixel
DSP: Dummy sub-pixel SL: Scan wiring
SL1: 1st scan wiring SL2: 2nd scan wiring
DL: Data wiring PL: High potential power wiring
AL1: First low-potential power supply wiring AL2: Second low-potential power supply wiring
EL: Light emission control signal wiring IL: Initialization signal wiring
EVDD: High potential supply voltage EVSS: Low potential supply voltage
SCAN1: first scan voltage SCAN2: second scan voltage
Vdata: data voltage EM: emission control voltage
Vini: Initialization voltage Cst: Capacitor
T1: first transistor T2: second transistor
T3: third transistor T4: fourth transistor
T5: fifth transistor T6: sixth transistor
ACT: active layer GE: gate electrode
DE: drain electrode SE: source electrode
CE: Connection electrode TE: Touch electrode

Claims (19)

A substrate including a display area on which a plurality of sub-pixels are arranged and a non-display area surrounding the display area;
a plurality of first low-potential power lines disposed in the display area on the substrate and connected to each of the plurality of sub-pixels; and
A plurality of light emitting elements are disposed in each of the plurality of sub-pixels on the substrate and include an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer,
The cathode is electrically connected to at least a portion of the plurality of first low-potential power wirings. According to paragraph 1,
a planarization layer disposed on the first low-potential power wiring; and
Further comprising a bank disposed between the plurality of sub-pixels to cover an end of the anode,
The display device wherein the cathode is electrically connected to the first low-potential power wiring through a contact hole in the bank and the planarization layer. According to paragraph 2,
The cathode is in direct contact with at least a portion of a top surface of the first low-potential power wiring exposed through a contact hole in the bank and the planarization layer. According to paragraph 1,
A display device, wherein the plurality of first low-potential power wirings are disposed between the plurality of sub-pixels. According to paragraph 1,
The display device further includes second low-potential power wires disposed along an outer edge of the display area in the non-display area and connected to the plurality of first low-potential power wires. According to clause 5,
A display device wherein the width of the second low-potential power supply wiring is wider than the width of the first low-potential power supply wiring. According to paragraph 1,
Among the plurality of sub-pixels, a sub-pixel disposed at the outermost edge of the display area is a dummy sub-pixel in which a dummy light-emitting element is disposed,
The cathode is electrically connected to a first low-potential power wire connected to the dummy sub-pixel among the plurality of first low-potential power wires. In clause 7,
The display device wherein the cathode is electrically connected only to a first low-potential power wire connected to the dummy sub-pixel among the plurality of first low-potential power wires. According to paragraph 1,
a touch insulating layer disposed on top of the plurality of light emitting devices; and
Further comprising a touch electrode disposed on the touch insulating layer,
The display device wherein the first low-potential power wiring is disposed on the same layer as the touch electrode on the touch insulating layer. According to clause 9,
The first low-potential power wiring is electrically connected to the cathode through a contact hole in the touch insulating layer. According to clause 9,
Further comprising an encapsulation layer disposed between the plurality of light emitting devices and the touch insulating layer,
The first low-potential power wiring is electrically connected to the cathode through a contact hole in the touch insulating layer and the encapsulation layer. According to clause 9,
The first low-potential power wiring is arranged to be spaced apart from the touch electrode. According to clause 9,
The first low-potential power wiring is made of the same material as the touch electrode. A substrate including a display area and a non-display area on which a plurality of sub-pixels are arranged;
a plurality of first low-potential power lines disposed in the display area and connected to each of the plurality of sub-pixels; and
A plurality of light emitting elements are disposed in each of the plurality of sub-pixels and include an anode, an organic layer disposed on the anode, and a cathode disposed on the organic layer,
The cathode extends onto at least a portion of the plurality of first low-potential power wires and is in direct contact with and electrically connected to the first low-potential power wires. According to clause 14,
a planarization layer disposed on the first low-potential power wiring; and
Further comprising a bank disposed between the anode and the cathode to cover an end of the anode,
The cathode is electrically connected to the first low-potential power wiring through a contact hole formed in the bank and the planarization layer. According to clause 14,
Further comprising a second low-potential power line disposed along the outer edge of the display area in the non-display area,
The display device wherein the second low-potential power wiring is connected to the plurality of first low-potential power wiring. According to clause 16,
A display device wherein the width of the second low-potential power wiring is wider than the width of the first low-potential power wiring. According to clause 14,
Further comprising a dummy sub-pixel disposed along an outermost edge of the display area in the display area,
The display device wherein the cathode is electrically connected only to a first low-potential power wire connected to the dummy sub-pixel among the plurality of first low-potential power wires. According to clause 14,
a touch insulating layer disposed on top of the plurality of light emitting devices; and
Further comprising a touch electrode disposed on the touch insulating layer,
The first low-potential power wiring is disposed on the same layer as the touch electrode and is spaced apart from the touch electrode.

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