KR20240083381A - Flip-flop circuit with pulsed latch structure - Google Patents

Abstract

A flip-flop circuit with a pulsed latch structure according to the first aspect of the present invention includes a differential pulsed latch structure; and a dynamic XOR structure, wherein the differential pulsed latch structure additionally includes a dual bridge structure and shares a clock transistor. Accordingly, the pull-down of the output signal is performed first to change the output value, enabling stable operation at low voltage.

Description

Flip-flop circuit with pulsed latch structure}

The present invention relates to a flip-flop circuit with a pulsed latch structure, and more specifically, to a flip-flop circuit with a pulsed latch structure that operates stably at a low voltage by first pulling down an output signal to change the output value.

Pulsed latch flip-flops have higher performance than regular flip-flops, but are vulnerable to variation and have problems operating at low voltages. Additionally, the use of a large area reduces the area efficiency of the processor. This structure, which is vulnerable to variation, causes flip-flop malfunction at low voltages and prevents proper operation.

Pulsed latch flip-flops with differential pulsed latch and dynamic This makes it suitable for use in processors that operate at low voltage and high performance. A pulsed latch flip-flop that can operate without signal contention without a separate signal generator by stabilizing the output signal more through this differential pulsed latch and dynamic XOR structure is required.

Figure 1 is a diagram showing a basic pulsed latch type transmission gate pulsed latch (TGPL) flip-flop circuit.

Referring to FIG. 1, a transmission gate pulsed latch (TGPL) as shown in FIG. 1 is a basic pulsed latch type flip-flop circuit. It uses a basic pulse generation method, and the pulse width can be controlled through an inverter chain. The inverter chain unit delays the clock signal (CK) by a predetermined amount after the rising edge and makes the inversion delay clock signal (DCK) to 0.

Such a transmission gate pulsed latch (TGPL) cannot operate at low voltages because it does not satisfy the minimum pulse width constraint due to variation at low voltages, and requires a large number of inverters in the inverter chain, taking up a lot of area. do.

Figure 2 is a diagram showing a self-timed pulsed latch (STPL) flip-flop circuit using a dynamic XOR structure.

Referring to FIG. 2, a self-timed pulsed latch (STPL) as shown in FIG. 2 uses a dynamic XOR (dynamic XOR) structure instead of an inverter chain to control the pulse width. By flexibly controlling the pulse width according to the variation through the dynamic However, due to structural problems, operation at low voltage is still unstable.

More specifically, compared to the transfer gate pulsed latch (TGPL), the self-timed pulsed latch (STPL) uses a dynamic XOR structure to wait until Q=D after the rising edge of the clock signal (CK). Change the inversion delay clock signal (DCK) to 0. However, when QN changes from 0 to 1 and QI does not change stably from 1 to 0, DCK changes to 0 and QN and QI may not be updated properly.

The present invention is intended to solve the problems of the prior art as described above, and provides a flip-flop circuit with a pulsed latch structure that operates stably at low voltage by first pulling down the output signal to change the output value.

A flip-flop circuit with a pulsed latch structure according to the first aspect of the present invention includes a differential pulsed latch structure; and a dynamic XOR structure, wherein the differential pulsed latch structure additionally includes a dual bridge structure and shares a clock transistor.

A microprocessor circuit according to a second aspect of the present invention includes a memory; and a processor capable of controlling data processing and operations from the memory, wherein the processor includes a flip-flop circuit with a pulsed latch structure according to the first feature.

A flip-flop circuit with a pulsed latch structure according to an embodiment of the present invention provides the following effects.

In a differential pulsed latch, a dual bridge structure is used to supply an output signal when the inverting delay clock signal (DCK) falls and the input signal changes, and the clock transistor is shared in the pull-down path to reduce the load of the clock ( load) and the number of transistors are reduced, and the output value is changed after the output signal is pulled down, enabling stable operation at low voltage.

Figure 1 is a diagram showing a basic pulsed latch type transmission gate pulsed latch (TGPL) flip-flop circuit.
Figure 2 is a diagram showing a self-timed pulsed latch (STPL) flip-flop circuit using a dynamic XOR structure.
FIG. 3 is a diagram illustrating a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.
FIG. 4 is a diagram conceptually illustrating the operation of a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.
FIG. 5 is a table showing operation measurement results of Monte-Carlo simulation for a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.
Figure 6 is a graph comparing the characteristics of the flip-flop circuit of the disclosed embodiment with that of a conventional flip-flop circuit.

Hereinafter, the present invention will be described in detail with reference to examples and drawings. However, the following description is not intended to limit the present invention to specific embodiments, and in describing the present invention, if it is determined that a detailed description of related known technology may obscure the gist of the present invention, the detailed description will be omitted. .

FIG. 3 is a diagram illustrating a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.

The flip-flop circuit of the pulsed latch structure of the disclosed embodiment includes a differential pulsed latch structure and a dynamic XOR (dynamic XOR) structure, and the differential pulsed latch structure includes a dual bridge structure (Figure 3, the structural part where the CK and DCK signals are input together) is additionally included, and a clock transistor (the transistor at the bottom in Figure 3, where the CK signal is input) is shared. Stable operation at low voltage is possible by using a combination of differential pulsed latch structure and dynamic XOR structure.

In the pulsed latch structure flip-flop circuit of the disclosed embodiment, an input signal (D) and an inverted input signal (DB), an output signal (QI) and an inverted output signal (QN), a clock signal (CK), and an inverted delay clock signal (DCK) ) can be used to operate the circuit.

In the disclosed embodiment, the differential pulsed latch structure changes the output value after the output signal is pulled down, thereby enabling stable operation at low voltage. More specifically, the pulldown will always occur first, with QN changing from 1 to 0 and QI changing from 0 to 1, or QI changing from 1 to 0 and QN changing from 0 to 1, and so on. After stabilization, DCK changes to 0. Accordingly, it can operate stably at low voltage compared to a self-timed pulsed latch (STPL).

The dual bridge structure (the part of the structure in which CK and DCK are input together in Figure 3) includes a PMOS bridge controlled by an inverted delay clock signal (DCK), and supplies an output signal when the DCK signal falls and the input signal changes. It operates as

Sharing of the clock transistor is done in the pull-down path of the differential pulsed latch structure, that is, the transistor where the CK signal is input at the bottom in FIG. 3. In other words, instead of using a transistor through which two CK signals are input, only one transistor is used.

FIG. 4 is a diagram conceptually illustrating the operation of a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.

In the disclosed embodiment, the differential pulsed latch structure operates as follows.

In the retention section, D=0, CK=0, DCK=1, QN=0, QI=1, and in the pulse start section, D=0, CK=1, DCK=1, QN=0. , QI=0, D=0, CK=1, DCK=0, QN=1, QI=0 in the pulse end section, D=1, CK=1, DCK in the data change section. It operates sequentially with =0, QN=1, QI=0.

The change in signal value for each section changes from 0 to 1 for CK and 1 to 0 for QI when the retention section becomes the pulse start section, and from 1 to 0 for DCK and 0 to 1 for QN when the pulse ends section. When the section is reached, D changes from 0 to 1.

FIG. 5 is a table showing operation measurement results of Monte-Carlo simulation for a flip-flop circuit with a pulsed latch structure according to the disclosed embodiment.

The operation of Monte-Carlo Simulation was measured to confirm the characteristics that are resistant to variations at low voltage. In the case of existing flip-flop circuits, it can be confirmed that they cannot operate at low voltages due to their weak characteristics against variation. It can be confirmed that the pulsed latch structure flip-flop circuit of the disclosed embodiment performs a stable operation at the TGFF level due to its resistance to variation.

Figure 6 is a graph comparing the characteristics of the flip-flop circuit of the disclosed embodiment with that of a conventional flip-flop circuit.

It is a graph comparing the setup time and hold time of the conventional flip-flop circuit and the flip-flop circuit of the disclosed embodiment. The flip-flop circuit of the disclosed embodiment has the setup time and hold at the level of the conventional flip-flop circuit. You can check that it keeps time.

As seen so far, the flip-flop circuit of the pulsed latch structure of the disclosed embodiment uses a combination of a differential pulsed latch structure and a dynamic XOR structure, but the differential pulsed latch structure includes a dual bridge structure and shares a clock transistor. By making the output signal more stable, operation can be performed without signal contention without a separate signal generator. Therefore, stable high-performance operation is possible even at low voltage, making it suitable for use in a high-performance processor utilizing dynamic voltage scaling, which enables high-performance operation over a wide voltage range.

Meanwhile, the microprocessor includes a memory and a processor capable of controlling data processing and operations from the memory, and the pulsed latch structure flip-flop circuit of the disclosed embodiment may be included and utilized in the processor.

Since various modifications may be made to the configurations and methods described and illustrated herein without departing from the scope of the present invention, all matters contained in the foregoing detailed description or shown in the accompanying drawings are exemplary and are not intended to limit the present invention. It's not. Accordingly, the scope of the present invention should not be limited by the above-described exemplary embodiments, but should be determined only by the following claims and their equivalents.

Claims (6)

In a flip-flop circuit with a pulsed latch structure,
differential pulsed latch structure; and
Dynamic XOR structure;
Including,
A flip-flop circuit wherein the differential pulsed latch structure additionally includes a dual bridge structure and shares a clock transistor. According to paragraph 1,
The differential pulsed latch structure is a flip-flop circuit characterized in that the output value is changed after a pulldown is performed between output signals that are inverted. According to paragraph 1,
The dual bridge structure includes a PMOS bridge controlled by an inverted delay clock signal,
A flip-flop circuit characterized in that it supplies an output signal when the inverted delay clock signal falls and the input signal changes. According to paragraph 1,
A flip-flop circuit, characterized in that sharing of the clock transistor is achieved in a pull-down path of the differential pulsed latch structure. According to paragraph 1,
The differential pulsed latch structure,
(a) In the conservation interval, D=0, CK=0, DCK=1, QN=0, QI=1
(b) In the pulse start section, D=0, CK=1, DCK=1, QN=0, QI=0
(c) In the pulse end section, D=0, CK=1, DCK=0, QN=1, QI=0
(d) In the data change section, D=1, CK=1, DCK=0, QN=1, QI=0
(Here, D is the input signal, CK is the clock signal, DCK is the inverted delay clock signal, QN is the inverted output signal, and QI is the output signal.)
A flip-flop circuit that operates as (a) to (d), but operates sequentially from (a) to (d). Memory; and
a processor capable of controlling data processing and operations from the memory;
Including,
A microprocessor circuit, wherein the processor includes the flip-flop circuit of any one of claims 1 to 5.

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