KR20240061586A - Method for manufacturing power semiconductor devices using template for semiconductor growth - Google Patents

Abstract

The present invention relates to a method of manufacturing a power semiconductor device using a template for semiconductor growth, comprising the steps of preparing a first growth substrate and a second growth substrate; A bonding step of bonding the first growth substrate and the second growth substrate through a bonding layer; A molding step of manufacturing a template by molding the second growth substrate into an ultra-thin shape so that the second growth substrate functions as a seed layer; and a device forming step of forming a power semiconductor device on the second growth substrate of the template.
According to the present invention, by manufacturing a power semiconductor device using a template for semiconductor growth containing an ultra-thin sapphire seed layer, defects in the power semiconductor device to which the high heat dissipation support substrate is bonded can be significantly reduced. You can.

Description

Method for manufacturing power semiconductor devices using templates for semiconductor growth {METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICES USING TEMPLATE FOR SEMICONDUCTOR GROWTH}

The present invention relates to a method of manufacturing a power semiconductor device using a template for semiconductor growth. The present invention relates to a method of manufacturing a power semiconductor device using a template for semiconductor growth including an ultra-thin sapphire seed layer, thereby forming a high heat dissipation support substrate. The present invention relates to a power semiconductor manufacturing method using a template for semiconductor growth in which defects in the bonded power semiconductor devices can be significantly reduced and high-performance power semiconductor devices can be manufactured.

A gallium nitride (GaN) material-based power semiconductor (HEMT, High Electron Mobility Transistor) with a horizontal channel structure based on technology for growing a gallium nitride (GaN) material directly on top of a conventional silicon (Si) single crystal growth substrate wafer. In order for the device to be stably driven with high voltage and/or high-speed switching function at high temperature, the leakage current of the power semiconductor device must be reduced through high-quality epitaxial thin film growth technology with high breakdown voltage and high reliability characteristics. Restraint design is essential.

To this end, conventional group III nitride semiconductor thin film materials and their power semiconductor device structures include 1) a silicon (Si) single crystal growth substrate wafer with high electrical resistance characteristics, 2) a silicon (Si) single crystal growth substrate wafer surface layer, and Growth of a melt-back etching prevention layer containing aluminum nitride (AlN) material (nitride or nitride oxide containing aluminum (Al) composition) to suppress the melt-back etching phenomenon through reaction at high temperature, and 3) aluminum gallium nitride (AlGaN) material system (Group 3 nitrides with aluminum (Al) or gallium (Ga) composition), growth of a condensed stress layer for crack prevention, and 4) Gallium nitride (GaN) material system (Group 3 nitrides with gallium (Ga) composition). It has a structure in which the growth of a power semiconductor active layer containing group 3 nitrides (group 3 nitrides) is formed by sequential stacking.

And the power semiconductor active layer (HEMT, High Electron Mobility Transistor) of the horizontal channel structure containing the above-described gallium nitride (GaN) material system typically consists of 1) a gallium nitride (GaN) buffer layer, 2) Gallium Nitride (GaN) Channel Layer (horizontal transistor), 3) Aluminum Gallium Nitride (AlGaN) Barrier Layer, 4) Capping Passivation Layer (Depletion Mode) or p-type nitride It is formed by stacking four areas of a semiconductor layer (p-type Nitride Semiconductor Layer; Enhancement Mode).

That is, in the Group III nitride power semiconductor HEMT device structure, which grows a gallium nitride (GaN) material system directly on the top of a conventional silicon (Si) single crystal growth substrate wafer, gallium nitride (GaN) with high resistance is placed under the gallium nitride (GaN) channel layer. A silicon (Si) single crystal growth substrate wafer with high resistance is always used along with the formation of a (GaN) buffer layer, but there are the following problems.

First, in the conventional Group 3 nitride (gallium nitride (GaN) material-based) power semiconductor HEMT device structure, MOCVD (Metal Organic Chemical Vapor Deposition) equipment is used to produce silicon (Si) single crystals for Group 3 nitride power semiconductor growth substrates. A process is performed to directly grow a gallium nitride (GaN) single crystal thin film and a power semiconductor device structure on the top of the wafer. At this time, a single crystal thin film growth (film formation) process based on gallium nitride (GaN) material containing gallium (Ga) atoms is basically performed at a high temperature of around 1000°C and a reducing atmosphere (H2, H+, NH3, radical ions), and silicon (Si) A melt-back etching prevention film area that blocks active Si-Ga metallic eutectic reactions with relatively low energy between the single crystal wafer surface layer and gallium (Ga) atoms is absolutely necessary.

This melt-back etching prevention film area typically has a thickness of around 100 nm, and the representative example is the aluminum nitride (AlN) material layer grown through an in-situ process in the MOCVD chamber, but in addition, other external films ( Before loading into the MOCVD chamber using process equipment (Sputter, PLD, ALD), aluminum nitride (AlN) or aluminum nitride oxide (Aluminum nitride (AlN)) is deposited on the top of a silicon (Si) single crystal wafer for a Group 3 nitride power semiconductor growth substrate. The AlNO) material layer can also be formed (deposited) through an ex-situ process.

However, when forming a melt-back etching prevention film area with the above-described aluminum nitride (AlN) material layer on the top of a silicon (Si) single crystal wafer for a growth substrate with high electrical resistance characteristics, when growing aluminum nitride (AlN), silicon (Si) ) Although the level of damage to the surface of the growth substrate is less, Si-Al metallic eutectic reaction still occurs entirely or locally on the surface of the silicon (Si) growth substrate, forming a conductive interface material layer, which causes nitriding to be grown in a continuous process. There is a problem that causes the crystal quality of the gallium (GaN) material system to deteriorate. In addition, damage to the surface of the silicon (Si) growth substrate causes deterioration in crystal quality (reduced crystallinity) due to the formation of a conductive interface material (disordered SiAlN), and as a result, leakage current increases due to an increase in the density of “dislocations”, which are major crystal defects. This ultimately has the problem of promoting insulation breakdown.

Second, in the above-described conventional Group III nitride (GaN material-based) power semiconductor HEMT device structure, when growing (or forming a film) a material, the lattice constant (LC), which is the material intrinsic value between different heterogeneous materials, The process must be carried out considering the coefficient of thermal expansion (CTE). Typically, when the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between two materials is large, during or after the growth (film formation) process. Due to structural and thermo-mechanical stress, micro (fine) or macro (macro) cracks inevitably occur within the grown (film-formed) material thin film or crystal quality deteriorates. In particular, when directly growing (or forming a film) a gallium nitride (GaN) material system or an aluminum nitride (AlN) material system on the top of a Si single crystal wafer for a Group 3 nitride power semiconductor growth substrate, the coefficient of thermal expansion (CTE) and/or lattice constant ( In terms of LC), tensile stress is strongly generated, so not only can the crack phenomenon be easily observed, but it can also grow beyond a certain thickness to realize a high breakdown voltage and high reliability device. Due to the tensile stress, the group 3 The thickness of the nitride power semiconductor device structure cannot be increased.

Several technologies have been devised as a way to relieve the above-described tensile stress or suppress cracks, but it is difficult to introduce materials and processes that artificially generate compressive stress to compensate and buffer the tensile stress. As a solution, an aluminum gallium nitride (AlGaN) material system containing an aluminum (Al) or gallium (Ga) composition is laminated on the melt-back etching prevention layer area described above in a known multi-layer structure to create a crack prevention condensation stress layer that suppresses the crack phenomenon. This has been introduced and is being used.

However, the crack-prevention condensation stress layer of the conventional Group 3 nitride (GaN material system) power semiconductor HEMT device structure is used to grow a thick layer with high quality when forming an aluminum gallium nitride (AlGaN) material system with a high aluminum (Al) ratio. It is difficult, and there is a problem in that dislocations are generated due to a decrease in crystal quality, which promotes an increase in leakage current.

Third, in the conventional Group 3 nitride (GaN material-based) power semiconductor HEMT device structure, iron (Fe) or carbon (C) is usually used to have high resistance to suppress leakage current under the gallium nitride (GaN) channel layer. A gallium nitride (GaN) buffer layer heavily doped with impurities such as is formed.

However, according to the conventional Group 3 nitride (GaN material system) power semiconductor HEMT device structure, the crystal quality of the gallium nitride (GaN) material system is poor due to impurities such as excessively doped iron (Fe) or carbon (C). It is very degraded, and there is a problem in that it promotes an increase in leakage current due to a fatal crystal defect, that is, an increase in dislocation density. In addition, due to the low crystal quality of the gallium nitride (GaN) buffer layer, there is a problem in that the gallium nitride (GaN) channel layer and aluminum gallium nitride (AlGaN) barrier layer, which are grown on top of the gallium nitride (GaN) buffer layer in a continuous process, also have low crystal quality. .

Accordingly, in order to improve crystal quality, the GaN on Sapphire method, which has the best crystal quality, is widely used next to power semiconductor devices manufactured using the GaN on GaN method, and the epitaxial film deposition technology for this method has already been developed and matured. However, the only drawback of the GaN on Sapphire method is that sapphire's heat dissipation ability is poor, so there is a limit to its application to high-output products.

To overcome this, high-output products have been developed using silicon carbide (SiC) and silicon (Si) growth substrates with high heat dissipation ability. However, in terms of performance, crystal quality, defects, and cost, it is necessary to develop products grown on sapphire growth substrates. It is inferior to epitaxy.

Furthermore, in order to improve the heat dissipation performance of the power semiconductor device, if the growth substrate is completely removed and a high heat dissipation support substrate is bonded, the heat dissipation performance of the power semiconductor device can be greatly improved. There is a problem that adversely affects the long-term reliability of the power semiconductor device due to thermo-mechanical shock or material diffusion during the bonding process.

Republic of Korea Patent Publication No. 10-2019-0074774

The purpose of the present invention is to solve the above-described conventional problems, by manufacturing a power semiconductor device using a template for semiconductor growth containing an ultra-thin sapphire seed layer, thereby providing a high heat dissipation support substrate. The present invention provides a method of manufacturing a power semiconductor device using a template for semiconductor growth, in which defects in bonded power semiconductor devices can be significantly reduced and high performance power semiconductor devices can be manufactured.

The above object is, according to the present invention, a preparation step of preparing a first growth substrate and a second growth substrate; A bonding step of bonding the first growth substrate and the second growth substrate through a bonding layer; A molding step of manufacturing a template by molding the second growth substrate into an ultra-thin shape so that the second growth substrate functions as a seed layer; and a device forming step of forming a power semiconductor device on the second growth substrate of the template. This is achieved by a method of manufacturing a power semiconductor device using a template for semiconductor growth.

Additionally, the first growth substrate and the second growth substrate may be sapphire substrates.

Additionally, the thickness of the molded second growth substrate may be less than 50㎛.

Additionally, a sacrificial separation layer may be disposed on at least one of the upper surface of the first growth substrate and the lower surface of the second growth substrate.

Additionally, in the device forming step, the bonding layer and the first growth substrate may be separated from the second growth substrate, and the second growth substrate and the support substrate may be bonded through a bonding layer.

Additionally, a reinforcing layer may be disposed on at least one of the upper and lower surfaces of the bonding layer to strengthen the bonding force of the bonding layer and cause condensation stress.

Additionally, in the device forming step, a via hole may be formed in the second growth substrate, and then a heat dissipation portion may be formed in the via hole.

Additionally, the heat dissipation unit may be connected to the electrode of the power semiconductor device through a connection part.

In addition, the device forming step includes a first step of bonding the ultra-thin molded second growth substrate and the support substrate through a bonding layer, and the bonding layer and the sacrificial separation layer disposed on the lower surface of the second growth substrate. a second step of separating the first growth substrate, and a third step of growing a semiconductor layer on the sacrificial isolation layer, or growing the semiconductor layer on the second growth substrate when the sacrificial isolation layer is removed; It may include a fourth step of forming a power semiconductor device on the second growth substrate by performing a fab process on the grown semiconductor layer.

In addition, the device forming step includes a first step of growing a semiconductor layer on the ultra-thin molded second growth substrate, and performing a fab process on the grown semiconductor layer to generate power on the second growth substrate. A second step of forming a semiconductor device, a third step of bonding the upper part of the power semiconductor device and the first temporary substrate through an adhesive layer, and the bonding layer and the sacrificial separation layer disposed on the lower surface of the second growth substrate. A fourth step of separating the first growth substrate, a fifth step of bonding the sacrificial separation layer and the support substrate through a first bonding layer, and bonding the adhesive layer and the first temporary substrate from the top of the power semiconductor device. A sixth step of separation may be included.

Additionally, in the fifth step, the sacrificial separation layer and the support substrate are bonded through the bonding layer, and the support substrate and the second temporary substrate are bonded through the lower bonding layer, and the sixth step is to bond the power After separating the adhesive layer and the first temporary substrate from the top of the semiconductor device, the second temporary substrate can be separated from the lower adhesive layer.

Additionally, in the third step, after forming a protective layer on the power semiconductor device, the protective layer and the first temporary substrate may be adhered through the adhesive layer.

Additionally, in the fifth step, after forming a surface texture pattern on the sacrificial separation layer, the sacrificial separation layer and the support substrate can be bonded through a bonding layer.

Additionally, the semiconductor layer may include at least one of a buffer layer, a channel layer, and a barrier layer.

According to the present invention, by manufacturing a power semiconductor device using a template for semiconductor growth containing an ultra-thin sapphire seed layer, defects in the power semiconductor device to which the high heat dissipation support substrate is bonded can be significantly reduced. This has the effect of enabling the manufacture of high-performance power semiconductor devices.

In addition, according to the present invention, when growing a Group 3 nitride semiconductor, the thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) with the sapphire growth substrate is completely eliminated. A template for semiconductor growth that can be solved can be provided, so the defect rate of the manufactured power semiconductor device can be significantly lowered.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within the range apparent to those skilled in the art from the contents described below.

1 is a flowchart of a method of manufacturing a power semiconductor device using a template for semiconductor growth according to first to third embodiments of the present invention;
Figure 2 shows the process of manufacturing a template by a power semiconductor device manufacturing method using a template for semiconductor growth according to the first to third embodiments of the present invention;
Figure 3 is a flowchart of the device forming step of the power semiconductor device manufacturing method using a template for semiconductor growth according to the first embodiment of the present invention;
Figure 4 shows the process of forming a power semiconductor device on a template in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first embodiment of the present invention;
Figure 5 is a flowchart of the device formation step of the power semiconductor device manufacturing method using a template for semiconductor growth according to the second embodiment of the present invention;
Figure 6 shows the process of forming a power semiconductor device on a template in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the second embodiment of the present invention;
Figure 7 shows the formation of a surface texture pattern on the sacrificial isolation layer in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the second or third embodiment of the present invention;
Figure 8 is a flowchart of the device formation step of the power semiconductor device manufacturing method using a template for semiconductor growth according to the third embodiment of the present invention;
Figure 9 shows the process of forming a power semiconductor device on the template of the power semiconductor device manufacturing method using a template for semiconductor growth according to the third embodiment of the present invention;
Figure 10 shows a heat dissipation portion formed on a second growth substrate in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first to third embodiments of the present invention;
Figure 11 shows a heat dissipation portion and a connection portion formed on a second growth substrate in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first to third embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through illustrative drawings. When adding reference numerals to components in each drawing, it should be noted that identical components are given the same reference numerals as much as possible even if they are shown in different drawings.

Additionally, when describing embodiments of the present invention, if detailed descriptions of related known configurations or functions are judged to impede understanding of the embodiments of the present invention, the detailed descriptions will be omitted.

Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the component is not limited by the term.

From now on, with reference to the attached drawings, a method (S100) for manufacturing a power semiconductor device using a template for semiconductor growth according to the first embodiment of the present invention will be described in detail.

1 is a flowchart of a method of manufacturing a power semiconductor device using a template for semiconductor growth according to first to third embodiments of the present invention, and FIG. 2 is a semiconductor device manufacturing method according to first to third embodiments of the present invention. It shows the process of manufacturing a template by a power semiconductor device manufacturing method using a template for growth, and Figure 3 shows a device of the power semiconductor device manufacturing method (S100) using a template for semiconductor growth according to the first embodiment of the present invention. This is a flow chart of the forming step (S140), and Figure 4 shows the process of forming a power semiconductor device on the template of the power semiconductor device manufacturing method (S100) using a template for semiconductor growth according to the first embodiment of the present invention. FIG. 10 shows a heat dissipation portion formed on a second growth substrate in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first to third embodiments of the present invention, and FIG. It shows that a heat dissipation part and a connection part are formed on a second growth substrate in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to Examples 1 to 3.

As shown in Figures 1 and 2, the power semiconductor device manufacturing method (S100) using a template for semiconductor growth according to the first embodiment of the present invention includes a preparation step (S110), a bonding step (S120), It includes a forming step (S130) and a device forming step (S140).

The preparation step (S110) is a step of preparing the first growth substrate 11a and the second growth substrate 11b.

Here, the first growth substrate 11a and the second growth substrate 11b are prepared as sapphire substrates, and this sapphire substrate is used by a laser beam (single wavelength light) in the laser lift off (LLO) process. It is an optically transparent and high-temperature heat-resistant substrate that can transmit 100% without absorption (in theory), and can be made of α-phase Al ₂ O ₃ sapphire (including ScAlMgO ₄ ). In addition, the growth substrate is patterned regularly or irregularly with various dimensions (size and shape) at the microscale or nanoscale to minimize crystal defects inside the group III nitride semiconductor epitaxial thin film grown on top. It is also desirable to have a protruding shape.

In addition, the first growth substrate 11a serves as a carrier sapphire substrate and does not require relatively high quality compared to the second growth substrate 11b, but is optically transparent as both sides are polished. It is a requirement.

And the second growth substrate 11b serves as a growth sapphire substrate, and is molded into an ultra-thin type in a later step to function as a seed layer. This second growth substrate 11b must be placed so that the surface on which a group III nitride semiconductor such as gallium nitride (GaN) is grown is the upper surface, and both sides must be polished with high quality to be optically transparent.

The bonding step (S120) is a step of bonding the first growth substrate 11a and the second growth substrate 11b through the bonding layer 12.

In more detail, the bonding layer 12 is formed on the upper surface of the first growth substrate 11a or the lower surface of the second growth substrate 11b, and then bonds the first growth substrate 11a and the second growth substrate 11b. Preferably, after forming the first bonding layer (12a) on the upper surface of the first growth substrate (11a) and forming the second bonding layer (12b) on the lower surface of the second growth substrate (11b), The first bonding layer 12a and the second bonding layer 12b are pressed and bonded to each other at a temperature of less than 300° C. to form the bonding layer 12, thereby forming the first growth substrate 11a and the second growth substrate 11b. can be joined.

This bonding layer 12 is preferably formed of a material that does not melt or decompose even at the growth temperature (around 1000°C) of the group 3 nitride semiconductor layer 110 and does not cause issues such as contamination during the growth process. Specifically, The material forming the bonding layer 12 is preferentially selected as a dielectric material that does not change physical properties in the MOCVD chamber (temperature above 1000°C and reducing atmosphere) in which group III nitride semiconductors are grown, for example, oxidation. _Silicon (SiO ₂ , 0.8ppm), silicon _nitride ( _SiN ), and furthermore, to improve the surface, FOx (Flowable Oxides) such as SOG (Spin On Glass, liquid SiO ₂ ) and HSQ (Hydrogen Silsesquioxane) may be included.

Additionally, a sacrificial isolation layer 13 may be disposed on at least one of the upper surface of the first growth substrate 11a and the lower surface of the second growth substrate 11b.

That is, the sacrificial isolation layer 13 may be disposed on the upper surface, the lower surface, or both the upper and lower surfaces of the bonding layer 12. In this case, the bonding step (S120) is performed by separating the sacrificial isolation layer on the upper surface of the first growth substrate 11a. After forming (13), the first bonding layer (12a) is formed on the upper surface of the sacrificial separation layer (13), and the sacrificial separation layer (13) is formed on the lower surface of the second growth substrate (11b). A second bonding layer (12b) is formed on the lower surface of (13), and then the first bonding layer (12a) and the second bonding layer (12b) are bonded to each other to form the bonding layer (12), thereby forming a first growth substrate ( 11a) and the second growth substrate 11b can be bonded. However, it goes without saying that the sacrificial separation layer 13 may be omitted if the growth substrate can be separated through the bonding layer 12.

Here, the sacrificial separation layer 13 is a layer that is sacrificed and separated when the growth substrate is separated using the laser lift-off (LLO) or chemical lift-off (CLO) technique, and preferentially uses the laser lift-off (LLO) technique. It is preferable that the sacrificial isolation layer 13 is formed of a material that does not melt or decompose even before or after the growth temperature of the group III nitride semiconductor layer 110 and at the same time does not cause issues such as contamination during the growth process.

On the other hand, when the laser lift-off (LLO) technique is used to separate the growth substrate, the sacrificial separation layer 13 is made of a material capable of sacrificial separation by a thermo-chemical decomposition reaction, for example, in the case of a sapphire growth substrate. It may be composed of a Group 3 nitride semiconductor material such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum nitride (InAlN).

In addition, when a chemical lift-off (CLO) technique is used to separate the growth substrate, the sacrificial separation layer 13 may be made of a material containing chromium nitride (CrN), titanium nitride (TiN), etc., which can be wet etched. there is.

The forming step (S130) is a step of manufacturing a template by molding the second growth substrate 11b into an ultra-thin type so that the second growth substrate 11b functions as a semiconductor seed layer.

In order to improve the heat dissipation ability of the power semiconductor device, when the growth substrate is completely removed and the high heat dissipation support substrate 14 is bonded, there is an advantage that the heat dissipation ability of the power semiconductor device can be greatly improved. During the process of bonding the support substrate 14, the long-term reliability of the power semiconductor device may be adversely affected due to thermo-mechanical shock or material diffusion.

Accordingly, in the present invention, a power semiconductor device structure is formed by growing a group III nitride semiconductor layer 110 on a template, but the ultra-thin second growth substrate 11b is left without removing all of the growth substrate of the template. 2 By bonding the high heat dissipation support substrate 14 to the lower part of the growth substrate 11b, the long-term reliability of the power semiconductor device may be adversely affected due to thermo-mechanical shock or material diffusion during the process of bonding the high heat dissipation support substrate 14. You can prevent it from happening.

At this time, the thickness of the molded sapphire second growth substrate 11b is preferably less than 50 μm for heat dissipation of the power semiconductor device.

Meanwhile, the second growth substrate 11b can be formed through a sapphire substrate polishing process that will be described later. At this time, the final thickness (F) to be molded is the thickness (A) of the first growth substrate (11a), the thickness (B) of the second growth substrate (11b), and the total thickness of the bonded substrate prior to polishing molding ( C) and the target thickness (D) of the second growth substrate 11b can be calculated as follows.

i) Thickness (B) of the second growth substrate (11b) - Target thickness (D) of the second growth substrate (11b) = Thickness of the sapphire substrate to be removed by polishing (E)

ii) Total thickness of the bonded substrate prior to polishing (C) - Sapphire substrate thickness to be removed by polishing (E) = Final thickness of the second growth substrate 11b after polishing (F)

In addition, the specific process process is as follows, but is not limited thereto, as long as it is for molding the second growth substrate 11b to the final thickness (F). First, the sapphire of the second growth substrate 11b is mechanically polished at a high speed through a lapping process, and then the second growth substrate 11b is mechanically polished to have an accurate ultra-thin final thickness (F). A mechanical polishing process is performed. Thereafter, in order to enable epitaxial growth of the group III nitride semiconductor as the final forming step, the surface of the second growth substrate 11b is chemically mechanically polished (CMP) to have a surface roughness of 0.5 nm or less. ) process is carried out to complete the molding process.

In addition, if necessary, in order to improve the quality of the group III nitride semiconductor epitaxial thin film after completing the CMP process, various dimensions (sizes) in the microscale or nanoscale are added to the sapphire upper surface of the second growth substrate 11b. It is also desirable to have a protrusion shape patterned regularly or irregularly.

The device forming step (S140) is a step of forming a power semiconductor device on the second growth substrate 11b of the manufactured template. In this embodiment, the HEMT structure is described as an example, but it is not limited to this, and the template of the present invention can also be used in power semiconductor devices for switching or wireless amplifiers such as MOSFET and JFET, semiconductor light emitting devices such as MiniLED or MicroLED, and AlN-based communication filters. This can be applied.

As shown in FIGS. 3 and 4, the device forming step (S140) is in more detail, the first step (S141), the second step (S142), the third step (S143), and the fourth step ( S144).

The first step (S141) is a step of bonding the ultra-thin molded second growth substrate 11b and the final support substrate 14 through the bonding layer 15.

Here, the final support substrate 14 can be selected from among silicon carbide (SiC), silicon (Si), and AlNcera substrates that suit the purpose of the power semiconductor device to be manufactured. Among these, the AlNcera substrate can be selected preferentially due to its advantages such as increased thickness of the stacked structure by matching the thermal expansion coefficient with the HEMT stacked structure, improved composition uniformity, high heat dissipation ability and cost reduction, and enabling IC processing.

In addition, the bonding layer 15 is preferably formed of a material that does not melt or decompose even at the growth temperature (around 1000°C) of the group 3 nitride semiconductor layer 110 and does not cause issues such as contamination during the growth process. The material forming the bonding layer 15 is preferentially selected as a dielectric material that does not change physical properties in the MOCVD chamber (temperature over 1000°C and reducing atmosphere) in which group III nitride semiconductors are grown. For example, Silicon oxide (SiO ₂ , 0.8ppm), silicon _{nitride ( SiN} ppm), and furthermore, for surface improvement, FOx (Flowable Oxides) such as SOG (Spin On Glass, liquid SiO ₂ ) and HSQ (Hydrogen Silsesquioxane) may be included.

More specifically, the bonding layer 15 can be formed on the upper surface of the second growth substrate 11b or the lower surface of the final support substrate 14, and then bond the second growth substrate 11b and the final support substrate 14. Preferably, the first bonding layer 15a is formed on the upper surface of the second growth substrate 11b, the second bonding layer 15b is formed on the lower surface of the final support substrate 14, and then the first bonding layer is formed. The layer 15a and the second bonding layer 15b are pressed and bonded to each other at a temperature of less than 300° C. to form the bonding layer 15, thereby bonding the second growth substrate 11b and the final support substrate 14 to each other. You can.

Meanwhile, at least one of the upper or lower surface of the bonding layer 15, that is, between the bonding layer 15 and the final support substrate 14 or between the bonding layer 15 and the second growth substrate 11b A reinforcing layer that strengthens the bonding force of the bonding layer 15 and causes condensation stress may be disposed. The material constituting this reinforcement layer does not melt even at the growth temperature (around 1000°C) of the group 3 nitride semiconductor layer 110, and can be selected from materials that do not cause problems in the growth of the group 3 nitride semiconductor layer 110. there is.

Here, the reinforcement layer includes, in more detail, a condensation stress layer disposed on the final support substrate and a bonding reinforcement layer disposed on the condensation stress layer.

The condensation stress layer is a layer that causes condensation stress, and is a dielectric material with a higher value of thermal expansion coefficient than the final support substrate 14, such as aluminum nitride (AlN, 4.6 ppm), aluminum nitride oxide (AlNO, 4.6- 6.8ppm), aluminum oxide (Al ₂ O ₃ , 6.8ppm), silicon carbide (SiC, 4.8ppm), silicon carbonitride (SiCN, 3.8-4.8ppm), gallium nitride (GaN, 5.6ppm), gallium nitride oxide ( It is composed of materials that relieve tensile stress, that is, cause condensation stress, such as GaNO, 5.6-6.8ppm), which plays a role in improving product quality through stress control.

The bonding reinforcement layer is a layer introduced to strengthen the bonding force when the second growth substrate 11b is bonded to the final support substrate 14 through the bonding layer 15, and the second bonding layer 15b is formed on the bonding strengthening layer. ) is formed, and the material constituting the bond reinforcement layer is preferably selected from silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), etc.

Meanwhile, in the present invention, the bonding reinforcement layer or the condensation stress layer may be omitted in some cases, and in some cases, the entire reinforcing layer may be omitted so that the final support substrate 14 and the bonding layer 15 can be in direct contact. In this case, the bonding layer 15 may be formed of a material with a higher thermal expansion coefficient than the final support substrate 14, such as silicon (Si), to function as a bonding layer and cause condensation stress.

The second step (S142) is a step of separating the bonding layer 12 and the first growth substrate 11a from the sacrificial separation layer 13 disposed on the lower surface of the second growth substrate 11b. Here, the first growth substrate 11a can be separated using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the sacrificial separation layer 13.

Here, the laser lift-off (LLO) technique is a technique of separating the growth substrate by irradiating an ultraviolet (UV) laser beam with uniform light output, beam profile, and single wavelength to the back of the transparent growth substrate. In this embodiment, the laser lift-off (LLO) technique is used. 1 When the growth substrate 11a is separated, the inside of the Group 3 nitride semiconductor layer 110 bonded to the final support substrate 14 is in a state where stress is completely relieved, and is flat along with the final support substrate 14. ) maintain the status. Thereafter, it is desirable to completely remove the damaged area, contaminated surface residue, and low-quality single crystal thin film area resulting from the separation of the first growth substrate 11a as much as possible.

In addition, the chemical lift-off (CLO) technique refers to mechanically grinding and polishing the back of the first growth substrate 11a, and then completely removing the remaining thin first growth substrate 11a using a wet etching method. This is a technique.

Thereafter, the sacrificial isolation layer 13 may be selectively removed, and if the sacrificial isolation layer 13 is made of a group 3 nitride semiconductor, it may not be removed.

In the third step (S143), the group III nitride semiconductor layer 110 is grown as a single layer or multilayer on the sacrificial isolation layer 13, or when the sacrificial isolation layer 13 is removed in the second step (S142). 2 This is the step of growing the group III nitride semiconductor layer 110 as a single layer or multilayer on the growth substrate 11b.

Here, the group 3 nitride semiconductor layer 110 includes at least one of the buffer layer 111, the channel layer 112, and the barrier layer 113, and the buffer layer 111 and the channel layer ( 112) and the barrier layer 113 may be stacked in order.

This group 3 nitride semiconductor layer 110 is composed of a single or multi-layer group 3 nitride semiconductor, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), etc., which have high temperature (HT) and high resistance (HR) characteristics. Aluminum nitride (AlN), superlattice aluminum gallium nitride/gallium nitride (AlGaN/GaN SLs), superlattice aluminum gallium nitride/gallium nitride (AlN/GaN SLs), superlattice aluminum gallium nitride/aluminum nitride ( AlGaN/AlN SLs), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), gallium nitride/indium aluminum nitride (GaN/InAlN), aluminum scandium nitride (AlScN), gallium nitride/aluminum scandium nitride (GaN/AlScN) It may be composed of etc. For the Group 3 nitride semiconductor layer 110, reducing the density of critical crystal defects, that is, penetration dislocations (existing in a direction perpendicular to the initial growth substrate), is a critical quality factor (≤ Low 108/cm2). For example, in this embodiment, the buffer layer 111 of the group 3 nitride semiconductor layer 110 is made of gallium nitride (GaN) or aluminum nitride (AlN), the channel layer 112 is made of gallium nitride (GaN), and the barrier layer 112 is made of gallium nitride (GaN) or aluminum nitride (AlN). Layer 113 may be formed of aluminum gallium nitride (AlGaN).

The fourth step (S144) is a step of forming a power semiconductor device on the second growth substrate 11b by performing a fab process and a chip process on the grown group III nitride semiconductor layer 110. .

That is, in the fourth step (S144), if necessary according to the device structure of the HEMT, MOSFET, JFET, etc., the group 3 nitride semiconductor layer 110 is etched and then electrically connected to the group 3 nitride semiconductor layer 110. A plurality of electrodes 120 (source electrode 121, drain electrode 122, gate electrode 123, etc. in the case of HEMT) are formed, and the group 3 nitride semiconductor layer 110 or the plurality of electrodes 120 are formed. A power semiconductor device structure is formed on the ultra-thin second growth substrate 11b by performing a fab process and a chip process, such as forming a passivation layer 130 that partially covers it.

Meanwhile, as shown in FIG. 10, when the final support substrate 14 and the bonding layer 15 are each conductive (e.g., Metallic Substrate, Metal Bonding), the device forming step (S140) of the present invention (e.g. For example, in the fourth step (S144), a power semiconductor device structure may be formed, a via hole may be formed in the second growth substrate 11b, and then a heat dissipation portion 140 may be formed in the via hole.

Specifically, in the fourth step (S144), a via hole is formed through laser drilling in an area of the second growth substrate 11b on which the power semiconductor device structure is not formed, and then a metal material is placed in the via hole. By filling the heat dissipation portion 140, an additional heat dissipation passage can be formed. Here, the metal material filled in the via hole is not limited as long as it is a material that has a heat dissipation function.

In addition, as shown in FIG. 11, when the structure of the power semiconductor device is a vertical structure, in the fourth step (S144), the electrode 120 with high calorific value among the electrodes 120 of the power semiconductor device is connected to the connection portion 150. It can be connected to the heat dissipation unit 140 through, and for example, in the case of a HEMT structure, the drain electrode 122 can be connected to the heat dissipation unit 140 through the connection part 150. That is, the connection portion 150 functions as a drain pad, and by disposing a plurality of heat dissipation portions 140 below the drain pad, the effect of reducing chip size and improving heat dissipation performance is expected. Here, the connection part 150 is not limited as long as it is made of a material that can transfer heat generated from the drain electrode 122 to the heat dissipation part 140, and may be formed of the same material as the heat dissipation part 140.

From now on, with reference to the attached drawings, a method (S200) for manufacturing a power semiconductor device using a template for semiconductor growth according to a second embodiment of the present invention will be described in detail.

1 is a flowchart of a method of manufacturing a power semiconductor device using a template for semiconductor growth according to first to third embodiments of the present invention, and FIG. 2 is a semiconductor device manufacturing method according to first to third embodiments of the present invention. It shows the process of manufacturing a template by a power semiconductor device manufacturing method using a template for growth, and Figure 5 shows a device of the power semiconductor device manufacturing method (S200) using a template for semiconductor growth according to the second embodiment of the present invention. This is a flow chart of the forming step (S140), and Figure 6 shows the process of forming a power semiconductor device on the template of the power semiconductor device manufacturing method (S200) using a template for semiconductor growth according to the second embodiment of the present invention. Figure 7 shows the formation of a surface texture pattern on the sacrificial isolation layer 13 in the power semiconductor device manufacturing method using a template for semiconductor growth according to the second or third embodiment of the present invention. , FIG. 10 shows a heat dissipation portion formed on a second growth substrate in the power semiconductor device manufacturing method using a template for semiconductor growth according to the first to third embodiments of the present invention, and FIG. It shows that a heat dissipation portion and a connection portion are formed on a second growth substrate in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first to third embodiments.

As shown in Figures 1 and 2, the power semiconductor device manufacturing method (S200) using a template for semiconductor growth according to the second embodiment of the present invention includes a preparation step (S210), a bonding step (S220), It includes a forming step (S230) and a device forming step (S240).

Here, the contents of the preparation step (S210), the bonding step (S220), and the forming step (S230) for manufacturing the template are described in detail in the power semiconductor device manufacturing method using the template for semiconductor growth according to the first embodiment of the present invention. Since it is the same as (S100), redundant description is omitted.

The device forming step (S240) is a step of forming a power semiconductor device on the second growth substrate 11b of the manufactured template. In this embodiment, the HEMT structure is described as an example, but it is not limited to this, and the template of the present invention can also be used in power semiconductor devices for switching or wireless amplifiers such as MOSFET and JFET, semiconductor light emitting devices such as MiniLED or MicroLED, and AlN-based communication filters. This can be applied.

As shown in FIGS. 5 to 7, the device forming step (S240) is in more detail, the first step (S241), the second step (S242), the third step (S243), and the fourth step ( S244), the fifth step (S245), and the sixth step (S246).

The first step (S141) is a step of growing the group III nitride semiconductor layer 110 as a single layer or multilayer on the second growth substrate 11b formed into an ultra-thin template.

Here, the group 3 nitride semiconductor layer 110 includes at least one of the buffer layer 111, the channel layer 112, and the barrier layer 113, and the buffer layer 111 and the channel layer ( 112) and the barrier layer 113 may be stacked in order.

This group 3 nitride semiconductor layer 110 is composed of a single or multi-layer group 3 nitride semiconductor, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), etc., which have high temperature (HT) and high resistance (HR) characteristics. Aluminum nitride (AlN), superlattice aluminum gallium nitride/gallium nitride (AlGaN/GaN SLs), superlattice aluminum gallium nitride/gallium nitride (AlN/GaN SLs), superlattice aluminum gallium nitride/aluminum nitride ( AlGaN/AlN SLs), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), gallium nitride/indium aluminum nitride (GaN/InAlN), aluminum scandium nitride (AlScN), gallium nitride/aluminum scandium nitride (GaN/AlScN) It may be composed of etc. For the Group 3 nitride semiconductor layer 110, reducing the density of critical crystal defects, that is, penetration dislocations (existing in a direction perpendicular to the initial growth substrate), is a critical quality factor (≤ Low 108/cm2). For example, in this embodiment, the buffer layer 111 of the group 3 nitride semiconductor layer 110 is made of gallium nitride (GaN) or aluminum nitride (AlN), the channel layer 112 is made of gallium nitride (GaN), and the barrier layer 112 is made of gallium nitride (GaN) or aluminum nitride (AlN). Layer 113 may be formed of aluminum gallium nitride (AlGaN).

The second step (S142) is a step of forming a power semiconductor device on the second growth substrate 11b by performing a fab process and a chip process on the grown group III nitride semiconductor layer 110. .

That is, in the second step (S142), if necessary according to the device structure of the HEMT, MOSFET, JFET, etc., the group 3 nitride semiconductor layer 110 is etched and then electrically connected to the group 3 nitride semiconductor layer 110. A plurality of electrodes 120 (source electrode 121, drain electrode 122, gate electrode 123, etc. in the case of HEMT) are formed, and the group 3 nitride semiconductor layer 110 or the plurality of electrodes 120 are formed. A power semiconductor device structure is formed on the ultra-thin second growth substrate 11b by performing a fab process and a chip process, such as forming a passivation layer 130 that partially covers it.

Meanwhile, after completion of the fab process, the second growth substrate (11b) area, which is the sapphire seed area, must be separated by a process such as laser scribing or pattern etching. If separation is not possible, the die may be cut due to material differences when the final substrate is metal. Issues may arise.

The third step (S143) is a step of bonding the upper part of the formed power semiconductor device to the intermediate temporary substrate 17 through the adhesive layer 18.

Here, the intermediate temporary substrate 17 is formed to have a coefficient of thermal expansion (CTE) equal to or similar to that of the final support substrate 14, and the difference in coefficient of thermal expansion (CTE) from the final support substrate 14 does not exceed a maximum of 2 ppm. It is desirable to do so. Sapphire is preferred as the material for this intermediate temporary substrate 17, and silicon carbide or glass whose coefficient of thermal expansion (CTE) is adjusted to have a difference of 2ppm or less from that of the support substrate 14 may be included.

In addition, the adhesive layer 18 may be prepared from various adhesive materials, for example, materials according to various adhesive methods such as Metallic Bonding, Adhesive Bonding, and Direct Bonding, and the intermediate temporary substrate 17 may be formed of a first growth material. The larger the difference in thermal expansion coefficient from the material of the substrate 11a, the more necessary it is to bond at a lower temperature. Therefore, it is desirable to use a material that can be bonded at as low a temperature as possible.

At this time, in the third step (S143), in order to protect the power semiconductor device structure, a protective layer 19 is formed on the upper part of the power semiconductor device, and then the protective layer 19 and the intermediate temporary substrate 17 are bonded to the adhesive layer 18. ) can be bonded through.

This protective layer 19 serves to protect the power semiconductor device when the adhesive layer 18 is removed in the subsequent process, and may be included in or removed from the final power semiconductor device structure, and may be included in the final power semiconductor device structure. In this case, it must be made of a material that can function as the passivation layer 130 with high resistance, and in the case of removal, it must be removed so as not to damage the separately formed passivation layer 130 (i.e., easy to remove). or the etch selectivity must be high). Meanwhile, representative materials of the protective layer 19 may include SiO ₂ , SiN _x , AlN, etc., but are not limited thereto.

In more detail, the adhesive layer 18 may be formed on the upper surface of the protective layer 19 or the lower surface of the intermediate temporary substrate 17, and then bond the second growth substrate 11b and the final support substrate 14, preferably. In other words, the first adhesive layer 18a is formed on the upper surface of the protective layer 19 and the second adhesive layer 18b is formed on the lower surface of the intermediate temporary substrate 17, and then the first adhesive layer 18a and the second adhesive layer are formed. The protective layer 19 and the intermediate temporary substrate 17 can be bonded to each other by pressing and bonding the (18b) to each other at a temperature of less than 300° C. to form the adhesive layer 18. Additionally, a sacrificial separation layer 13 may be disposed between the intermediate temporary substrate 17 and the adhesive layer 18.

The fourth step (S144) is a step of separating the bonding layer 12 and the first growth substrate 11a from the sacrificial separation layer 13 disposed on the lower surface of the second growth substrate 11b. Here, the first growth substrate 11a can be separated using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the sacrificial separation layer 13.

Thereafter, the sacrificial separation layer 13 disposed on the lower surface of the second growth substrate 11b can be removed for the purpose of improving heat dissipation performance, and if removal is not necessary, it is left in the final support substrate 14 in the subsequent process. ) can also be combined with.

In the fifth step (S245), the sacrificial separation layer 13 and the final support substrate 14 are bonded through the bonding layer 15, or when the sacrificial separation layer 13 is removed in the fourth step (S144). This is the step of bonding the second growth substrate 11b and the final support substrate 14 through the bonding layer 15.

Here, the final support substrate 14 is a substrate such as a ceramic substrate with high heat dissipation ability (AlN, SiC, Diamond), a metal substrate (Mo, Cu, MoCu, CuW), a single crystal substrate (Si, SiC), and a composite substrate (CMC). You can select a substrate that suits the purpose of the power semiconductor device you want to manufacture.

In addition, the bonding layer 15 is preferably made of a material that performs metallic bonding (Eutectic Bonding, Diffusion Bonding, Direct Bonding, etc.) for high heat dissipation ability.

More specifically, the bonding layer 15 is formed on the lower surface of the second growth substrate 11b (or the lower surface of the sacrificial separation layer 13) or the upper surface of the final support substrate 14, and then formed on the second growth substrate 11b. and the final support substrate 14 can be bonded, and preferably, the first bonding layer 15a is formed on the lower surface of the second growth substrate 11b (or the lower surface of the sacrificial separation layer 13), and the final support substrate 14 is bonded to the final support substrate 14. After forming the second bonding layer 15b on the upper surface of the substrate 14, the first bonding layer 15a and the second bonding layer 15b are bonded to each other by pressing at a temperature of less than 300° C. to form a bonding layer 15. ), the second growth substrate 11b (or sacrificial separation layer 13) and the final support substrate 14 can be bonded to each other.

Meanwhile, as shown in FIG. 7, when the sacrificial isolation layer 13 disposed on the lower surface of the second growth substrate 11b is a group 3 nitride such as gallium nitride (GaN), the fifth step (S245) is bonding. In order to expand the area, after forming a surface texture pattern on the sacrificial separation layer 13, the sacrificial separation layer 13 and the final support substrate 14 can be bonded through the bonding layer 15. .

Meanwhile, at least one of the upper or lower surface of the bonding layer 15, that is, between the bonding layer 15 and the final support substrate 14 or between the bonding layer 15 and the second growth substrate 11b A reinforcing layer that strengthens the bonding force of the bonding layer 15 and causes condensation stress may be disposed. The material constituting this reinforcement layer does not melt even at the growth temperature (around 1000°C) of the group 3 nitride semiconductor layer 110, and can be selected from materials that do not cause problems in the growth of the group 3 nitride semiconductor layer 110. there is.

Here, the reinforcement layer includes a bond reinforcement layer and a condensation stress layer in more detail, and the following details are the same as the power semiconductor device manufacturing method (S100) using the template for semiconductor growth according to the first embodiment of the present invention described above. Therefore, redundant description is omitted.

The sixth step (S246) is a step of separating the adhesive layer 18 and the intermediate temporary substrate 17 from the top of the power semiconductor device through dry or wet etching, and selectively removing the protective layer 19 if necessary.

Meanwhile, as shown in FIGS. 10 and 11, the device forming step (S240) of the present invention (for example, the sixth step (S246)) can form the heat dissipation portion 140, as described below. is the same as the power semiconductor device manufacturing method (S100) using the template for semiconductor growth according to the first embodiment of the present invention described above, so redundant description is omitted.

From now on, with reference to the attached drawings, a method (S300) for manufacturing a power semiconductor device using a template for semiconductor growth according to a third embodiment of the present invention will be described in detail.

1 is a flowchart of a method of manufacturing a power semiconductor device using a template for semiconductor growth according to first to third embodiments of the present invention, and FIG. 2 is a semiconductor device manufacturing method according to first to third embodiments of the present invention. It shows the process of manufacturing a template by the power semiconductor device manufacturing method using a template for growth, and Figure 8 shows a device of the power semiconductor device manufacturing method (S300) using a template for semiconductor growth according to the third embodiment of the present invention. This is a flowchart of the forming step (S140), and Figure 9 shows the process of forming a power semiconductor device on the template of the power semiconductor device manufacturing method (S300) using a template for semiconductor growth according to the third embodiment of the present invention. Figure 10 shows the heat dissipation portion 140 formed on the second growth substrate 11b in the method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first to third embodiments of the present invention.

As shown in Figures 1 and 2, the power semiconductor device manufacturing method (S300) using a template for semiconductor growth according to the third embodiment of the present invention includes a preparation step (S310), a bonding step (S320), It includes a forming step (S330) and a device forming step (S340).

Here, the contents of the preparation step (S310), the bonding step (S320), and the forming step (S330) for manufacturing the template are described in detail in the power semiconductor device manufacturing method using the template for semiconductor growth according to the first embodiment of the present invention. Since it is the same as (S100), redundant description is omitted.

The device forming step (S340) is a step of forming a power semiconductor device on the second growth substrate 11b of the manufactured template. In this embodiment, the HEMT structure is described as an example, but it is not limited to this, and the template of the present invention can also be used in power semiconductor devices for switching or wireless amplifiers such as MOSFET and JFET, semiconductor light emitting devices such as MiniLED or MicroLED, and AlN-based communication filters. This can be applied.

As shown in Figures 8 and 9, the device forming step (S340) is in more detail, the first step (S341), the second step (S342), the third step (S343), and the fourth step ( S344), the fifth step (S345), and the sixth step (S346).

Here, the first step (S341) and the second step (S342) are the same as the power semiconductor device manufacturing method (S200) using the template for semiconductor growth according to the second embodiment of the present invention described above, so duplicate descriptions are omitted. .

The third step (S343) is a step of bonding the upper part of the formed power semiconductor device and the first temporary substrate 17a through the adhesive layer 18.

Here, the first temporary substrate 17a is formed to have a coefficient of thermal expansion (CTE) equal to or similar to that of the final support substrate 14, and the difference in coefficient of thermal expansion (CTE) from the final support substrate 14 does not exceed a maximum difference of 2 ppm. It is desirable to avoid this. The material for the first temporary substrate 17a is preferably sapphire, and may include silicon carbide or glass whose coefficient of thermal expansion (CTE) is adjusted to have a difference of 2ppm or less from that of the support substrate 14.

In addition, the adhesive layer 18 may be prepared with various adhesive materials, for example, metallic bonding, adhesive bonding, direct bonding, etc., and the first temporary substrate 17a may be prepared with the first temporary substrate 17a. Since the greater the difference in thermal expansion coefficient from the material of the growth substrate 11a, bonding at a lower temperature becomes necessary, it is preferable to use a material that can be bonded at as low a temperature as possible.

At this time, in the third step (S343), in order to protect the power semiconductor device structure, a protective layer 19 is formed on the upper part of the power semiconductor device, and then the protective layer 19 and the first temporary substrate 17a are attached with an adhesive layer ( It can be bonded through 18).

This protective layer 19 serves to protect the power semiconductor device when the adhesive layer 18 is removed in the subsequent process, and may be included in or removed from the final power semiconductor device structure, and may be included in the final power semiconductor device structure. In this case, it must be made of a material that can function as the passivation layer 130 with high resistance, and in the case of removal, it must be removed so as not to damage the separately formed passivation layer 130 (i.e., easy to remove). or the etch selectivity must be high). Meanwhile, representative materials of the protective layer 19 may include SiO ₂ , SiN _x , AlN, etc., but are not limited thereto.

More specifically, the adhesive layer 18 can be formed on the upper surface of the protective layer 19 or the lower surface of the first temporary substrate 17a, and then bond the second growth substrate 11b and the final support substrate 14, Preferably, the first adhesive layer 18a is formed on the upper surface of the protective layer 19, and the second adhesive layer 18b is formed on the lower surface of the first temporary substrate 17a, and then the first adhesive layer 18a and the second adhesive layer 18b are formed on the lower surface of the first temporary substrate 17a. 2 The protective layer 19 and the first temporary substrate 17a can be bonded to each other by pressing and bonding the adhesive layer 18b to each other at a temperature of less than 300° C. to form the adhesive layer 18. Additionally, a sacrificial separation layer 13 may be disposed between the first temporary substrate 17a and the adhesive layer 18.

The fourth step (S344) is a step of separating the bonding layer 12 and the first growth substrate 11a from the sacrificial separation layer 13 disposed on the lower surface of the second growth substrate 11b. Here, the first growth substrate 11a can be separated using a laser lift off (LLO) technique or a chemical lift off (CLO) technique depending on the material of the sacrificial separation layer 13.

Thereafter, the sacrificial separation layer 13 disposed on the lower surface of the second growth substrate 11b can be removed for the purpose of improving heat dissipation performance, and if removal is not necessary, it is left in the final support substrate 14 in the subsequent process. ) can also be combined with.

In the fifth step (S345), the sacrificial separation layer 13 and the final support substrate 14 are bonded through the bonding layer 15, or when the sacrificial separation layer 13 is removed in the fourth step (S144). The second growth substrate 11b and the final support substrate 14 are bonded through the bonding layer 15, and the final support substrate 14 and the second temporary substrate 17b are bonded through the lower bonding layer 20. This is the joining step.

Here, the final support substrate 14 is a substrate such as a ceramic substrate with high heat dissipation ability (AlN, SiC, Diamond), a metal substrate (Mo, Cu, MoCu, CuW), a single crystal substrate (Si, SiC), and a composite substrate (CMC). A substrate suitable for the purpose of the power semiconductor device to be manufactured can be selected, and the second temporary substrate 17b is preferably made of the same material as the first temporary substrate 17a described above.

In addition, the bonding layer 15 and the lower bonding layer 20 are preferably made of a material that performs metallic bonding (Eutectic Bonding, Diffusion Bonding, Direct Bonding, etc.) for high heat dissipation ability.

More specifically, the first bonding layer 15a is formed on the lower surface of the second growth substrate 11b (or the lower surface of the sacrificial separation layer 13) or the upper surface of the final support substrate 14, and then the second growth substrate ( 11b) and the final support substrate 14 can be bonded, and preferably, the first bonding layer 15a is formed on the lower surface of the second growth substrate 11b (or the lower surface of the sacrificial separation layer 13), After forming the second bonding layer 15b on the upper surface of the final support substrate 14, the first bonding layer 15a and the second bonding layer 15b are bonded to each other by pressing at a temperature of less than 300° C. to form a bonding layer. By forming (15), the second growth substrate 11b (or sacrificial separation layer 13) and the final support substrate 14 can be bonded to each other.

In addition, the lower bonding layer 20 can be formed on the lower surface of the final support substrate 14 or the upper surface of the second temporary substrate 17b, and then bond the final support substrate 14 and the second temporary substrate 17b. , Preferably, the first lower bonding layer 20a is formed on the lower surface of the final support substrate 14, and the sacrificial separation layer (20a) is formed on the upper surface of the second temporary substrate 17b (or the second temporary substrate 17b). 13) After forming the second lower bonding layer (20b) on the upper surface of), the first lower bonding layer (20a) and the second lower bonding layer (20b) are bonded to each other by pressing at a temperature of less than 300° C. to form lower bonding. By forming the layer 20, the final support substrate 14 and the second temporary substrate 17b (or the sacrificial separation layer 13) can be bonded to each other.

Meanwhile, when the sacrificial isolation layer 13 disposed on the lower surface of the second growth substrate 11b is a group 3 nitride such as gallium nitride (GaN), the fifth step (S245) is a sacrificial separation layer to expand the bonding area. After forming a surface texture pattern on the layer 13, the sacrificial separation layer 13 and the final support substrate 14 can be bonded through the bonding layer 15.

Meanwhile, at least one of the upper or lower surface of the bonding layer 15, that is, between the bonding layer 15 and the final support substrate 14 or between the bonding layer 15 and the second growth substrate 11b A reinforcing layer may be disposed to strengthen the bonding force of the bonding layer 15 and cause condensation stress. The material constituting this reinforcement layer does not melt even at the growth temperature (around 1000°C) of the group 3 nitride semiconductor layer 110, and can be selected from materials that do not cause problems in the growth of the group 3 nitride semiconductor layer 110. there is.

Here, the reinforcement layer includes a bond reinforcement layer and a condensation stress layer in more detail, and the following details are the same as the power semiconductor device manufacturing method (S100) using the template for semiconductor growth according to the first embodiment of the present invention described above. Therefore, redundant description is omitted.

In the sixth step (S346), the adhesive layer 18 and the first temporary substrate 17a are separated from the upper part of the power semiconductor device through dry or wet etching, and the second temporary substrate 17b is separated from the lower adhesive layer 20. After separation, this is a step of selectively removing the protective layer 19, if necessary. At this time, it is preferable that the sacrificial separation layer 13 on the bottom of the lower bonding layer 20 is removed, and if the lower bonding layer 20 on the bottom of the final support substrate 14 is made of a conductive metallic bonding material, it is not removed and functions as a bonding pad. can be performed.

Meanwhile, as shown in FIGS. 10 and 11, the device forming step (S240) of the present invention (for example, the sixth step (S246)) can form the heat dissipation portion 140, as described below. Since is the same as the power semiconductor device manufacturing method (S100) using the template for semiconductor growth according to the first embodiment of the present invention described above, redundant description will be omitted.

In the above, just because all the components constituting the embodiment of the present invention have been described as being combined or operated in combination, the present invention is not necessarily limited to this embodiment. That is, as long as it is within the scope of the purpose of the present invention, all of the components may be operated by selectively combining one or more of them.

In addition, terms such as “include,” “comprise,” or “have” described above mean that the corresponding component may be present, unless specifically stated to the contrary, and therefore do not exclude other components. Rather, it should be interpreted as being able to include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Commonly used terms, such as terms defined in a dictionary, should be interpreted as consistent with the contextual meaning of the related technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the present invention.

The above description is merely an illustrative explanation of the technical idea of the present invention, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present invention.

Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

S100: Method of manufacturing a power semiconductor device using a template for semiconductor growth according to the first embodiment of the present invention
S110: Preparation stage
S120: Bonding step
S130: Forming step
S140: Device formation step
S141: Step 1
S142: Second stage
S143: Step 3
S144: Step 4
11a: first growth substrate
11b: second growth substrate
12: bonding layer
12a: first bonding layer
12b: second bonding layer
13: Sacrificial separation layer
14: Support substrate
15: bonding layer
15a: first bonding layer
15b: second bonding layer
110: Group 3 nitride semiconductor layer
111: buffer layer
112: channel layer
113: barrier layer
120: electrode
121: source electrode
122: drain electrode
123: gate electrode
130: Passivation layer
140: heat dissipation unit
150: connection part
S200: Method of manufacturing a power semiconductor device using a template for semiconductor growth according to the second embodiment of the present invention
S210: Preparation stage
S220: Bonding step
S230: Forming step
S240: Device formation step
S241: Step 1
S242: Second stage
S243: Step 3
S244: Step 4
S245: Step 5
S246: Step 6
17: Temporary board
18: Adhesive layer
18a: first adhesive layer
18b: second adhesive layer
19: protective layer
S300: Method of manufacturing a power semiconductor device using a template for semiconductor growth according to the third embodiment of the present invention
S310: Preparation stage
S320: Bonding step
S330: Forming stage
S340: Device formation step
S341: Step 1
S342: Second stage
S343: Stage 3
S344: Step 4
S345: Stage 5
S346: Step 6
17a: first temporary substrate
17b: second temporary board
20: lower bonding layer
20a: first lower bonding layer
20b: second lower bonding layer

Claims (14)

A preparation step of preparing a first growth substrate and a second growth substrate;
A bonding step of bonding the first growth substrate and the second growth substrate through a bonding layer;
A molding step of manufacturing a template by molding the second growth substrate into an ultra-thin shape so that the second growth substrate functions as a seed layer; and
A method of manufacturing a power semiconductor device using a template for semiconductor growth, comprising a device forming step of forming a power semiconductor device on the second growth substrate of the template. In claim 1,
The first growth substrate and the second growth substrate,
Method for manufacturing power semiconductor devices using a sapphire substrate, a template for semiconductor growth. In claim 1,
The thickness of the molded second growth substrate is,
Method of manufacturing a power semiconductor device using a template for semiconductor growth that is less than 50㎛. In claim 1,
On at least one of the upper surface of the first growth substrate and the lower surface of the second growth substrate,
A method of manufacturing a power semiconductor device using a template for semiconductor growth in which a sacrificial separation layer is disposed. In claim 1,
The device formation step is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, wherein the bonding layer and the first growth substrate are separated from the second growth substrate, and the second growth substrate and the support substrate are bonded through a bonding layer. In claim 5,
On at least one of the upper and lower surfaces of the bonding layer,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, in which a reinforcing layer that strengthens the bonding force of the bonding layer and causes condensation stress is disposed. In claim 1,
The device formation step is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, comprising forming a via hole in the second growth substrate and then forming a heat dissipation portion in the via hole. In claim 7,
The heat dissipation unit,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, which is connected to the electrode of the power semiconductor device through a connection part. In claim 1,
The device formation step is,
A first step of bonding the ultra-thin molded second growth substrate and the support substrate through a bonding layer;
a second step of separating the bonding layer and the first growth substrate from the sacrificial separation layer disposed on the lower surface of the second growth substrate;
a third step of growing a semiconductor layer on the sacrificial isolation layer, or growing the semiconductor layer on the second growth substrate when the sacrificial isolation layer is removed;
A method of manufacturing a power semiconductor device using a template for semiconductor growth, comprising a fourth step of forming a power semiconductor device on the second growth substrate by performing a fab process on the grown semiconductor layer. In claim 1,
The device formation step is,
A first step of growing a semiconductor layer on the ultra-thin second growth substrate,
A second step of forming a power semiconductor device on the second growth substrate by performing a fab process on the grown semiconductor layer;
A third step of adhering the upper part of the power semiconductor device and the first temporary substrate through an adhesive layer,
a fourth step of separating the bonding layer and the first growth substrate from the sacrificial separation layer disposed on the lower surface of the second growth substrate;
A fifth step of bonding the sacrificial separation layer and the support substrate through a first bonding layer,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, comprising a sixth step of separating the adhesive layer and the first temporary substrate from the top of the power semiconductor device. In claim 10,
The fifth step is,
The sacrificial separation layer and the support substrate are bonded through the bonding layer, and the support substrate and the second temporary substrate are bonded through the lower bonding layer,
The sixth step is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, wherein the adhesive layer and the first temporary substrate are separated from the upper part of the power semiconductor device, and then the second temporary substrate is separated from the lower adhesive layer. In claim 10,
The third step is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, wherein a protective layer is formed on the top of the power semiconductor device and then the protective layer and the first temporary substrate are bonded through the adhesive layer. In claim 10,
The fifth step is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, wherein a surface texture pattern is formed on the sacrificial isolation layer and then the sacrificial isolation layer and the support substrate are bonded through a bonding layer. The method of claim 9 or 10,
The semiconductor layer is,
A method of manufacturing a power semiconductor device using a template for semiconductor growth, including at least one of a buffer layer, a channel layer, and a barrier layer.