KR20230155332A - Image sensor - Google Patents

Abstract

Provides an image sensor. This image sensor includes: a first substrate having a first side and an opposing second side, the first substrate including a pixel array area and an edge area; an anti-reflection structure disposed on the second surface; a pixel separator disposed on the first substrate to separate pixels; and a micro lens array disposed on the anti-reflection structure, wherein the anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film sequentially stacked, wherein the first insulating film and the third insulating film include: The second insulating film and the third insulating film each include different materials, and the third insulating film penetrates the second insulating film and the titanium oxide film at the edge area and contacts the first insulating film.

Description

Image sensor

The present invention relates to image sensors.

An image sensor is a semiconductor device that converts optical images into electrical signals. The image sensor can be classified into a charge coupled device (CCD) type and a complementary metal oxide semiconductor (CMOS) type. The CMOS type image sensor is abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels arranged two-dimensionally. Each of the pixels includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

The problem to be solved by the present invention is to provide an image sensor capable of realizing clear image quality.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

An image sensor according to embodiments of the present invention for achieving the above object includes a first substrate having a first surface and an opposing second surface, the first substrate including a pixel array area and an edge area; an anti-reflection structure disposed on the second surface; a pixel separator disposed on the first substrate to separate pixels; and a micro lens array disposed on the anti-reflection structure, wherein the anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film sequentially stacked, wherein the first insulating film and the third insulating film include: The second insulating film and the third insulating film each include different materials, and the third insulating film penetrates the second insulating film and the titanium oxide film at the edge area and contacts the first insulating film.

An image sensor according to an aspect of the present invention includes a first substrate having a first surface and an opposing second surface, the first substrate including a pixel array area and an edge area; an anti-reflection structure disposed on the second surface; a pixel separator disposed on the first substrate to separate pixels; a color filter disposed on the anti-reflection structure; a micro lens array disposed on the color filter; a first interlayer insulating film disposed on the first side of the first substrate; a first wiring layer disposed within the first interlayer insulating film; a second interlayer insulating film disposed below the first interlayer insulating film; a second wiring layer disposed within the second interlayer insulating film; a second substrate disposed under the second interlayer insulating film; a first contact disposed on a second surface of the first substrate in the edge area; and a second contact that penetrates a portion of the first substrate, the first interlayer insulating film, and the second interlayer insulating film in the edge area and contacts the second wiring layer, wherein the anti-reflection structure is formed by sequentially stacking a first insulating film. , a titanium oxide film, a second insulating film, and a third insulating film, wherein the first insulating film, the second insulating film, and the third insulating film each include different materials, and the third insulating film is formed between the first contact and the third insulating film. It penetrates the second insulating film and the titanium oxide film between the second contacts and comes into contact with the first insulating film.

An image sensor according to another aspect of the present invention includes a first substrate having a first surface and an opposing second surface, the first substrate including a pixel array area and an edge area; an anti-reflection structure disposed on the second surface; a pixel separator disposed on the first substrate to separate pixels; and a micro lens array disposed on the anti-reflection structure, wherein the anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film, which are sequentially stacked. The second insulating film and the third insulating film each include different materials, a groove is formed in the titanium oxide film and the second insulating film on the edge area, the first insulating film is exposed at the bottom of the groove, and the third insulating film is exposed at the bottom of the groove. An insulating film conformally covers the bottom and side surfaces of the groove, and the groove two-dimensionally surrounds the pixel array area.

In the image sensor of the present invention, the anti-reflection structure includes a titanium oxide film. The titanium oxide film overall reduces the reflectivity of all colors of light, and can further reduce the reflectivity of blue light in particular. This can increase the QE (Quantum Efficiency) of the blue pixel.

In the image sensor of the present invention, grooves are formed in the anti-reflection structure between the back contacts, back vias, and back conductive pads in the edge area, and the titanium oxide film can be cut by the grooves. This can prevent leakage current generated by the titanium oxide film between adjacent rear contacts, rear vias, and rear conductive pads. This can prevent operation errors in the image sensor and achieve clear image quality.

1 is a block diagram for explaining an image sensor according to embodiments of the present invention.
Figure 2 is a circuit diagram of an active pixel array of an image sensor according to embodiments of the present invention.
Figure 3 is a plan view of an image sensor according to embodiments of the present invention.
Figure 4 is a cross-sectional view taken along line AA' of Figure 3 according to embodiments of the present invention.
FIG. 5 is a partial plan view of the image sensor of FIG. 3.
FIG. 6 is a top view of a via array disposed in the via area of FIG. 3 according to embodiments of the present invention.
FIG. 7A is an enlarged view of portion 'P1' of FIG. 4 according to embodiments of the present invention.
FIG. 7B is an enlarged view of portion 'P2' of FIG. 4 according to embodiments of the present invention.
FIGS. 8A to 8H are cross-sectional views sequentially showing a method of manufacturing an image sensor having the cross-section of FIG. 4 according to embodiments of the present invention.
Figure 9 is a cross-sectional view taken along line AA' of Figure 3 according to embodiments of the present invention.
10 is a cross-sectional view of an image sensor according to embodiments of the present invention.
FIG. 11A is an enlarged view of portion 'P1' of FIG. 10 according to embodiments of the present invention.
FIG. 11B is an enlarged view of portion 'P2' of FIG. 10 according to embodiments of the present invention.
Figure 12 is a cross-sectional view of an image sensor according to embodiments of the present invention.

Hereinafter, in order to explain the present invention in more detail, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram for explaining an image sensor according to embodiments of the present invention.

Referring to FIG. 1, the image sensor includes an active pixel sensor array (1001), a row decoder (1002), a row driver (1003), a column decoder (1004), and a timing sensor. It may include a timing generator (1005), a correlated double sampler (CDS) (1006), an analog to digital converter (ADC) (1007), and an input/output buffer (I/O buffer (1008)). .

The active pixel sensor array 1001 includes a plurality of unit pixels arranged two-dimensionally and can convert optical signals into electrical signals. The active pixel sensor array 1001 may be driven by a plurality of driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal from the row driver 1003. Additionally, the converted electrical signal may be provided to a correlated double sampler 1006.

The row driver 1003 may provide a plurality of driving signals for driving a plurality of unit pixels to the active pixel sensor array 1001 according to a result decoded by the row decoder 1002. When unit pixels are arranged in a matrix, driving signals may be provided for each row.

The timing generator 1005 may provide timing signals and control signals to the row decoder 1002 and the column decoder 1004.

A correlated double sampler (CDS) 1006 may receive, hold, and sample the electrical signal generated by the active pixel sensor array 1001. The correlated double sampler 1006 can double sample a specific noise level and a signal level caused by an electrical signal and output a difference level corresponding to the difference between the noise level and the signal level.

The analog-to-digital converter (ADC) 1007 can convert the analog signal corresponding to the difference level output from the correlated double sampler 1006 into a digital signal and output it.

The input/output buffer 1008 latches a digital signal, and the latched signal can be sequentially output as a digital signal to an image signal processor (not shown) according to the decoding result in the column decoder 1004.

Figure 2 is a circuit diagram of an active pixel array of an image sensor according to embodiments of the present invention.

Referring to FIGS. 1 and 2 , the sensor array 1001 includes a plurality of unit pixels UP, and the unit pixels UP may be arranged in a matrix form. Each unit pixel (UP) may include a transfer transistor (TX). Each unit pixel UP may further include logic transistors RX, SX, and DX. The logic transistor may be a reset transistor (RX), a select transistor (SX), or a source follower transistor (DX). The transfer transistor (TX) may include a transfer gate (TG). Each unit pixel UP may further include a photoelectric conversion unit PD and a floating diffusion area FD. Logic transistors (RX, SX, DX) may be shared among a plurality of unit pixels (UP).

The photoelectric conversion unit (PD) can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion unit (PD) may include a photo diode, a photo transistor, a photo gate, a pinned photo diode, or a combination thereof. The transfer transistor (TX) can transmit the charge generated in the photoelectric conversion unit (PD) to the floating diffusion region (FD). The floating diffusion region (FD) can receive charges generated in the photoelectric conversion unit (PD) and store them cumulatively. The source follower transistor (DX) can be controlled according to the amount of photocharges accumulated in the floating diffusion region (FD).

The reset transistor (RX) may periodically reset the charges accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) may be connected to the floating diffusion region (FD), and the source electrode may be connected to the power supply voltage (VDD). When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Accordingly, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be discharged and the floating diffusion region FD may be reset.

The source follower transistor (DX) including the source follower gate electrode (SF) may serve as a source follower buffer amplifier. The source follower transistor (DX) can amplify the potential change in the floating diffusion region (FD) and output it to the output line (Vout).

The selection transistor SX including the selection gate electrode SEL can select unit pixels UP to be read row by row. When the selection transistor (SX) is turned on, the power supply voltage (VDD) may be applied to the drain electrode of the source follower transistor (DX).

Figure 3 is a plan view of an image sensor according to embodiments of the present invention. Figure 4 is a cross-sectional view taken along line A-A' of Figure 3 according to embodiments of the present invention. FIG. 5 is a partial plan view of the image sensor of FIG. 3. FIG. 6 is a top view of a via array disposed in the via area of FIG. 3 according to embodiments of the present invention. FIG. 7A is an enlarged view of portion 'P1' of FIG. 4 according to embodiments of the present invention. FIG. 7B is an enlarged view of portion 'P2' of FIG. 4 according to embodiments of the present invention.

Referring to FIGS. 3 and 4 , the image sensor 500 according to embodiments of the present invention may have a structure in which first and second sub-chips CH1 and CH2 are bonded. The first sub-chip CH1 may be placed on the second sub-chip CH2. The first sub-chip CH1 includes a first substrate 1. The first substrate 1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon on insulator (SOI) substrate. The first substrate 1 may be doped with an impurity of a first conductivity type, for example. For example, the first conductivity type may be P type. The first substrate 1 includes a front surface 1a and a back surface 1b that are opposite to each other. In this specification, the front surface 1a may be referred to as the first surface 1a, and the rear surface 1b may be referred to as the second surface 1b. The first substrate 1 may include a pixel array area (APS), an optical black area (OB), and an edge area (ER).

The pixel array area (APS) and the optical black area (OB) may each include a plurality of unit pixels (UP). The optical black area (OB) may surround the pixel array area (APS). The edge area ER may surround the pixel array area APS and the optical black area OB. The edge area ER may include a contact area BR1, a via area BR2, and a pad area PR. The via area BR2 may be located between the contact area BR1 and the pad area PR. The pad area (PR) may be located at the outermost part of the edge area (ER). In this specification, 'via' may also be called 'contact'. Alternatively, 'contact' may also be named 'via'.

A first pixel separator DTI1 may be disposed within the first substrate 1 in the pixel array area APS and the optical black area OB to separate/limit the unit pixels UP. The first pixel separator DTI1 may extend to the contact area BR1 of the edge area ER. The first pixel separator DTI1 may have a mesh shape in plan view.

Back contacts BCA, back vias BVS, and back conductive pads PAD may be disposed on the back surface 1b of the first substrate 1 in the edge area ER. Referring to FIGS. 4 and 6 , the second pixel separator DTI2 may respectively surround the rear vias BVS from a plan view. The back vias BVS may include first back vias BVS(1) and second back vias BVS(2). Column signals and/or row signals may be transmitted between the first and second sub-chips (CH1, CH2) through the back vias (BVS).

The first pixel separator DTI1 and the second pixel separators DTI2 are each located within a deep trench 22 formed from the front surface 1a to the back surface 1b of the first substrate 1. The first pixel separator DTI1 and the second pixel separators DTI2 may be frontside deep trench isolation (FDTI). The first pixel separator DTI1 and the second pixel separators DTI2 may include a buried insulating pattern 12, a separate insulating pattern 14, and a separate conductive pattern 16, respectively. The buried insulating pattern 12 may be interposed between the separation conductive pattern 16 and the first interlayer insulating layer IL. The separation insulating pattern 14 may be interposed between the separation conductive pattern 16 and the first substrate 1 and between the buried insulating pattern 12 and the first substrate 1.

The buried insulating pattern 12 and the separated insulating pattern 14 may be formed of an insulating material having a refractive index different from that of the first substrate 1. The buried insulating pattern 12 and the separated insulating pattern 14 may include, for example, silicon oxide. The separation conductive pattern 16 may be spaced apart from the first substrate 1 . The separation conductive pattern 16 may include a polysilicon film or a silicon germanium film doped with impurities. The impurity doped into the polysilicon or silicon germanium film may be, for example, one of boron, phosphorus, and arsenic. Alternatively, the separation conductive pattern 16 may include a metal film.

The first pixel separator DTI1 and the second pixel separators DTI2 each have a narrower width from the front side 1a to the back side 1b of the first substrate 1, as shown in FIG. 4 . In this specification, the term 'width' may also be replaced with the term 'thickness' in a specific direction. The second pixel separator DTI2 may also be called a ‘substrate separator’.

In the unit pixels UP, photoelectric conversion units PD may be disposed within the first substrate 1, respectively. The photoelectric conversion units PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N-type. The N-type impurity doped in the photoelectric conversion unit PD may form a PN junction with the P-type impurity doped in the surrounding first substrate 1 to provide a photodiode.

Element isolation parts (STI) may be disposed within the first substrate 1 adjacent to the front surface 1a. The device isolation portions (STI) may be penetrated by the first pixel isolation portion (DTI1). The device isolation units (STI) may define active areas (ACT) adjacent to the front surface (1a) in each unit pixel (UP). The active areas ACT may be provided for the transistors TX, RX, DX, and SX of FIG. 2.

Referring to FIG. 4 , a transfer gate TG may be disposed on the front surface 1a of the first substrate 1 in each unit pixel UP. A portion of the transfer gate TG may extend into the first substrate 1. The transmission gate (TG) may be a vertical type. Alternatively, the transfer gate TG may be a planar type that does not extend into the first substrate 1 and is flat. A gate insulating layer (Gox) may be interposed between the transfer gate (TG) and the first substrate (1). A floating diffusion region FD may be disposed in the first substrate 1 on one side of the transfer gate TG. For example, the floating diffusion region FD may be doped with impurities of the second conductivity type.

The image sensor 500 may be a rear light-receiving image sensor. Light may be incident into the first substrate 1 through the rear surface 1b of the first substrate 1. Electron-hole pairs may be created at the PN junction by incident light. Electrons generated in this way can be moved to the photoelectric conversion unit (PD). When a voltage is applied to the transfer gate (TG), the electrons may move to the floating diffusion region (FD).

As shown in FIG. 5 , a reset gate RG may be disposed adjacent to the transfer gate TG on the front surface 1a in one of the unit pixels UP. In another one of the unit pixels UP, a source follower gate SF and a selection gate SEL may be disposed adjacent to the transfer gate TG on the front surface 1a. The gates (TG, RG, SF, and SEL) may respectively correspond to the gates of the transistors (TX, RX, DX, and SX) of FIG. 2. The gates TG, RG, SF, and SEL may overlap the active regions ACT. In this example, the reset transistor (RX), the selection transistor (SX), and the source follower transistor (DX) may be shared between two adjacent unit pixels (UP).

A first unit pixel UP(1) and a second unit pixel UP(2) may be disposed in the optical black area OB of the first substrate 1. In the first unit pixel UP(1), a black photoelectric conversion unit PD' is provided within the first substrate 1. A dummy area PD'' may be provided in the first substrate 1 in the second unit pixel UP(2). For example, the black photoelectric conversion unit PD' may be doped with impurities of a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, n-type. The pixel array area (APS) may include a plurality of unit pixels (UP). The black photoelectric conversion unit (PD') has a similar structure to the photoelectric conversion unit (PD), but may not perform the same operation (i.e., receiving light and generating an electrical signal) as the photoelectric conversion unit (PD). . The dummy region PD'' may not be doped with impurities. The signal generated in the dummy area PD'' can be used as information to remove process noise later.

The first sub-chip CH1 further includes first interlayer insulating films IL disposed on the front surface 1a. The first interlayer insulating films IL may be formed as a multilayer film of at least one film selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low-k dielectric film. First wires 15 may be disposed between or within the first interlayer insulating films IL. The floating diffusion region FD may be connected to the first wires 15 by a first contact plug 17 . The first contact plug 17 may penetrate the first interlayer insulating film IL closest to the front surface 1a (lowest layer) among the first interlayer insulating films IL in the pixel array area APS. there is.

The second sub-chip CH2 may include a second substrate SB2, peripheral transistors PTR disposed thereon, and second interlayer insulating films IL2 covering them. Second wires 217 may be disposed within the second interlayer insulating films IL2. The second sub-chip CH1 may include circuits for storing electrical signals generated in the first sub-chip CH1.

Referring to FIGS. 4, 7a, and 7b, an anti-reflection structure AL is disposed on the rear surface 1b of the first substrate 1. The anti-reflection structure AL includes a first insulating film A1, a titanium oxide film A2, a second insulating film A3, and a third insulating film A4 that are sequentially stacked. The first insulating layer A1, the second insulating layer A3, and the third insulating layer A4 may each include different materials. Preferably, the first insulating layer A1 includes aluminum oxide, the second insulating layer A3 includes silicon oxide, and the third insulating layer A4 includes hafnium oxide.

In this specification, the first insulating film (A1) is referred to as a ‘first anti-reflection film’, the titanium oxide film (A2) is referred to as a ‘second anti-reflection film’, the second insulating film (A3) is referred to as a ‘third anti-reflection film’, and The third insulating layer A4 may be called a ‘fourth anti-reflection layer’.

The first substrate 1 has a first refractive index (n1), the first insulating film (A1) has a second refractive index (n2), and the titanium oxide film (A2) has a third refractive index (n3), The second insulating layer A3 may have a fourth refractive index n4. The average value {(n2+n3)/2} of the second refractive index (n2) and the third refractive index (n3) is smaller than the first refractive index (n1) and greater than the fourth refractive index (n4). The first refractive index (n1) is preferably 4.0 to 4.4. The second refractive index (n2) is 2.0 to 3.0. The third refractive index (n3) is 2.2 to 2.8. The fourth refractive index (n4) is 1.0 to 1.9.

As shown in FIG. 7B, the first insulating film A1 has a first thickness T1, the titanium oxide film A2 has a second thickness T2, and the second insulating film A3 has a third thickness T3. , the third insulating layer A4 may have a fourth thickness T4. At this time, the second thickness T2 is greater than the first thickness T1 and the fourth thickness T4, respectively, and is smaller than the third thickness T3.

Preferably, the first thickness (T1) is 10Å to 100Å. The second thickness (T2) is 100Å to 600Å. The third thickness (T3) is 600Å to 900Å. The fourth thickness (T4) is 20Å to 200Å.

Due to the relationship between these refractive indices and/or the relationship between the thicknesses, as shown in FIG. 7B, the light L1 incident on the micro lens ML is refracted and passes through the multilayer structure of the anti-reflection structure AL to be transmitted to the photoelectric conversion unit PD. ), you can easily get hired. As a result, it is possible to provide an image sensor 500 with clear image quality by increasing the light reception rate.

Additionally, in the image sensor 500 according to the present invention, the anti-reflection structure (AL) includes a titanium oxide film (A2). The titanium oxide film (A2) overall reduces the reflectivity of all colors of light, and can further reduce the reflectivity of blue light in particular. This can increase the QE (Quantum Efficiency) of the blue pixel.

The first insulating layer A1 may also serve as a negative fixed charge layer. This can improve dark current and white spot.

3, 4, and 7A, the third insulating layer A4 penetrates the second insulating layer A3 and the titanium oxide layer A2 in the edge region ER to form the first insulating layer A1. ) is in contact with. Grooves GR are formed in the second insulating layer A3 and the titanium oxide layer A2. The third insulating film A4 may conformally cover the side and bottom surfaces of the grooves GR. The grooves GR may surround the pixel array area APS and the optical black area OB in a two-dimensional manner as shown in FIG. 3 .

Referring to FIGS. 3 and 4 , back surface contacts BCA may be disposed on the back surface 1b of the first substrate 1 in the contact area BR1. First back vias BVS(1) may be disposed on the back surface 1b of the first substrate 1 in the via area BR2. Backside conductive pads (PAD) and second backside vias (BVS(2)) may be disposed on the backside 1b of the first substrate 1 in the pad area PR. The second rear vias (BVS(2)) may be arranged in groups of a predetermined number, respectively, around the rear conductive pads (PAD). External signals can be input/output through rear conductive pads (PAD). The rear conductive pads (PAD) can be an interface for external signals.

As shown in FIG. 3, the grooves GR may surround the rear contacts BCA. The grooves GR may not be interposed between the rear contacts BCA. The grooves GR may respectively surround the first rear vias BVS(1). The grooves GR may surround each of the rear conductive pads PAD. The grooves GR may surround a predetermined number of second rear vias BVS(2) at once. Some of the grooves GR may be connected to each other.

The arrangement of the first back vias BVS(1) is not limited to that shown in FIG. 3 and may vary. For example, as shown in FIG. 6, the first back vias BVS(1) may form a back via array BVSA in the via area BR2. That is, the first back vias BVS(1) may be arranged in a predetermined number of columns and rows. The grooves GR may respectively surround the first rear vias BVS(1). In FIG. 6, the first gap DS1 between one first rear via (BVS(1)) and the second pixel separator DTI2 adjacent thereto is equal to the distance between the second pixel separator DTI2 and the groove GR adjacent thereto. It is greater than the second gap between the liver (DS2). Adjacent second pixel separators DTI2 may be spaced apart from each other by a third distance DS3. The third gap DS3 may be larger than the second gap DS2 and smaller than the first gap DS1. The first spacing DS1 may be, for example, 1.5 μm to 2.5 μm. The second spacing DS2 may be 0.1 μm to 0.5 μm. The third spacing DS3 may be 0.5 μm to 1.5 μm.

4 and 7A, the back surface contacts (BCA), the first back surface vias (BVS(1)), the second back surface vias (BVS(2)), and the back surface conductive pads (PAD) are anti-reflective. It penetrates at least a portion of the structure AL and the first substrate 1. Backside contacts (BCA) are disposed within the first backside trench (46). The back contacts BCA include a first conductive pattern 52a and a first metal pattern 54a. The first conductive pattern 52a may conformally cover the side and bottom surfaces of the first rear trench 46. The first conductive pattern 52a may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The first metal pattern 54a may include aluminum, for example. The first metal pattern 54a fills the first backside trench 46.

The rear contacts BCA may contact the isolation conductive pattern 16 of the first pixel isolation unit DTI1. A negative bias may be applied to the isolation conductive pattern 16 of the first pixel isolation unit DTI1 through the back contacts BCA. Separate conductive pattern 16 may serve as a common bias line. As a result, holes that may exist on the surface of the first substrate 1 in contact with the first pixel separator DTI1 are captured, thereby improving dark current characteristics.

The first rear vias BVS(1) are respectively disposed in the first holes H1. The first rear vias BVS(1) may partially penetrate the anti-reflection structure AL, the first substrate 1, the first interlayer insulating layer IL1, and the second interlayer insulating layer IL2. The first rear vias BVS(1) may connect some of the first wires 15 and some of the second wires 217. The first rear vias BVS(1) may conformally fill the inner wall and bottom surface of the first holes H1. The first back vias BVS(1) may include the same material and have the same thickness as the first conductive pattern 52a. The first back vias (BVS(1)) may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

One of the first back vias BVS(1) may be electrically connected to one of the back contacts BCA by one of the back connection wires 52b. The rear connection wire 52b is disposed on the anti-reflection structure AL. The rear connection wire 52b may include the same material as the first conductive pattern 52a and may have the same thickness. The rear connection wiring 52b may have a single-layer or multi-layer structure of at least one of a titanium film, a titanium nitride film, and a tungsten film.

A rear conductive pad (PAD) is disposed within the second rear trench 60. The back conductive pad (PAD) includes a second conductive pattern 52c and a second metal pattern 54b. The second conductive pattern 52c may conformally cover the side and bottom surfaces of the second rear trench 60. The second conductive pattern 52c may include the same material and have the same thickness as the first conductive pattern 52a. The second conductive pattern 52c may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The second metal pattern 54b may include aluminum, for example. The second metal pattern 54b fills the second rear trench 60.

The second back vias BVS(2) are respectively disposed in the second holes H2. The second back vias BVS(2) may partially penetrate the anti-reflection structure AL, the first substrate 1, the first interlayer insulating film IL1, and the second interlayer insulating film IL2. The second rear vias (BVS(2)) may be connected to some of the second wires 217. Although not shown, the second back vias BVS(2) may be connected to some of the first wires 15. The second back vias BVS(2) may conformally fill the inner wall and bottom surface of the second holes H2. The second rear vias BVS(2) may include the same material and have the same thickness as the first conductive pattern 52a. The second rear vias (BVS(2)) may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. One of the second back vias BVS(2) may be electrically connected to one of the back conductive pads PAD by another one of the back connection wires 52b.

The grooves GR may include first to fifth grooves GR(1) to GR(5). The first groove GR(1) may be interposed between the optical black area OB and the contact area BR1. The second groove GR(2) may be interposed between the back surface contacts BCA and the first back vias BVS(1). The third groove GR(3) may be interposed between the first rear vias BVS(1) and the rear conductive pads PAD. The fourth groove GR(4) may be interposed between the rear conductive pads PAD and the second rear vias BVS(2). The fifth groove GR(5) is spaced apart from the second rear vias BVS(2) and may be disposed on one side of the second rear vias BVS(2).

One of the rear connection wires 52b may conformally cover the sidewall and bottom surface of the third insulating layer A4 within the second groove GR(2). Another one of the rear connection wires 52b may conformally cover the sidewall and bottom surface of the third insulating layer A4 within the fourth groove GR(4).

The titanium oxide film A2 is broken by the grooves GR. The titanium oxide film (A2) may have stronger conductivity than other insulating films. If there are no grooves GR, unwanted leakage current may occur between the back surface contacts (BCA), back vias (BVS), and back conductive pads (PAD) adjacent to each other due to the titanium oxide film (A2). This may cause operation errors or deterioration of image quality in the image sensor. However, in the present invention, the titanium oxide film (A2) is broken by the grooves (GR), thereby preventing unwanted leakage current between the adjacent back contacts (BCA), back vias (BVS), and back conductive pads (PAD). Occurrence can be prevented. This can prevent image sensor operation errors or image quality deterioration.

A first optical black pattern 52p is disposed on the anti-reflection structure AL in the edge region ER. The first optical black pattern 52p may include the same material and have the same thickness as the first conductive pattern 52a. The first optical black pattern 52p may have a single-layer or multi-layer structure of at least one of a titanium layer, a titanium nitride layer, and a tungsten layer.

Light-blocking grid patterns 48a may be disposed on the anti-reflection structure AL in the pixel array area APS. Low-refraction grid patterns 50a may be disposed on the light-shielding grid patterns 48a, respectively. The light-shielding grid pattern 48a and the low-refraction grid pattern 50a overlap the first pixel separator DTI1 and may have a two-dimensional grid shape. For example, the light blocking grid pattern 48a may include at least one of titanium and titanium nitride. The low-refraction grid patterns 50a have the same thickness and may include the same organic material. The low-refractive grid pattern 50a may have a smaller refractive index than the color filters CF1 and CF2. For example, the low-refractive grid pattern 50a may have a refractive index of about 1.3 or less. The light-shielding grid pattern 48a and the low-refraction grid pattern 50a can prevent crosstalk between adjacent unit pixels UP.

A low-refraction residual pattern 50r may be disposed within the grooves GR to fill the grooves GR. A first low refractive index protection pattern 50b is disposed in the first hole H1. A second low-refraction protection pattern 50c is disposed in the second hole H2. The low refractive index residual pattern 50r, the first low refractive index protection pattern 50b, and the second low refractive protection pattern 50c may have the same material as the low refractive index grid pattern 50a. The upper surfaces of the first low refractive index protection pattern 50b and the second low refractive index protection pattern 50c may be concave.

Color filters CF1 and CF2 may be disposed between the low-refraction grid patterns 50a in the pixel array area APS. The color filters CF1 and CF2 may each have one of blue, green, and red. As another example, the color filters CAF1 and CF2 may include other colors such as cyan, magenta, or yellow. In the image sensor according to this example, the color filters CF1 and CF2 may be arranged in a Bayer pattern. In another example, the color filters CF1 and CF2 may be arranged in a 2x2 arrangement of a tetra pattern, a 3x3 arrangement of a nona pattern, or a 4x4 arrangement of a hexadeca pattern.

A capping pattern (CFR) may be disposed on the first low refractive index protection pattern 50b and the second low refractive index protection pattern 50c, respectively. The capping pattern (CFR) may include, for example, a photoresist material. The capping pattern (CFR) can prevent moisture absorption in the rear vias (BVS) and eliminate the level difference.

A second optical black pattern (CFB) may be disposed on the protective film 56. For example, the second optical black pattern (CFB) may include the same material as the blue color filter.

Micro lenses ML may be disposed on the color filters CF1 and CF2 in the pixel array area APS. The edges of the micro lenses ML may be in contact with each other and connected. Micro lenses (ML) may form an array. Micro lenses (ML) may also be called 'micro lens array'.

A lens residual layer (MLR) may be disposed on the second optical black pattern (CFB) in the edge region (ER). The lens residual layer (MLR) may include the same material as the micro lenses (ML). An opening 35 exposing the rear conductive pad PAD is formed in the lens residual layer MLR in the pad area PR.

FIGS. 8A to 8H are cross-sectional views sequentially showing a method of manufacturing an image sensor having the cross-section of FIG. 4 according to embodiments of the present invention.

Referring to FIG. 8A, the first sub-chip CH1 is manufactured. To this end, first, an ion implantation process is performed on the first substrate 1 including the pixel array area (APS) and the edge area (ER) to form a photoelectric conversion unit (PD) and a black photoelectric conversion unit (PD'). do. The edge area ER includes a contact area BR1, a via area BR2, and a pad area PR. A device isolation portion (STI) is formed on the front surface 1a of the first substrate 1 to define active regions. The element isolation part (STI) can be formed through the shallow trench isolation process. The device isolation portion (STI) and a portion of the first substrate 1 are etched to form deep trenches 22. Deep trenches 22 may define unit pixels UP in the pixel array area APS and the optical black area OB.

After forming an isolation insulating film conformally on the front surface 1a of the first substrate 1 and filling the deep trenches 22 with a conductive material, an etch-back process is performed to form an isolation insulating film in each of the deep trenches 22. Separate conductive patterns 16 are formed. Additionally, buried insulating patterns 12 may be formed on the separation conductive patterns 16 and the separation insulating film on the front surface 1a may be removed to expose the front surface 1a. As a result, the first and second pixel separation parts DTI1 and DTI2 can be formed simultaneously.

Subsequently, a normal process is performed to form a gate insulating film (Gox), a transfer gate (TG), a floating diffusion region (FD), a first interlayer insulating film (IL1), and a first interlayer insulating film (IL1) on the front surface (1a) of the first substrate (1). 1 Contact plugs 17 and first wires 15 are formed.

Referring to FIG. 8A, a second sub-chip CH2 having the structure described with reference to FIG. 4 is prepared. The first sub chip (CH1) is turned over so that the back side (1b) faces upward. After positioning the first sub-chip (CH1) so that the first interlayer insulating film (IL) is in contact with the second interlayer insulating film (IL2), a thermal compression process is performed to form a layer on the second sub-chip (CH2). The first sub-chip (CH1) can be bonded to.

Referring to FIG. 8B, a grinding process may be performed on the rear surface 1b of the first substrate 1 in the state of FIG. 8A to reduce the thickness of the first substrate 1 to a desired thickness. At this time, the separation conductive patterns 16 of the first and second pixel separation units DTI1 and DTI2 may be exposed. A first insulating film (A1), a titanium oxide film (A2), and a second insulating film (A3) are sequentially stacked on the rear surface (1b) of the first substrate (1). The first insulating layer A1, the titanium oxide layer A2, and the second insulating layer A3 may be formed by Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD), respectively. The first insulating film A1 is preferably made of aluminum oxide and may be formed to have a first thickness T1 as shown in FIG. 7A. The second insulating film A3 is preferably made of silicon oxide and may be formed to have a third thickness T3 as shown in FIG. 7A. As shown in FIG. 7A, the titanium oxide film A2 may be formed to a second thickness T2.

Referring to FIG. 8C, the second insulating layer A3 and the titanium oxide layer A2 are partially sequentially etched to form grooves GR exposing the first insulating layer A1. The positions and planar shapes of the grooves GR may be the same/similar to those described with reference to FIGS. 3 to 7B.

Referring to FIG. 8D, while the grooves GR are formed, a third insulating layer A4 is conformally formed on the second insulating layer A3. The third insulating layer A4 may be formed using Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). The third insulating layer A4 may be formed of hafnium oxide. The third insulating layer A4 may be formed to have the fourth thickness shown in FIG. 7A. The third insulating layer A4 may conformally cover the sidewalls and bottoms of the grooves GR. As a result, the anti-reflection structure AL can be formed.

Referring to FIG. 8E , the anti-reflection structure AL and a predetermined portion of the first substrate 1 are etched in the edge region ER to form the first rear trench 46 and the second rear trench 60. When forming the first rear trench 46, the first pixel isolation portion DTI1 may be partially etched to expose the isolation conductive pattern 16 of the first pixel isolation portion DTI1. The anti-reflection structure (AL), the first substrate (1), the first interlayer insulating film (IL1), and the second interlayer insulating film (IL2) are partially etched in the edge region (ER) to form first and second holes (H1, H2). forms. The first rear trench 46, the second rear trench 60, and the first and second holes H1 and H2 may be formed between the grooves GR.

Referring to FIG. 8F, a conductive film is conformally stacked on the rear surface 1b of the first substrate 1 and etched to form a first conductive pattern 54a, a second conductive pattern 52c, and a rear connection wire 52b. ), the first optical black pattern 52p, and the first and second rear vias (BVS(1) and BVS(2)) are formed. When etching the conductive layer, the third insulating layer A4 may function as an etch stop layer. After filling the first and second holes H1 and H2 with the sacrificial film 70 and covering the unwanted area with a mask pattern (not shown), an electroplating or deposition process is performed to form the first back trench 46 and the second back trench 46. 2 A first metal pattern 54a and a second metal pattern 54b are formed to fill the rear trench 60, respectively. This can form back contacts (BCA) and back conductive pads (PAD).

Referring to FIG. 8G, a light-shielding film and a low-refractive-index film are sequentially stacked and etched on the rear surface 1b of the first substrate 1 to form a light-shielding grid pattern 48a and a low-refractive index grid pattern 50a. . When etching the light blocking layer and the low refractive index layer, the third insulating layer A4 may function as an etch stop layer.

Referring to FIG. 8H, a protective film 56 is conformally formed on the rear surface 1b of the first substrate 1. The color filters CF1 and CF2 and the second optical black pattern (CFB) can be formed through a normal process. The second optical black pattern (CFB) can be formed simultaneously when forming the blue color filter. Additionally, micro lenses (ML) and a lens residual layer (MLR) may be formed on the color filters (CF1, CF2) and the second optical black pattern (CFB). Subsequently, referring to FIG. 4 , an opening 35 may be formed in the pad region PR to expose the rear conductive pad PAD to the remaining lens layer MLR.

Figure 9 is a cross-sectional view taken along line A-A' of Figure 3 according to embodiments of the present invention.

Referring to FIG. 9, in the image sensor 501 according to this example, the rear connection wires 52b of FIG. 4 are not shown. The rear connection wires 52b are not disposed in the grooves GR. The back contacts BCA, the first back vias BVS(1), the back conductive pads PAD, and the second back vias BVS(2) may not be electrically connected to each other but may be insulated. Grooves GR are disposed between the back contacts BCA, the first back vias BVS(1), the back conductive pads PAD, and the second back vias BVS(2). The titanium oxide film A2 is cut by the grooves GR to form back contacts BCA, first back vias BVS(1), back conductive pads PAD, and second back vias ( Leakage current or short circuit between BVS(2)) can be prevented. Other structures may be the same/similar to those described with reference to FIGS. 3 to 7B.

10 is a cross-sectional view of an image sensor according to embodiments of the present invention. FIG. 11A is an enlarged view of portion 'P1' of FIG. 10 according to embodiments of the present invention. FIG. 11B is an enlarged view of portion 'P2' of FIG. 10 according to embodiments of the present invention.

Referring to FIGS. 10, 11a, and 11b, the image sensor 502 according to this example may have a structure in which first and second sub-chips CH1 and CH2 are bonded. The first sub-chip CH1 may be placed on the second sub-chip CH2. The first sub-chip CH1 includes a first substrate 1.

The first pixel separator DTI1 and the second pixel separators DTI2 are each located within a deep trench 22 formed from the rear surface 1b to the front surface 1a of the first substrate 1. The first pixel separator (DTI1) and the second pixel separator (DTI2) may be backside deep trench isolation (BDTI). A portion of the anti-reflection structure AL may be inserted into the deep trench 22 to form the first pixel separator DTI1 and the second pixel separator DTI2. Specifically, the first pixel isolation portion (DTI1) and the second pixel isolation portions (DTI2) each have a first insulating pattern (A1P), a titanium oxide pattern (A2P), and a second insulating pattern that sequentially cover the inner wall of the deep trench 22. Includes pattern (A3P). The second insulating pattern A3P may fill the deep trench 22 . The first insulating pattern A1P may be formed as part of the first insulating layer A1 of the anti-reflection structure AL. The titanium oxide pattern (A2P) may be formed as part of the titanium oxide film (A2) of the anti-reflection structure (AL). The second insulating pattern A2P may be formed as part of the second insulating layer A3 of the anti-reflection structure AL.

The first insulating pattern A1P, the second insulating pattern A3P, and the third insulating layer A4 may each include different materials. Preferably, the first insulating film (A1) and the first insulating pattern (A1P) include aluminum oxide, the second insulating film (A3) and the second insulating pattern (A3P) include silicon oxide, and the third insulating film (A1) includes aluminum oxide. The insulating film A4 includes hafnium oxide.

The first substrate 1 has a first refractive index (n1), the first insulating pattern (A1P) has a second refractive index (n2), and the titanium oxide film (A2) has a third refractive index (n3). , the second insulating pattern A3P may have a fourth refractive index n4. The average value {(n2+n3)/2} of the second refractive index (n2) and the third refractive index (n3) is smaller than the first refractive index (n1) and greater than the fourth refractive index (n4). The first refractive index (n1) is preferably 4.0 to 4.4. The second refractive index (n2) is 2.0 to 3.0. The third refractive index (n3) is 2.2 to 2.8. The fourth refractive index (n4) is 1.0 to 1.9.

As shown in FIG. 11B, the first insulating film A1 has a first thickness T1, the titanium oxide film A2 has a second thickness T2, and the second insulating film A3 has a third thickness T3. , the third insulating layer A4 may have a fourth thickness T4. At this time, the second thickness T2 is greater than the first thickness T1 and the fourth thickness T4, respectively, and is smaller than the third thickness T3.

Preferably, the first thickness (T1) is 10Å to 100Å. The second thickness (T2) is 100Å to 600Å. The third thickness (T3) is 600Å to 900Å. The fourth thickness (T4) is 20Å to 200Å.

Due to the relationship between these refractive indices and/or the relationship between thicknesses, as shown in FIG. 11b, the light L1 incident on the micro lens ML is refracted and passes through the multilayer structure of the anti-reflection structure AL to be transmitted to the photoelectric conversion unit PD. ), you can easily get hired. As a result, it is possible to provide an image sensor 502 with clear image quality by increasing the light reception rate.

Additionally, in the image sensor 502 according to the present invention, the anti-reflection structure (AL) includes a titanium oxide film (A2). The titanium oxide film (A2) overall reduces the reflectivity of all colors of light, and can further reduce the reflectivity of blue light in particular. This can increase the QE (Quantum Efficiency) of the blue pixel.

The first insulating pattern A1P and the first insulating layer A1 may also serve as a negative fixed charge layer. This can improve dark current and white spot.

The image sensor 502 according to this example may not include back surface contacts (BCA). Back vias BVS and back conductive pads PAD may be disposed on the back side 1b of the first substrate 1 in the edge region ER. As shown in FIG. 6 , the second pixel isolation unit DTI2 may surround each of the back vias BVS from a plan view. The back vias BVS may include first back vias BVS(1) and second back vias BVS(2). Other structures may be the same/similar to those described with reference to FIGS. 3 to 7B.

Figure 12 is a cross-sectional view of an image sensor according to embodiments of the present invention.

Referring to FIG. 12, the image sensor 503 according to this example may have a structure in which the first to third sub-chips CH1 to CH3 are sequentially bonded. The first sub-chip CH1 may preferably perform an image sensing function.

The first sub-chip CH1 may include transfer gates TG on the front surface 1a of the first substrate 1 and first interlayer insulating films IL1 covering them. A first device isolation portion (STI1) is disposed on the first substrate 1 to define active regions. The first sub-chip CH1 may exclude the back contacts BCA and the back vias BVS. The first sub-chip CH1 may further include internal connection contacts 17a. At least one of the internal connection contacts 17a penetrates the buried insulating pattern 12 of the first pixel isolation unit DTI1 in the edge region ER to separate some of the first interconnections 15 and the first pixel. The separation conductive pattern 16 of the subdivision DTI1 is connected, and a negative bias voltage can be applied to the separation conduction pattern 16. At least another one of the internal connection contacts 17a penetrates the buried insulating pattern 12 of the second pixel isolation portion DTI2 below the rear conductive pad PAD to connect some of the first interconnections 15 and the second interconnection line 17a. The isolation conductive pattern 16 of the pixel isolation unit DTI2 can be connected. A first conductive pad (CP1) may be disposed in the first interlayer insulating film (IL1) of the lowermost layer. The first conductive pad CP1 may include copper.

The second sub-chip CH2 includes a second substrate SB2, select gates SEL, source follower gates SF, and reset gates (not shown) disposed thereon, and a second interlayer insulating film covering them ( IL2) may be included. A second device isolation portion (STI2) is disposed on the second substrate (SB2) to define active regions. Second contacts 215 and second wires 217 may be disposed within the second interlayer insulating films IL2. A second conductive pad CP2 may be disposed within the second interlayer insulating film IL2 on the uppermost layer. The second conductive pad CP2 may include copper. The second conductive pad CP2 may be in contact with the first conductive pad CP1. The source follower gates SF may each be connected to the floating diffusion regions FD of the first sub-chip CH1.

The third sub-chip CH3 may include a third substrate SB3, peripheral transistors PTR disposed thereon, and third interlayer insulating films IL3 covering them. A third device isolation portion (STI3) is disposed on the third substrate (SB3) to define active regions. Third contacts 317 and third wires 315 may be disposed in the third interlayer insulating films IL3. The uppermost third interlayer insulating film IL3 is in contact with the second substrate SB2. The through electrode TSV penetrates the second interlayer insulating layer IL2, the second device isolation portion STI2, the second substrate SB2, and the third interlayer insulating layer IL3 to connect one of the second interconnections 217 and the third interlayer insulating layer IL3. One of the third wires 315 may be connected. The sidewall of the through electrode (TSV) may be surrounded by a via insulating layer (TVL). The third sub-chip (CH3) includes circuits for driving the first and/or second sub-chips (CH1, CH2) or storing electrical signals generated from the first and/or second sub-chips (CH1, CH2). It can be included.

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The embodiments of FIGS. 3 to 12 can be combined with each other.

Claims (20)

a first substrate having a first side and an opposing second side, the first substrate including a pixel array area and an edge area;
an anti-reflection structure disposed on the second surface;
a pixel separator disposed in the first substrate to separate pixels; and
Including a micro lens array disposed on the anti-reflection structure,
The anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film, which are sequentially stacked,
The first insulating film, the second insulating film, and the third insulating film each include different materials,
The image sensor wherein the third insulating layer penetrates the second insulating layer and the titanium oxide layer in the edge area and contacts the first insulating layer.
According to claim 1,
The first insulating film includes aluminum oxide,
The second insulating film includes silicon oxide,
The third insulating film is an image sensor comprising hafnium oxide.
According to claim 1,
The first substrate has a first refractive index,
The first insulating film has a second refractive index,
The titanium oxide film has a third refractive index,
The second insulating film has a fourth refractive index,
An image sensor wherein an average value of the second refractive index and the third refractive index is smaller than the first refractive index and larger than the fourth refractive index.
According to claim 1,
Further comprising a first contact and a second contact disposed on a second surface of the first substrate in the edge region,
The pixel separator extends to the edge, and the first contact penetrates a portion of the first substrate and contacts the pixel separator,
The image sensor wherein the third insulating layer penetrates the second insulating layer and the titanium oxide layer between the first contact and the second contact and contacts the first insulating layer.
According to clause 4,
The pixel separation unit further includes a separation conductive pattern and a separation insulating pattern interposed between the separation conductive pattern and the first substrate,
The first contact is an image sensor in contact with the separation conductive pattern.
According to clause 4,
a first interlayer insulating film disposed on the first surface of the first substrate;
a first wiring layer disposed within the first interlayer insulating film;
a second interlayer insulating film disposed below the first interlayer insulating film;
a second wiring layer disposed within the second interlayer insulating film; and
It further includes a second substrate disposed under the second interlayer insulating film,
The image sensor wherein the second contact penetrates a portion of the first substrate, the first interlayer insulating film, and the second interlayer insulating film and contacts the second wiring layer.
According to clause 4,
A groove is formed in the titanium oxide film and the second insulating film on the edge area,
The first insulating film is exposed at the bottom of the groove,
The third insulating film conformally covers the bottom and side surfaces of the groove,
The image sensor further includes a conductive line connecting the first contact and the second contact, and the conductive line covers a sidewall and a bottom surface of the groove.
According to clause 4,
A groove is formed in the titanium oxide film and the second insulating film on the edge area,
The first insulating film is exposed at the bottom of the groove,
The third insulating film conformally covers the bottom and side surfaces of the groove,
The groove is an image sensor planarly surrounding the second contact.
According to clause 8,
Further comprising a substrate separator spaced apart from the second contact in the edge area and surrounding the second contact between the second contact and the groove,
The image sensor wherein a first gap between the second contact and the substrate separator is greater than a second gap between the substrate separator and the groove.
According to claim 1,
A groove is formed in the titanium oxide film and the second insulating film on the edge area,
The first insulating film is exposed at the bottom of the groove,
The third insulating film conformally covers the bottom and side surfaces of the groove,
The image sensor is:
a low refractive index grid pattern disposed on the anti-reflection structure of the first substrate in the pixel array area; and
An image sensor further comprising a low refractive index residual pattern filling the groove.
According to claim 1,
a first interlayer insulating film disposed on the first surface of the first substrate;
a first wiring layer disposed within the first interlayer insulating film;
a second interlayer insulating film disposed below the first interlayer insulating film;
a second wiring layer disposed within the second interlayer insulating film; and
a second substrate disposed under the second interlayer insulating film;
a conductive pad disposed on a second side of the first substrate in the edge area; and
Further comprising a via that passes through a portion of the first substrate, the first interlayer insulating film, and the second interlayer insulating film in the edge area and contacts the second wiring layer,
The image sensor wherein the third insulating layer penetrates the second insulating layer and the titanium oxide layer between the conductive pad and the via in the edge area and contacts the first insulating layer.
According to claim 1,
The pixel separator is disposed in a deep trench formed from the second side toward the first side,
An image sensor wherein a portion of the anti-reflection structure is inserted into the deep trench to form the pixel separation unit.
According to claim 11,
The first insulating film has a first thickness,
The titanium oxide film has a second thickness,
The second insulating film has a third thickness,
The third insulating film has a fourth thickness,
The second thickness is greater than the first thickness and the fourth thickness, and is smaller than the third thickness.
According to claim 1,
A groove is formed in the titanium oxide film and the second insulating film on the edge area,
The first insulating film is exposed at the bottom of the groove,
The third insulating film conformally covers the bottom and side surfaces of the groove,
The groove is an image sensor that two-dimensionally surrounds the pixel array area.
a first substrate having a first side and an opposing second side, the first substrate including a pixel array area and an edge area;
an anti-reflection structure disposed on the second surface;
a pixel separator disposed on the first substrate to separate pixels;
a color filter disposed on the anti-reflection structure;
a micro lens array disposed on the color filter;
a first interlayer insulating film disposed on the first surface of the first substrate;
a first wiring layer disposed within the first interlayer insulating film;
a second interlayer insulating film disposed below the first interlayer insulating film;
a second wiring layer disposed within the second interlayer insulating film; and
a second substrate disposed under the second interlayer insulating film;
a first contact disposed on a second surface of the first substrate in the edge area; and
A second contact passes through a portion of the first substrate, the first interlayer insulating film, and the second interlayer insulating film in the edge area and contacts the second wiring layer,
The anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film, which are sequentially stacked,
The first insulating film, the second insulating film, and the third insulating film each include different materials,
The image sensor wherein the third insulating layer penetrates the second insulating layer and the titanium oxide layer between the first contact and the second contact and contacts the first insulating layer.
According to claim 15,
The first substrate has a first refractive index,
The first insulating film has a second refractive index,
The titanium oxide film has a third refractive index,
The second insulating film has a fourth refractive index,
An image sensor wherein an average value of the second refractive index and the third refractive index is smaller than the first refractive index and larger than the fourth refractive index.
According to claim 15,
The pixel separation unit further includes a separation conductive pattern and a separation insulating pattern interposed between the separation conductive pattern and the first substrate,
The first contact is an image sensor in contact with the separation conductive pattern.
a first substrate having a first side and an opposing second side, the first substrate including a pixel array area and an edge area;
an anti-reflection structure disposed on the second surface;
a pixel separator disposed on the first substrate to separate pixels; and
Including a micro lens array disposed on the anti-reflection structure,
The anti-reflection structure includes a first insulating film, a titanium oxide film, a second insulating film, and a third insulating film, which are sequentially stacked,
The first insulating film, the second insulating film, and the third insulating film each include different materials,
A groove is formed in the titanium oxide film and the second insulating film on the edge area,
The first insulating film is exposed at the bottom of the groove,
The third insulating film conformally covers the bottom and side surfaces of the groove,
The groove is an image sensor that two-dimensionally surrounds the pixel array area.
According to clause 18,
The first insulating film has a first thickness,
The titanium oxide film has a second thickness,
The second insulating film has a third thickness,
The third insulating film has a fourth thickness,
The second thickness is greater than the first thickness and the fourth thickness, and is smaller than the third thickness.
According to clause 18,
a first wiring layer disposed within the first interlayer insulating film;
a second interlayer insulating film disposed below the first interlayer insulating film;
a second wiring layer disposed within the second interlayer insulating film; and
a second substrate disposed under the second interlayer insulating film;
a first contact disposed on a second surface of the first substrate in the edge area; and
It further includes a second contact that penetrates a portion of the first substrate, the first interlayer insulating film, and the second interlayer insulating film in the edge area and contacts the second wiring layer,
The pixel separation unit further includes a separation conductive pattern and a separation insulating pattern interposed between the separation conductive pattern and the first substrate,
The groove is disposed between the first contact and the second contact,
The first contact is an image sensor in contact with the separation conductive pattern.

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