KR20230034171A - Method of ultra thinning of wafer - Google Patents

Abstract

Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided, and a buried etch stop layer is formed on the silicon wafer. The wafer is then processed into devices through front-end processing. After front-end processing, the wafer undergoes hybrid bonding, followed by thinning of the wafer. To thin the wafer, a silicon substrate layer, having an initial first thickness, is ground to a second thickness, where the second thickness is thinner than the first thickness. After grinding, the silicon wafer undergoes chemical mechanical planarization (CMP), followed by etching and CMP buffing, reducing the thickness of the silicon to a third thickness, which is thinner than the second thickness.

Description

Wafer ultra-thinning method {METHOD OF ULTRA THINNING OF WAFER}

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments of the present disclosure relate to power rail architecture, 3D packaging, and methods of manufacturing semiconductor devices.

[0002] The semiconductor processing industry continues to strive for greater production yields while increasing the uniformity of layers deposited on substrates with greater surface areas. These same factors combined with the new materials also provide a higher degree of integration of circuits per unit area of the substrate. As circuit integration increases, the need for greater uniformity in layer thickness and process control increases. As a result, various techniques have been developed for depositing layers on substrates in a cost effective manner while maintaining control over the properties of the layer.

[0003] Semiconductor devices generally deposit insulating or dielectric layers, conductive layers, and semiconductor material layers sequentially over a semiconductor substrate, and pattern the various material layers using lithography to form circuit components thereon. and by forming elements. Conductive layers are used in transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors ), inductors, resistors, and the like.

[0004] Transistors are a key component of most integrated circuits. Since a transistor's drive current, and thus its speed, is proportional to its gate width, faster transistors generally require larger gate widths. Thus, there is a trade-off between transistor size and speed, and “fin” field effect transistors (finFETs) are used to address the conflicting goals of transistors with maximum drive current and minimum size. this was developed FinFETs are characterized by a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor, and is currently being applied to many integrated circuits. However, finFETs have their inherent disadvantages.

[0005] As feature sizes of transistor devices continue to shrink to achieve greater circuit density and higher performance, to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage A need exists to improve transistor device structures. Examples of transistor device structures include a planar structure, a fin field effect transistor (FinFET) structure, and a horizontal gate all around (hGAA) structure. The hGAA device structure includes several lattice matching channels suspended in a stacked configuration and connected by source/drain regions. The hGAA structure provides excellent static control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0006] Connecting the semiconductors to the power rail is usually done in front of the cell, which requires significant cell area. Accordingly, a need exists for semiconductor devices that connect to power rails using less cell area.

[0007] One or more embodiments of the present disclosure relate to methods of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device includes: forming an etch stop layer on a top surface of a substrate, wherein the substrate has a first thickness; forming an epitaxial layer on the top surface of the etch stop layer; forming a wafer device on the top surface of the epitaxial layer; bonding the wafer device to a bonding wafer; grinding the substrate to form a substrate having a second thickness less than the first thickness; planarizing the substrate to form a substrate having a third thickness less than the second thickness; removing the etch stop layer to expose source/drain regions on the wafer device; and forming contacts electrically connected to the source/drain regions.

[0008] Additional embodiments of the present disclosure relate to methods of forming a semiconductor device. In one or more embodiments, a method of forming a semiconductor device includes: forming an etch stop layer on a top surface of a substrate, wherein the substrate has a first thickness; forming an epitaxial layer on the top surface of the etch stop layer; forming a wafer device on the top surface of the epitaxial layer; bonding the wafer device to a bonding dummy wafer or a Cu wafer by hybrid bonding; grinding the substrate to form a substrate having a second thickness less than the first thickness; depositing a mask layer on the bottom surface of the etch stop layer; forming at least one via opening in the mask layer; selectively removing the etch stop layer; and removing the mask layer to expose the substrate, wherein the substrate has a fourth thickness less than the first thickness.

[0009] In such a way that the above-listed features of the present disclosure may be understood in detail, a more detailed description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are provided in the appended illustrated in the drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be regarded as limiting the scope of the present disclosure, as it allows for other equally valid embodiments. Because you can.
1A is a process flow diagram of a method in accordance with one or more embodiments.
FIG. 1B is a continuation of the process flow diagram of FIG. 1A showing a method in accordance with one or more embodiments.
2A illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2B illustrates a cross-sectional view of a device according to one or more embodiments.
2C illustrates a cross-sectional view of a device according to one or more embodiments.
2D illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2E illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2F illustrates a cross-sectional view of a device according to one or more embodiments.
2G illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2H illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2I illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0021] FIG. 2J illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0022] FIG. 2K illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0023] FIG. 2L illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2M illustrates a cross-sectional view of a device according to one or more embodiments.
2N illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2O illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2P illustrates a cross-sectional view of a device according to one or more embodiments.
2Q illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2R illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2S illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0031] FIG. 2T illustrates a cross-sectional view of a device in accordance with one or more embodiments.
2U illustrates a cross-sectional view of a device in accordance with one or more embodiments.
3 illustrates a process flow diagram of a method according to one or more embodiments.
4A illustrates a cross-sectional view of a device in accordance with one or more embodiments.
4B illustrates a cross-sectional view of a device according to one or more embodiments.
[0036] FIG. 4C illustrates a cross-sectional view of a device in accordance with one or more embodiments.
4D illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0038] FIG. 4E illustrates a cross-sectional view of a device in accordance with one or more embodiments.
5A illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0040] FIG. 5B illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0041] FIG. 5C illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0042] FIG. 5D illustrates a cross-sectional view of a device in accordance with one or more embodiments.
6 illustrates a process flow diagram of a method according to one or more embodiments.
7A illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0045] FIG. 7B illustrates a cross-sectional view of a device according to one or more embodiments.
[0046] FIG. 7C illustrates a cross-sectional view of a device in accordance with one or more embodiments.
[0047] FIG. 7D illustrates a cross-sectional view of a device in accordance with one or more embodiments.
8 illustrates a cluster tool in accordance with one or more embodiments.
[0049] For ease of understanding, like reference numbers have been used where possible to designate like elements that are common to the drawings. The drawings are not drawn to scale and may have been simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

[0050] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

[0051] As used in this specification and the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process operates. Further, it will be understood by those skilled in the art that reference to a substrate may also refer to only a portion of a substrate, unless the context clearly dictates otherwise. Additionally, reference to deposition on a substrate may refer to both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0052] As used herein, “substrate” refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, the substrate surface on which processing may be performed may be silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium, depending on the application. materials such as arsenic, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, without limitation, semiconductor wafers. Substrates can be polished, etched, reduced, oxidized, hydroxylated (or otherwise created or grafted with target chemical moieties to impart chemical functionality), annealed and/or baked ( may be exposed to a pretreatment process for baking. In the present disclosure, in addition to directly processing the film on the surface of the substrate itself, any of the disclosed film processing steps may also be performed on an underlayer formed on the substrate as disclosed in more detail below; The term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film/layer or partial film/layer is deposited on a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface. What a given substrate surface contains will depend not only on what films are to be deposited, but also on the particular chemistry used.

[0053] As used in this specification and the appended claims, the terms "precursor", "reactant", "reactive gas" and the like are interchangeable to refer to any gaseous species capable of reacting with the substrate surface. possibly used

[0054] Transistors are circuit components or elements that are often formed on semiconductor devices. Depending on the circuit design, transistors are formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise a doped region of the substrate and exhibit a doping profile suitable for the particular application. The gate is positioned over the channel region and includes a gate dielectric interposed between the gate electrode and the channel region of the substrate.

[0055] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field of the device created by the voltage difference between the body and gate of the device. The three terminals of the FET are the source (S) through which carriers enter the channel; Drain (D) where carriers leave the channel; and gate (G), which terminal modulates the channel conductance. In general, the current entering the channel from the source (S) is designated as I _S , and the current entering the channel from the drain (D) is designated as I _D . The drain-to-source voltage is specified as V _DS . By applying a voltage to the gate G, the current entering the channel from the drain (ie, I _D ) can be controlled.

[0056] A metal oxide semiconductor field effect transistor (MOSFET) is one type of field effect transistor (FET). It has an insulated gate, and the voltage of that insulated gate determines the conductivity of the device. This ability to change conductivity by the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on modulation of the charge concentration by a metal oxide semiconductor (MOS) capacitance between a body electrode and a gate electrode positioned over the body and insulated from all other device regions by a gate dielectric layer. Compared to MOS capacitors, MOSFETs contain two additional terminals (source and drain), each connected to individual heavily doped regions separated by a body region. These regions can be p or n type, but they are both of the same type, opposite the body region. (Unlike the body) the source and drain are highly doped as indicated by a "+" sign after the doping type.

[0057] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of the charge carriers flowing through the channel (electrons for n-channel, holes for p-channel); Similarly, the drain is where the charge carriers leave the channel.

[0058] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gate is disposed on two or three sides of the channel to form a double or triple gate structure. . FinFET devices have been given the generic name FinFETs because the channel region forms a “fin” on the substrate. FinFET devices have fast switching times and high current density.

[0059] As used herein, the term "gate-all-around" (GAA) is used to refer to an electronic device, eg, a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor includes nanowires or nano-slabs or nano-sheets, bar-shaped channels, or other suitable channel configurations known to those skilled in the art. can do. In one or more embodiments, the channel region of the GAA device has multiple vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0060] As used herein, the term "nanowire" refers to a nanostructure having a diameter on the order of nanometers (10 ⁻⁹ meters). Nanowires may also be defined as having a length to width ratio greater than 1000. Alternatively, nanowires may be defined as structures having a thickness or diameter limited to tens of nanometers or less and an unrestricted length. Nanowires are used in transistors and some laser applications and, in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (eg, DRAM) and non-volatile (eg, NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure having a thickness on the scale ranging from about 0.1 nm to about 1000 nm.

[0061] Embodiments of the present disclosure are described through figures that illustrate processes and devices (eg, transistors) for forming transistors in accordance with one or more embodiments of the present disclosure. The depicted processes are merely illustrative of possible uses for the disclosed processes, and one skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0062] One or more embodiments of the present disclosure are described with reference to the drawings. In the method of one or more embodiments, transistors, eg, gate-all-around transistors, are fabricated using standard process flows. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, for example epitaxial silicon, is deposited. The wafer is then processed into devices and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, for example to copper or oxide, and then the wafer is advantageously thinned. Thinning the wafer provides the desired flatness and bonding to enable the backside power rail. To thin the wafer, a silicon substrate layer having a starting first thickness is ground to a second thickness, the second thickness being smaller than the first thickness. After grinding, in some embodiments, the silicon wafer is subjected to chemical mechanical planarization (CMP) followed by etching and CMP buffing to reduce the thickness of the silicon to a third thickness, the third thickness is smaller than the second thickness. In one or more embodiments, the etch stops at the buried etch stop layer. The contacts are then pre-filled with metal and metallization is carried out.

[0063] In alternative embodiments, transistors, eg, gate-all-around transistors, are fabricated using standard process flows. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, for example epitaxial silicon, is deposited. The wafer is then processed into devices and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, for example to copper or oxide, and then the wafer is advantageously thinned. Thinning the wafer provides the desired flatness and bonding to enable the backside power rail. To thin the wafer, a silicon substrate layer having a starting first thickness is ground to a second thickness, which second thickness is smaller than the first thickness. After grinding, a large mask is deposited and vias are formed in the mask. The wafer is then etched through the vias to the buried etch stop layer, then the etch stop layer is selectively removed, and liftoff occurs.

[0064] In the method of one or more embodiments, transistors, eg, gate-all-around transistors, are fabricated using standard process flows. After the source/drain cavity is recessed, the dimensions of the source/drain cavity are enlarged and a sacrificial fill material is deposited. Fabrication proceeds with formation of internal spacers, source/drain epitaxy, formation of interlayer dielectrics, formation of replacement gates, formation of CT and CG, and formation of front metal lines. The substrate is then flipped and planarized. An interlevel dielectric is deposited on the backside, backside power rail vias are patterned, and the interlevel dielectric is etched. A damascene trench is formed and the sacrificial filler is removed to form an opening. Metal is deposited in the opening, and then backside metal lines are formed. In one or more embodiments, the sacrificial fill material is advantageously selective so that, upon etching, self-aligned trenches and/or vias are formed, thereby preventing misalignment.

[0065] In the method of one or more embodiments, transistors, eg, gate-all-around transistors, are fabricated using standard process flows. Deep vias are etched with a separate mask, or alternatively they are etched with a regular contact or via mask. After etching the regular vias, a mask is placed and then the power rail vias are etched to a depth below the device to facilitate back side connections. Both standard and deep vias/contacts are simultaneously filled with titanium nitride/tungsten (TiN/W) or titanium nitride/ruthenium (TiN/Ru) or molybdenum (Mo) contact filler and then planarized. The wafer may optionally be thinned. On the back side, vias are etched and connected to deep vias. Then metallization takes place.

[0066] 1A illustrates a process flow diagram for a method 6 for forming a semiconductor device in accordance with some embodiments of the present disclosure. 1B is a continuation of the process flow diagram of FIG. 1A showing a method 6 in accordance with one or more embodiments. 2A-2U show fabrication stages of semiconductor structures in accordance with some embodiments of the present disclosure. Method 6 is described below with respect to FIGS. 2A-2U. 2A-2U are cross-sectional views of an electronic device (eg, GAA) in accordance with one or more embodiments. Method 6 may be part of a multi-step fabrication process of a semiconductor device. Accordingly, method 6 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may be used in process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other process chambers used in the fabrication of semiconductor devices. A suitable chamber may be included.

[0067] Figures 2a-2u are fabrication steps of operations 8-54 of Figures 1a and 1b. Referring to FIG. 1A , a method 6 of forming a device 100 begins at operation 8 by providing a substrate 102 . In some embodiments, substrate 102 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" means a substrate entirely composed of a semiconductor material. The bulk semiconductor substrate may include any suitable semiconductor material and/or combinations of semiconductor materials for forming the semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconducting materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 is a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), another semiconductor material. , or any combination thereof. In one or more embodiments, substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While several examples of materials from which the substrate may be formed are described herein, passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits) , amplifiers, optoelectronic devices, or any other electronic devices) that can serve as a foundation upon which to be built are within the spirit and scope of the present disclosure.

[0068] In some embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to semiconductors produced by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of a well (or hole). Unlike n-type semiconductors, p-type semiconductors have a greater hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0069] Referring to FIG. 1A , in some illustrative embodiments, in operation 10, an etch stop layer may be formed on a top surface of a substrate. The etch stop layer may include any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer includes silicon germanium (SiGe). In one or more embodiments, the etch stop layer has a high germanium (Ge) content. In one or more embodiments, the amount of germanium ranges from 30% to 50%, including from 35% to 45%. Without intending to be bound by theory, it is believed that a germanium content in the range of 30% to 50% increases the selectivity of the etch stop layer and minimizes stress defects. In one or more embodiments, the etch stop layer has a thickness ranging from 5 nm to 30 nm. The etch stop layer can serve as an etch stop for planarization (eg CMP), dry or wet etching during back side processing.

[0070] In one or more illustrative embodiments, in operation 12, an epitaxial layer, eg, epitaxial silicon, may be deposited on the etch stop layer. The epitaxial layer may range in thickness from 20 nm to 100 nm.

[0071] Referring to FIGS. 1A and 2A , in one or more embodiments, in operation 14 , at least one superlattice structure 101 is placed atop the top surface of the substrate 102 or an etch stop layer and formed on the top surface of the epitaxial layer. The superlattice structure 101 includes a plurality of semiconductor material layers 106 and a corresponding plurality of horizontal channel layers 104 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked groups of layers include a silicon (Si) and a silicon germanium (SiGe) group. In some embodiments, the plurality of semiconductor material layers 106 includes silicon germanium (SiGe) and the plurality of horizontal channel layers 104 includes silicon (Si). In other embodiments, the plurality of horizontal channel layers 104 includes silicon germanium (SiGe) and the plurality of semiconductor material layers 106 includes silicon (Si).

[0072] In some embodiments, plurality of semiconductor material layers 106 and corresponding plurality of horizontal channel layers 104 may include any number of lattice matching material pairs suitable for forming superlattice structure 204 . . In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 include from about 2 to about 50 pairs of lattice matching materials.

[0073] In one or more embodiments, the thickness of the plurality of semiconductor material layers 106 and the plurality of horizontal channel layers 104 ranges from about 2 nm to about 50 nm, from about 3 nm to about 20 nm, or from about 2 nm to about 15 nm.

[0001] Referring to FIGS. 1A and 2B , in one or more embodiments, in operation 16 , superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105 . Patterning may be performed by any suitable means known to those skilled in the art. As used in this regard, the term “aperture” means any intentional surface irregularity. Suitable examples of openings include (but are not limited to) trenches having a top, two sidewalls and a bottom. The apertures may have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is greater than about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1; same.

[0074] Referring to FIGS. 1A and 2C , in operation 18, shallow trench isolation (STI) 110 is formed. As used herein, the term “shallow trench isolation (STI)” refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, the STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill the trench or opening 108 and removing the excess dielectric using a technique such as chemical mechanical planarization.

[0075] Referring to FIGS. 1A and 2D , in some embodiments, a replacement gate structure 113 (eg, a dummy gate structure) is formed over and adjacent to the superlattice structure 101 . Dummy gate structure 113 defines a channel region of the transistor device. Dummy gate structure 113 may be formed using any suitable conventional deposition and patterning process known in the art.

[0076] In one or more embodiments, the dummy gate structure includes one or more of a gate 114 and a poly-silicon layer 112 . In one or more embodiments, the dummy gate structure may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

[0077] Referring to FIGS. 1A and 2E , in some embodiments, in operation 22 , sidewall spacers 116 are formed along outer sidewalls of dummy gate structure 113a on superlattice 101 . Sidewall spacers 116 may include any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, for example. In some embodiments, the sidewall spacers use any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, or isotropic deposition. is formed by

[0078] Referring to FIGS. 1A and 2F , in operation 24 , source/drain trenches 118 are formed adjacent to (ie, on either side of) the superlattice structure 101 , in one or more embodiments.

[0079] Referring to FIGS. 1A and 2G , in operation 26 , in one or more embodiments, source/drain trenches 118 are deepened and extended to form cavities 119 underneath superlattice structure 101 . form The cavities 119 may have any suitable depth and width. In one or more embodiments, cavity 119 extends through shallow trench isolation 110 into substrate 102 . In one or more embodiments, the cavity 119 etch and dummy fill extends below the shallow trench isolation 110 and up to a silicon germanium (SiGe) etch stop layer, thus providing self-aligned contacts without touching the device. make it possible to hear

[0080] Cavity 119 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, a hard mask 117 is deposited to block the non V _ss /V _dd source/drain. In one or more embodiments, hard mask 117 may include any suitable material known to those skilled in the art. In some embodiments, hard mask 117 is a resist. Once the hard mask 117 is formed, the cavity 119 is formed by etching.

[0081] The etch process of operation 26 may include any suitable etch process that is selective to the source/drain trenches 118 . In some embodiments, the etching process of operation 26 includes one or more of a wet etching process or a dry etching process. The etching process may be a directional etch.

[0082] In some embodiments, the dry etch process may include a conventional plasma etch, or a remote plasma assisted dry etch process, such as the SiCoNi ^™ etch process available from Applied Materials, Inc. of Santa Clara, Calif. . In the SiCoNi ^™ etch process, the device is exposed to H ₂ , NF ₃ and/or NH ₃ plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, a device can undergo simultaneous exposure to H ₂ , NF ₃ , and NH ₃ plasma. The SiCoNi ^TM etch process can be performed in a SiCoNi ^TM Preclean chamber that can be integrated into one of a variety of multiple processing platforms including the Centura ^® , Dual ACP, Producer ^® GT and Endura ^® platforms available from Applied ^Materials ® . The wet etch process may include a hydrogen fluoride (HF) acid last process, a so-called “HF last” process in which an HF etch of the surface is performed to keep the surface in a hydrogen-terminated state. Alternatively, any other liquid based pre-epitaxial pre-clean process may be used. In some embodiments, the process includes a sublimation etch for native oxide removal. The etching process may be plasma or thermal based. The plasma processes may be any suitable plasma (eg, conductive coupled plasma, inductively coupled plasma, microwave plasma).

[0083] Referring to FIGS. 1A and 2H , in operation 28 , sacrificial material 120 is deposited in cavity 119 . The sacrificial material may include any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 120 includes silicon germanium (SiGe). In one or more embodiments, the sacrificial material 120 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium ranges from 30% to 50%, including from 35% to 45%. Without intending to be bound by theory, it is believed that the selectivity of the sacrificial material increases and stress defects are minimized when the germanium content is in the range of 30% to 50%.

[0084] In one or more embodiments, the sacrificial material 120 is doped with a dopant for lower contact resistance. In some embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In certain embodiments, the sacrificial material 120 has a germanium content in the range of 30% to 50% and with a dopant selected from one or more of boron (B), gallium (Ga), phosphorus (P), and arsenic (As). It is doped silicon germanium.

[0085] Referring to FIGS. 1A and 2I , in operation 30 , an inner spacer layer 121 is formed on each of the horizontal channel layers 104 . The inner spacer layer 121 may include any suitable material known to those skilled in the art. In one or more embodiments, inner spacer layer 121 includes a nitride material. In certain embodiments, inner spacer layer 121 includes silicon nitride.

[0086] Referring to FIGS. 2J and 1A , in operation 32 , in some embodiments, embedded source/drain regions 122 are formed in source/drain trench 118 . In some embodiments, source region 122 is formed adjacent to a first end of superlattice structure 101 and drain region 122 is formed adjacent to an opposite second end of superlattice structure 101 . do. In some embodiments, source region and/or drain region 122 may be made of (but not limited to) silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorous (SiP), silicon arsenic (SiAs), or the like. not) is formed of any suitable semiconductor material. In some embodiments, source/drain regions 122 may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source/drain regions 122 are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0087] In some embodiments, referring to FIGS. 1A and 2K , in operation 34 , inter-layer dielectric (ILD) layer 124 is applied to source/drain regions 122 , a dummy gate structure ( 113), and sidewall spacers 116 are blanket deposited over the substrate 102. ILD layer 124 may be deposited using conventional chemical vapor deposition methods (eg, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition). In one or more embodiments, the ILD layer 124 may be any material such as, but not limited to, undoped silicon oxide, doped silicon oxide (eg, BPSG, PSG), silicon nitride, and silicon oxynitride. of suitable dielectric materials. In one or more embodiments, ILD layer 124 is then polished again using a conventional chemical mechanical planarization method to expose the top of dummy gate structure 113 . In some embodiments, the ILD layer 124 is polished to expose the top of the dummy gate structure 113 and the top of the sidewall spacers 116 .

[0088] The dummy gate structure 101 may be removed to expose the channel region 108 of the superlattice structure 101 . ILD layer 124 protects source/drain regions 122 while removing dummy gate structure 113 . Dummy gate structure 113 may be removed using any conventional etching method, such as plasma dry etching or wet etching. In some embodiments, dummy gate structure 113 includes polysilicon, and dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 includes polysilicon and the superlattice structure 101 includes alternating layers of silicon (Si) and silicon germanium (SiGe).

[0089] Referring to FIGS. 1B and 2L, at operation 38, formation of the semiconductor device, eg, GAA, continues according to conventional procedures with nanosheet release and replacement metal gate formation. Specifically, in one or more illustrative embodiments, the plurality of semiconductor material layers 106 are selectively etched between the plurality of horizontal channel layers 104 in the superlattice structure 101 . For example, when the superlattice structure 101 is composed of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The plurality of semiconductor material layers 106, for example silicon germanium (SiGe), may be removed using any well-known etchant that is selective to the plurality of horizontal channel layers 104, wherein the etchant Etches the plurality of semiconductor material layers 106 at a much higher rate than the horizontal channel layers 104 . In some embodiments, a selective dry etch or wet etch process may be used. In some embodiments, when the plurality of horizontal channel layers 104 is silicon (Si) and the plurality of semiconductor material layers 106 is silicon germanium (SiGe), the layers of silicon germanium are carboxylic acid/nitric acid/HF aqueous solution. and wet etchants such as, but not limited to, citric acid/nitric acid/HF aqueous solution. Removal of the plurality of semiconductor material layers 106 leaves voids between the plurality of horizontal channel layers 104 . Gaps between the plurality of horizontal channel layers 104 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 104 form a vertical array of channel nanowires coupled to the source/drain regions 122 . The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single column of channel nanowires.

[0090] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high-k dielectric of some embodiments includes hafnium oxide. In some embodiments, a conductive material such as titanium nitride (TiN), tungsten (W), cobalt (Co), aluminum (Al), or the like is deposited on the high-k dielectric to form the replacement metal gate 128 . The conductive material may be formed using any suitable deposition process such as, but not limited to, atomic layer deposition (ALD) to ensure formation of a layer having a uniform thickness around each of the plurality of channel layers.

[0091] Referring to FIGS. 1B and 2M, in operation 38, a contact to the transistor (CT) 132 and a contact to the gate (CG) 134 are formed.

[0092] Referring to FIGS. 1B and 2N , in operation 40 , a metal M0 line 142 is formed and electrically connected to via V1 144 . This is similar to traditional processing, only the M0 lines do not have power rails, thus creating enough space for the signal lines.

[0093] Referring to FIG. 2O , in operation 42 , device 100 is rotated or flipped 180 degrees so that substrate 102 is now at the top of the example. Additionally, in one or more embodiments, substrate 102 is planarized. Planarization can be any suitable planarization process known to those skilled in the art including, but not limited to, chemical mechanical planarization (CMP). In one or more embodiments, prior to rotation, the front surface is bonded to the copper (Cu) metallization in the last layer with hybrid bonding (oxide to oxide and Cu to Cu) or electrostatic dummy wafer bonding.

[0094] Referring to Figures 1B and 2P, in operation 44, an interlayer dielectric 146/148 is deposited on the backside. Interlayer dielectric materials 146/148 may be deposited by any suitable means known to those skilled in the art. Interlayer dielectric materials 146/148 may include any suitable materials known to those skilled in the art. In one or more embodiments, interlayer dielectric materials 146/148 include one or more of silicon nitride (SiN), carbide, or boron carbide to allow for high aspect ratio etching and metallization.

[0095] As illustrated in FIG. 2Q , in operation 46 , in one or more embodiments, a back side power rail via 152 is formed. Via 152 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, via 152 may be formed by patterning and etching interlayer dielectric materials 146/148.

[0096] Referring to FIGS. 1B and 2R , in operation 48 , damascene trench 154 is formed by extending via 152 to contacts 120 and 122 . The expansion of via 152 to form trench 154 increases the size of the opening by at least a factor of two, allowing self-alignment. In one or more embodiments, via 152 has a starting size of about 16 nm by about 26 nm and is widened to form a trench 154 having a size of about 90 nm by about 74 nm.

[0097] Damascene trench 154 is stopped at contacts 120 and 122 . Damascene trench 154 may have any suitable aspect ratio known to those skilled in the art. In some embodiments, the aspect ratio is greater than about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1; same. In one or more embodiments, the critical dimensions of damascene trench 154 are about 16 nm by about 26 nm, or about 10 nm by about 30 nm, or about 15 nm by about 30 nm. In one or more embodiments, the height of the backside vias depends on the thickness of the original epitaxial layer deposited over the etch stop layer.

[0098] In operation 50, the sacrificial layer 120 is selectively removed to form an opening 156 over the source/drain 122, as illustrated in FIG. 2S. In one or more embodiments, when the sacrificial layer 120 is doped with one or more of Ga, B, and P, a portion of the sacrificial layer 120 may be partially removed while remaining. Partial removal of the sacrificial layer 120 allows formation of low resistivity contacts to the remaining sacrificial layer 120 (eg, SiGe).

[0099] In operation 52, a metal filler 156 is deposited in the opening 156 formed by the removal of the sacrificial layer 120, as illustrated in FIG. 2T. Metal filler 156 may include any suitable material known to those skilled in the art. In one or more embodiments, the metal filler 156 is titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), It is selected from one or more of copper (Cu), ruthenium (Ru), and the like.

[00100] Referring to FIGS. 1B and 2U, in operation 54, a back surface metal line (MO) 160 is formed. Without intending to be bound by theory, it is believed that placing the power rails on the back side allows gains in cell area in the range of 20% to 30%.

[00101] 3 illustrates a process flow diagram for a method 60 for thinning a semiconductor wafer according to some embodiments of the present disclosure. 4A-4E show wafer thinning stages according to some embodiments of the present disclosure. Method 60 is described below with respect to FIGS. 4A-4E. 4A-4E are cross-sectional views of an electronic device (eg, GAA) in accordance with one or more embodiments. Method 60 may be part of a multi-step fabrication process of a semiconductor device. Accordingly, method 60 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may be used in process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any used in the fabrication of semiconductor devices. Other suitable chambers may be included.

[00102] 4A to 4E are fabrication steps of operations 62 to 76 of FIG. 3 . Referring to FIG. 3 , method 60 of thinning device 400 begins at operation 62 . Referring to FIGS. 3 and 4A-4E , in a method of one or more embodiments, transistors, eg, gate-all-around transistors, are fabricated using standard process flows.

[00103] In some embodiments, a silicon wafer 402 is provided and, in operation 62, a buried etch stop layer 404 is formed on the silicon wafer. The buried etch stop layer 404 may include any suitable material known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 includes silicon germanium (SiGe). In one or more embodiments, the buried etch stop layer 404 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium ranges from 30% to 50%, including from 35% to 45%. Without intending to be bound by theory, it is believed that a germanium content in the range of 30% to 50% increases the selectivity of the buried etch stop layer 404 and minimizes stress defects.

[00104] In one or more illustrative embodiments, at operation 64, an epitaxial layer, eg, epitaxial silicon, is deposited. Then, in operation 66, the wafer is subjected to device and front-end processing. Front-end processing may be the processes described above with respect to method 6 illustrated in FIGS. 1A and 1B and illustrated in the cross-sectional views of FIGS. 2A-2U.

[00105] 3 and 4B, in operation 68, in one or more embodiments, after front-end processing, wafer 400 undergoes hybrid bonding, for example to copper or oxide, and then the wafer is Favorably thinned. Without intending to be bound by theory, it is believed that thinning the wafer advantageously provides the desired flatness and bonding to enable the backside power rail.

[00106] In one or more embodiments, referring to FIGS. 3 and 4C, to thin the wafer, in operation 70, a silicon substrate layer 402 having a starting first thickness t ₁ is coated with a second thickness, and the second thickness t ₂ is smaller than the first thickness. The silicon substrate layer 402 may be ground by any suitable means known to those skilled in the art. In some embodiments, the silicon substrate layer 402 is treated with chemical mechanical planarization (CMP), followed by etching and CMP buffing, reducing the thickness of the silicon substrate layer 402 to a third thickness t ₃ . and the third thickness is less than the second thickness. In one or more embodiments, the first thickness is in the range of 500 μm to 1000 μm. In one or more embodiments, the second thickness is in the range of 20 μm to 100 μm. In one or more embodiments, the third thickness is in the range of 1 μm to 20 μm.

[00107] Referring to FIGS. 3 and 4D , in operation 72 , buried etch stop layer 404 is selectively removed to expose source/drain 408 . In operation 74, contacts 410 are then pre-filled with metal, and metallization is performed, as illustrated in FIG. 4E. In one or more embodiments, contact 410 is titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[00108] 5A-5E illustrate alternative fabrication steps of operations 78-80 of FIG. Referring to FIG. 3 , a method 60 of thinning a device 400 begins at operation 62 and proceeds to operation 70 as illustrated in detail in FIGS. 4A-4C .

[00109] After the silicon substrate 402 is thinned by silicon grinding in operation 70, the method may proceed to operation 78, where a large mask 502 is formed over the buried etch stop layer 404. . Mask 502 may include any suitable material known to those skilled in the art. In one or more embodiments, mask 502 is selected from one or more of carbide, boron carbide, and silicon nitride.

[00110] In operation 80 , the mask 502 is etched to form a plurality of thru silicon vias (TSVs) 508 extending to the buried etch stop layer 404 . Vias 508 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, vias 508 are formed by etching. Nanometer-sized TSVs allow high-density packaging of these formed devices, or other chips connected to such devices, without the need for existing large TSVs that add cost and space to typical 3D packaging.

[00111] In operation 82 , referring to FIGS. 3 and 5C , the buried etch stop layer 404 is selectively removed to form an opening 510 . The buried etch stop layer 404 may be selectively removed by any suitable means known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 is selectively removed by etching the side of the device.

[00112] Referring to Figures 3 and 5D, in operation 84, the mask 508 having vias 508 is lifted off the device. Liftoff may occur by any suitable means known to those skilled in the art. In one or more embodiments, liftoff allows thinning the wafer to a thickness ranging from 50 nm to 100 nm. In one or more embodiments, liftoff results in a thinned wafer that is substantially free of defects and scratches on device 500 . In one or more embodiments, liftoff requires a lateral (isotropic etch) of the sacrificial layer 120 across the wafer, which is accomplished by a Selectra® etch.

[00113] 6 illustrates a process flow diagram for a method 600 of fabricating a semiconductor device in accordance with some embodiments of the present disclosure. 7A-7D show stages of forming a deep via and back contact in accordance with some embodiments of the present disclosure. Method 600 is described below with respect to FIGS. 7A-7D. 7A-7D are cross-sectional views of an electronic device (eg, GAA) 700 in accordance with one or more embodiments. Method 600 can be part of a multi-step fabrication process of a semiconductor device. Accordingly, method 600 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may be used in process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any used for fabrication of semiconductor devices. of other suitable chambers.

[00114] 7A-7D are fabrication steps of operations 602-614 of FIG. Referring to FIG. 6 , a method 600 of forming deep vias and back contacts begins at operation 602 . 6 and 7A-7D , in method 600 of one or more embodiments, transistors, eg, gate-all-around transistors, are fabricated in operation 602 using a standard process flow. . Device 700 may be formed according to the methods described with respect to FIGS. 1A and 1B and FIGS. 2A-2Q .

[00115] In operation 604, at least one deep via 702 is formed in the front surface, as illustrated in FIG. 7A. Deep via 702 can have any suitable size or shape. Deep via 702 can have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is greater than about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1; same. In one or more embodiments, the critical dimensions of deep via 702 are about 16 nm by about 16 nm, or about 10 nm by about 10 nm, or about 15 nm by about 15 nm, or about 20 nm by 20 nm. .

[00116] Referring to FIGS. 6 and 7B , in operation 606 , deep via 702 may be filled with metal 704 . Metal 704 can be any suitable metal known to those skilled in the art. In one or more embodiments, metal 704 is titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[00117] Referring to Figures 6 and 7C, in operation 608, a bonding wafer 706 is bonded to the front side. At operation 610, the substrate 708 may optionally be thinned according to the method(s) described above with respect to FIG. Then, in operation 612, contacts 710 are formed to electrically connect to metal 704 in deep via 702, as illustrated in FIG. 7D. Contact 710 may include any suitable material known to those skilled in the art. In one or more embodiments, contact 710 may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like. Then, in operation 614, metallization occurs, as illustrated in FIG. 7D.

[00118] In some embodiments, these methods are integrated such that there is no vacuum break. In one or more embodiments, the method 60 is a via etch (act 80), removal of the buried sacrificial layer (act 82), and substrate release liftoff (act 84). It can be integrated so that there is no vacuum break in between.

[00119] Further embodiments of the present disclosure relate to processing tools 300 for formation of the described GAA devices and methods, as shown in FIG. 8. A variety of multiple processing platforms, including the Reflexion® ^CMP , Selectra® Etch, ^Centura® , Dual ACP, Producer® ^GT , and ^Endura® platforms available from Applied Materials®, as well as other processing systems may be used. The cluster tool 300 includes at least one central transfer station 314 having a plurality of sides. A robot 316 is positioned within the central transfer station 314 and is configured to move a robot blade and wafer to each of a plurality of sides.

[00120] The cluster tool 300 includes a plurality of processing chambers 308, 310, 312 (also referred to as process stations) connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent process stations. The processing chamber may be any suitable chamber including, but not limited to, a pre-clean chamber, a deposition chamber, an anneal chamber, an etch chamber, and the like. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered limiting the scope of the present disclosure.

[00121] In the embodiment shown in FIG. 8 , a factory interface 318 is connected to the front of the cluster tool 300 . The factory interface 318 includes chambers 302 for loading and unloading on the front surface 319 of the factory interface 318 .

[00122] The size and shape of the loading and unloading chambers 302 may vary depending on the substrate being processed in the cluster tool 300, for example. In the illustrated embodiment, the loading and unloading chamber 302 is sized to hold a wafer cassette with a plurality of wafers positioned within the cassette.

[00123] Robots 304 are within the factory interface 318 and can move between the loading and unloading chambers 302 . Robots 304 may transfer wafers from a cassette in loading chamber 302 to loadlock chamber 320 via factory interface 318 . The robots 304 may also transfer wafers from the loadlock chamber 320 to a cassette in the unloading chamber 302 via the factory interface 318 .

[00124] Robot 316 in some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. Robot 316 is configured to move wafers between chambers around transfer chamber 314 . Individual wafers are transported on a wafer transport blade located at the distal end of the first robotic instrument.

[00125] A system controller 357 communicates with the robot 316 and the plurality of processing chambers 308 , 310 , 312 . System controller 357 may be any suitable component capable of controlling processing chambers and robots. System controller 357 may be, for example, a computer comprising central processing unit (CPU) 392, memory 394, inputs/outputs 396, appropriate circuits 398, and storage. can be

[00126] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by the processor, cause the process chamber to perform the processes of the present disclosure. Software routines may also be stored and/or executed by a second processor (not shown) located remotely from hardware controlled by the processor. Some or all of the methods of this disclosure may also be performed in hardware. Accordingly, a process may be implemented in software and executed using a computer system, or may be implemented in hardware, such as as an application specific integrated circuit or other type of hardware implementation, or may be implemented as a combination of software and hardware. The software routines, when executed by the processor, transform the general purpose computer into a special purpose computer (controller) that controls chamber operation so that processes are performed.

[00127] In some embodiments, system controller 357 is configured to control the rapid thermal processing chamber to crystallize the template material.

[00128] In one or more embodiments, a processing tool includes: a central transfer station comprising a robot configured to move a wafer; a plurality of process stations, each process station connected to a central transfer station and providing a processing area separate from processing areas of adjacent process stations, the plurality of process stations including a template deposition chamber and a template crystallization chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between the process stations and to control the process occurring at each process station.

[00129] The use of the singular expressions, "a", "an," and similar referents in the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), unless otherwise indicated herein or otherwise clearly contradicted by context, the use of the singular forms, "an" and "an" It should be construed as covering both plural forms. Recitation of ranges of values herein is only intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, where each separate value is: Individual values of are incorporated herein as if individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Any and all examples provided herein, or use of exemplary language (eg, “such as”), are intended only to further clarify the materials and methods and do not pose limitations on scope unless otherwise claimed. . No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[00130] References throughout this specification to “one embodiment,” “particular embodiments,” “one or more embodiments” or “an embodiment” refer to a particular feature, structure, material, or It means that the feature is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one or more embodiments,” “in certain embodiments,” “in one embodiment,” or “in an embodiment” in various places throughout this specification necessarily indicate that this disclosure It is not intended to represent the same embodiment of the subject matter. Moreover, particular features, structures, materials, or characteristics may be combined in any suitable way in one or more embodiments.

[00131] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments merely illustrate the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Accordingly, this disclosure may contain modifications and variations that come within the scope of the appended claims and their equivalents.

Claims (20)

As a method of forming a semiconductor device,
forming an etch stop layer on the top surface of the substrate, the substrate having a first thickness;
forming an epitaxial layer on the top surface of the etch stop layer;
forming a wafer device on the top surface of the epitaxial layer;
bonding the wafer device to a bonding wafer;
grinding the substrate to form a substrate having a second thickness less than the first thickness;
planarizing the substrate to form a substrate having a third thickness less than the second thickness;
removing the etch stop layer to expose source/drain regions on the wafer device; and
Forming contacts electrically coupled to the source/drain regions.
A method of forming a semiconductor device. According to claim 1,
The first thickness ranges from 500 μm to 1000 μm,
A method of forming a semiconductor device. According to claim 1,
The second thickness ranges from 20 μm to 100 μm,
A method of forming a semiconductor device. According to claim 1,
The third thickness is in the range of 1 μm to 20 μm,
A method of forming a semiconductor device. According to claim 1,
Forming the wafer device,
Forming a superlattice structure on the top surface of the etch stop layer on the substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor materials alternately arranged in a plurality of stacked pairs. contains layers;
forming a gate structure on an uppermost surface of the superlattice structure;
forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate;
forming an inner spacer layer on each of the plurality of horizontal channel layers;
forming a source region and a drain region;
forming a replacement metal gate;
forming CT and CG electrically contacting the source region and the drain region; and
Including forming a first metal line,
A method of forming a semiconductor device. According to claim 1,
wherein the etch stop layer comprises silicon germanium (SiGe);
A method of forming a semiconductor device. According to claim 6,
The silicon germanium (SiGe) has a germanium (Ge) content in the range of 30% to 50%,
A method of forming a semiconductor device. According to claim 6,
The silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof.
A method of forming a semiconductor device. According to claim 5,
wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently include one or more of silicon germanium (SiGe) and silicon (Si).
A method of forming a semiconductor device. According to claim 5,
Forming the source and drain regions comprises growing an epitaxial layer.
A method of forming a semiconductor device. According to claim 5,
The source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).
A method of forming a semiconductor device. According to claim 5,
further comprising forming a dielectric layer over the gate structure and over the superlattice structure.
A method of forming a semiconductor device. According to claim 5,
The gate structure is one of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon. including more than
A method of forming a semiconductor device. As a method of forming a semiconductor device,
forming an etch stop layer on a top surface of a substrate, the substrate having a first thickness;
forming an epitaxial layer on the top surface of the etch stop layer;
forming a wafer device on the top surface of the epitaxial layer;
bonding the wafer device to a bonding dummy wafer or Cu wafer by hybrid bonding;
grinding the substrate to form a substrate having a second thickness less than the first thickness;
depositing a mask layer on the bottom surface of the etch stop layer;
forming at least one via opening in the mask layer;
selectively removing the etch stop layer; and
removing the mask layer to expose the substrate, the substrate having a fourth thickness less than the first thickness.
A method of forming a semiconductor device. According to claim 14,
The first thickness ranges from 500 μm to 1000 μm,
A method of forming a semiconductor device. According to claim 14,
The fourth thickness ranges from 50 nm to 100 nm,
A method of forming a semiconductor device. According to claim 14,
wherein the etch stop layer comprises silicon germanium (SiGe);
A method of forming a semiconductor device. According to claim 17,
The silicon germanium (SiGe) has a germanium (Ge) content in the range of 30% to 50%,
A method of forming a semiconductor device. According to claim 17,
The silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof.
A method of forming a semiconductor device. According to claim 14,
Forming the wafer device,
forming a superlattice structure on a top surface of the etch stop layer on the substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately in a plurality of stacked pairs. Ham ;
forming a gate structure on the top surface of the superlattice structure;
forming a plurality of source trenches and a plurality of drain trenches adjacent to the superlattice structure on the substrate;
forming an inner spacer layer on each of the plurality of horizontal channel layers;
forming a source region and a drain region;
forming a replacement metal gate;
forming CT and CG electrically contacting the source region and the drain region; and
Including forming a first metal line,
A method of forming a semiconductor device.

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