KR20230020259A - Method for manufacturing thin film transistor and display device - Google Patents

Abstract

The present invention relates to a method for manufacturing a thin film transistor and a display device. After forming a source/drain contact hole, a natural oxide film is removed by dry etching. After the natural oxide film is removed, a source/drain metal film is continuously formed in a vacuum state to maintain low contact resistance and uniform contact resistance.

Description

Method for manufacturing thin film transistor and display device {Method for manufacturing thin film transistor and display device}

The present invention relates to a method for manufacturing a thin film transistor and a display device, and more particularly, to a method for manufacturing a low temperature polysilicon thin film transistor and a method for manufacturing a display device using the same.

As the information society develops, demands for display devices are also increasing in various forms. In response to this, various display devices such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel), ELD (Electro Luminescent Display), VFD (Vacuum Fluorescent Display), OLED (Organic Light Emitting Diode) display devices have been studied. , some of which are already being utilized as display devices in various equipment.

In particular, the display device as described above includes a thin film transistor array substrate including thin film transistors that are switching elements formed in each pixel area. The thin film transistor may use silicon as an active layer (semiconductor layer). As the silicon constituting the thin film transistor, amorphous silicon or polysilicon is widely used.

In the amorphous silicon thin film transistor (a-Si TFT), since the active layer constituting the source/drain region and the channel region is amorphous silicon, 1 cm2/ It may have a low electron mobility of Vs or less.

However, recent display devices require high resolution, high aperture ratio, and narrow boarder for high image quality, requiring thin film transistors with higher electron mobility. Since the organic light emitting device disposed in the pixel is driven by a current driving method, a thin film transistor requiring particularly high electron mobility has been required.

Accordingly, there is a tendency to replace the amorphous silicon thin film transistor with a low temperature polysilicon thin film transistor (LTPS TFT) having higher electron mobility. The electron mobility of the polycrystalline silicon thin film transistor is about 70 to 100 cm 2 /Vs, and the electron mobility is higher than that of the amorphous silicon thin film transistor, and the stability against light irradiation is excellent. Accordingly, the polycrystalline silicon thin film transistor may be suitable for use as an active layer of a driving transistor and a switching transistor of a high-definition liquid crystal display and an organic light emitting display.

A natural oxide film exists on the polycrystalline silicon used as the active layer, which increases contact resistance when connecting source/drain electrodes to the active layer.

Therefore, contact resistance can be reduced if the source/drain metal is deposited after removing the natural oxide film by a wet method using a diluted HF solution before forming the source/drain electrodes.

In addition, the HF wet method has no selectivity between the gate insulating film composed of oxide film and nitride film and the ILD interlayer insulating film, so they are etched together and the contact hole can be formed with a reverse taper. In this case, the metal film for the source/drain electrode A film may not be completely formed on the inner wall of the contact hole, and voids may exist. Due to such a cause, there is a risk of disconnection of the source/drain electrodes.

In addition, when the natural oxide film is removed with a diluted HF solution and then exposed to the air, a natural oxide film is generated on the polysilicon again, so the contact resistance between the active layer and the source/drain electrode may increase, and the stagnation time after removing the natural oxide film must be constantly managed, and when the stagnant time is different, a difference in contact resistance between the source/drain electrode and the active layer is generated for each region of the display device, resulting in deterioration in display quality of the display device.

The present invention has been made to solve the above problems, and the natural oxide film is removed by a dry etching method, and after the natural oxide film is removed, a source/drain metal film is continuously formed in a vacuum state so as not to be exposed to the atmospheric state, resulting in low contact resistance. and a method for manufacturing a thin film transistor and a display device capable of maintaining uniform contact resistance.

In order to achieve the above object, a thin film transistor manufacturing method according to the present invention forms an amorphous silicon layer on a substrate, crystallizes the amorphous silicon layer into polycrystalline silicon, and patterns the polycrystalline silicon to form an active layer of the thin film transistor. Forming a polycrystalline silicon pattern, which is a layer, forming a gate insulating film on the entire surface of the substrate including the polycrystalline silicon pattern, forming a gate electrode on the gate insulating film above a central portion of the polycrystalline silicon pattern; , forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode, forming an interlayer insulating film on the entire surface of the substrate including the gate electrode, and the source region and the drain region forming source and drain contact holes by partially etching the interlayer insulating film and the gate insulating film so as to be exposed; and forming a natural polysilicon pattern on the source and drain regions exposed by the source and drain contact holes. removing the oxide film by dry etching; and forming source and drain electrodes on the interlayer insulating film so as to be electrically connected to the source region and the drain region through the source and drain contact holes. It has that characteristic.

In addition, a method of manufacturing a display device according to the present invention to achieve the above object is to form an amorphous silicon layer on a substrate, crystallize the amorphous silicon layer into polycrystalline silicon, and then pattern the polycrystalline silicon to form a thin film. Forming a polysilicon pattern, which is an active layer of a transistor, forming a gate insulating film on the entire surface of the substrate including the polysilicon pattern, and forming a gate electrode on the gate insulating film above a central portion of the polysilicon pattern. forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode; forming an interlayer insulating film on the entire surface of the substrate including the gate electrode; forming source and drain contact holes by partially etching the interlayer insulating film and the gate insulating film to expose a drain region; removing the natural oxide layer formed on the layer by dry etching; and forming source and drain electrodes on the interlayer insulating layer to be electrically connected to the source and drain regions through the source and drain contact holes. and forming a planarization film on the entire surface of the interlayer insulating film including the source electrode and the drain electrode, and forming a contact hole in the planarization film to expose the drain electrode, and electrically connecting the drain electrode through the contact hole. forming a first electrode on the planarization layer to be connected thereto; forming a pixel-defining layer on the planarization layer to expose the first electrode; forming a light emitting layer on the first electrode; It is characterized by including the step of forming a second electrode in.

In addition, a method of manufacturing a display device according to the present invention to achieve the above object is to form an amorphous silicon layer on a first substrate, crystallize the amorphous silicon layer into polycrystalline silicon, and then pattern the polycrystalline silicon. forming a polycrystalline silicon pattern, which is an active layer of a thin film transistor; forming a gate insulating film on the entire surface of the first substrate including the polycrystalline silicon pattern; and forming a gate insulating film on the upper side of the central portion of the polycrystalline silicon pattern. forming a gate electrode; forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode; forming an interlayer insulating film on the entire surface of the substrate including the gate electrode; forming source and drain contact holes by partially etching the interlayer insulating film and the gate insulating film to expose the source region and the drain region; removing the natural oxide layer formed on the polysilicon pattern of the source and drain regions exposed by the source and drain contact holes by a dry etching method; forming a source electrode and a drain electrode on the interlayer insulating film so as to be electrically connected to a region, forming a planarization film on the entire surface of the interlayer insulating film including the source electrode and the drain electrode, and exposing the drain electrode; Forming a contact hole in the planarization layer, forming a pixel electrode on the planarization layer to be electrically connected to the drain electrode through the contact hole, and forming a black matrix layer in an area corresponding to each pixel area. and preparing a second substrate on which color filter layers are formed corresponding to each pixel area, bonding the first and second substrates, and forming a liquid crystal layer on the first and second substrates. There are other features.

In the manufacturing method of the thin film transistor and the display device according to the present invention having the above characteristics, the following effects are obtained.

First, since the natural oxide film formed on the polycrystalline silicon pattern exposed by the contact hole is removed by a dry etching method using plasma, the inside of the contact hole is not reverse taper, so the contact resistance and disconnection between the source/drain electrode and the source/drain region defects can be prevented.

Second, since the metal layer for source/drain electrodes is continuously formed in a vacuum without being exposed to atmospheric conditions after removing the natural oxide film, no additional natural oxide film is generated, resulting in good and uniform contact resistance between the source/drain electrode and the source/drain region. can keep

1 to 11 are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.
12 to 13 are cross-sectional views illustrating a manufacturing method of the display device according to the first embodiment of the present invention.
14 is a cross-sectional view illustrating a method of manufacturing a display device according to a second exemplary embodiment of the present invention.
15 to 18 are cross-sectional views of plasma equipment according to various embodiments of the present invention for removing a natural oxide film using a dry etching method.
FIG. 19 is a device configuration diagram illustrating that the processes of FIGS. 10 to 12 are performed in a single chamber.

Advantages and features of the present invention, and how to achieve them, will become clear with reference to the detailed description of the following embodiments. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided so that the possessor can easily understand the scope of the invention, and the present invention is defined by the description of the claims.

Meanwhile, terms used in this specification are for describing the embodiments and are not intended to limit the present invention. In this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. “Comprises” or “comprising” as used in the specification does not preclude the addition of one or more other elements other than the recited elements.

Hereinafter, a semiconductor manufacturing apparatus according to the present invention and a manufacturing method of a thin film transistor and a display device using the same will be described in more detail with reference to the accompanying drawings.

1 to 11 are process cross-sectional views for explaining a thin film transistor manufacturing method according to an embodiment of the present invention.

As shown in FIG. 1 , a buffer layer 120 and an amorphous silicon layer 130 are sequentially deposited on a substrate 110 by plasma enhanced chemical vapor deposition (PECVD).

The substrate 110 may be an insulating substrate including glass, quartz, ceramic, or the like. The substrate 110 may be an insulating flexible substrate made of plastic such as polyimide (PI). The substrate 110 may be a substrate on which a plastic layer such as polyimide (PI) is formed on a substrate such as glass or quartz.

The buffer layer 120 may provide a flat surface on the top of the substrate 110 and prevent impurities from penetrating through the substrate 110 . The buffer layer 120 may be formed of a two-layer film of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

In this process, a natural oxide film 131 may be formed on the upper surface of the amorphous silicon layer 130 . The natural oxide layer 131 may be naturally formed by exposing the upper portion of the amorphous silicon layer 130 to air.

The natural oxide film 131 on the amorphous silicon layer affects ELA (Excimer Laser Annealing) crystallization, which crystallizes the amorphous silicon layer into polycrystalline silicon, and since the natural oxide film has a non-uniform thickness, ELA crystallization may become non-uniform.

Therefore, as shown in FIG. 2 , the native oxide film 131 is removed with a diluted HF solution.

As shown in FIG. 3, a uniform high-quality natural oxide film 132 is formed on the upper surface of the amorphous silicon layer 130 again by washing with ultrapure water containing O3.

As shown in FIGS. 4 and 5 , the amorphous silicon layer 130 is crystallized into polycrystalline silicon 133 by irradiating an excimer laser to the amorphous silicon layer 130 .

As shown in FIG. 6, a photo resist (not shown in the figure) is coated on the polycrystalline silicon 133, and the polycrystalline silicon 133 is selectively removed by an exposure and development process using a mask. Thus, the polysilicon pattern 135, which is an active layer of the thin film transistor, is formed, and the natural oxide film 132 remaining on the polysilicon pattern 135 is removed with a diluted HF solution.

As shown in FIG. 7 , a gate insulating layer 140 is formed on the entire surface of the buffer layer 120 on which the polysilicon pattern 135 is formed.

Then, a metal layer and a photoresist film (not shown) are sequentially coated on the gate insulating film 140, and a photoresist film pattern is formed through an exposure and development process using a mask. A gate electrode of a thin film transistor is formed by selectively removing the metal layer by a detection etching process or a wet etching process using the photoresist film pattern as a mask.

Here, the gate insulating film 140 may be formed as a two-layer film of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

The metal layer for the gate electrode (Gate) is made of aluminum (AL), molybdenum (Mo), titanium (Ti), tantalum (Ta), and alloys thereof, and may be made of a single metal layer or a multi-layer metal layer.

In this case, the gate electrode (Gate) may be formed to overlap the central portion of the polysilicon pattern 135 .

As shown in FIG. 8, ions are partially implanted into the polysilicon pattern 135 on both sides of the gate electrode (Gate) using the gate electrode (Gate) as a mask to form a source region (Source and Drain region). The ion may be an n-type impurity or a p-type impurity.

A portion of the polysilicon pattern 135 overlapping the gate electrode is not doped with ions and a channel region is formed.

As shown in FIG. 9 , the gate electrode Gate, the source region Source, and the drain region Drain cover the gate electrode Gate, the source region Source, and the drain region Drain. ) is formed on the entire surface of the substrate 110 to form an interlayer insulating film 150.

The interlayer insulating layer 150 may include silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.

Then, the interlayer insulating layer 150 and the gate insulating layer 140 are partially etched to expose the source region Souece and the drain region Drain, thereby forming source and drain contact holes 151 .

At this time, a natural oxide layer is formed on the polysilicon pattern of the source region (Souece) and the drain region (Drain) exposed by the contact hole 151 .

As described above, the natural oxide film formed in the contact hole 151 provides contact resistance between the source and drain electrodes, the source region (Souece), and the drain region (Drain) when the source and drain electrodes are formed, which is a subsequent process. This increases, and a difference in contact resistance is generated for each region, which causes deterioration in image quality when applied to a display device. Therefore, the natural oxide film formed in the contact hole 151 needs to be removed.

As shown in FIG. 10 , the natural oxide layer formed on the polysilicon pattern of the source region (Souece) and the drain region (Drain) exposed by the contact hole 151 is removed.

A method of removing the natural oxide film uses a dry etching method rather than a wet etching method.

Specifically, as shown in FIGS. 15 to 18, the natural oxide film is removed using plasma in a vacuum state using various types of plasma facilities.

That is, the plasma method used is a capacitively coupled plasma (CCP) method as shown in FIGS. 15 and 16, an inductively coupled plasma (ICP) method as shown in FIG. 17, and a remote induction as shown in FIG. 18 One of the plasma (Remote plasma) methods can be used or a mixture of them can be used.

FIG. 15 shows a plasma etch (PE) mode among capacitive coupled plasma methods, and FIG. 16 shows a reactive ion etch (RIE) mode among capacitive coupled plasma methods.

The gas used at this time can be a mixed gas by mixing one of the gases (source gas) such as CF4, SF6, CHF3, NF3, and HF and one of the gases such as Ar, N2, and H2. At this time, the selectivity between the natural oxide film and the polycrystalline silicon should be high, and the polycrystalline silicon pattern should be etched as little as possible when removing the natural oxide film. In addition, since the plasma treatment is performed using H2, N2, and Ar gas, the removal of fluorine groups that may remain on the substrate or modification of the surface may be induced.

Therefore, since it is a dry etching method rather than a wet etching method, the inclination of the contact hole is not a reverse taper, but a positive taper can be easily made.

In general, when the natural oxide film is removed by a wet method using a diluted HF solution, since the gate insulating film 140 and the interlayer insulating film 150 are formed of silicon oxide (SiOx) or silicon nitride (SiNx), the natural oxide film 140 and the interlayer insulating film 150 are formed. The etching selectivity of the gate insulating film 140 and the interlayer insulating film 150 relative to the oxide film is not high.

Therefore, when the natural oxide film is etched by a wet method using a diluted HF solution, not only the natural oxide film but also the interlayer insulating film of the gate insulating film 140 and the interlayer insulating film 150 can be etched, and the gate insulating film ( 140) and the interlayer insulating film 150 are formed of a double film, since the etching rates of silicon oxide (SiOx) and silicon nitride (SiNx) are different, the wall surface of the cortac hole 151 can be formed in an inverse taper shape. there is.

In addition, if the natural oxide film is removed with a diluted HF solution and then exposed to atmospheric conditions, a natural oxide film is generated on the polysilicon again. There is a difference in the contact resistance between them.

As shown in FIG. 11, a metal layer is deposited on the interlayer insulating film 150 including the contact hole 151 by a sputtering method, and the metal layer is formed by photolithography and an etching process using a photoresist film. It is selectively removed to form a source electrode (Source electrode) and a drain electrode (Drain electrode) electrically connected to the source region (Source) and the drain region (Drain) through the contact hole 151 .

Here, the metal layer includes aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), titanium (Ti) or an alloy thereof, and has a single layer or a multi-layer structure including different metal layers. can

During the manufacturing process of the thin film transistor (the process of FIGS. 10 and 11 ), after removing the natural oxide film formed on the polysilicon pattern exposed by the contact hole 151, a natural oxide film is formed again when exposed to air. It can be.

Therefore, in order to prevent the formation of an additional natural oxide film, as shown in FIG. 19, the plasma etching device and the sputtering device may be continuously arranged in a vacuum state.

That is, as shown in FIG. 19, at least one load lock chamber LL B/U, one plasma chamber CH A, and at least one metal deposition chamber around one transfer chamber TM. Equipment consisting of (CH B, CH D, CH E) can be used.

Specifically, the substrate on which the contact hole 151 is formed (substrate as shown in FIG. 10) is transferred to the plasma chamber CH A, and the source region exposed by the contact hole 151 and the The natural oxide film formed on the polysilicon pattern in the drain region is removed (a process shown in FIG. 10). Then, the substrate from which the natural oxide layer is removed is transferred from the plasma chamber (CH A) to one of the metal deposition chambers (CH B, CHD, CH E) through the transfer chamber (TM) in a vacuum state.

That is, it is transferred to one of the metal deposition chambers (CH B, CH D, CH E) according to the metal layers for the source and drain electrodes. If the metal layer for source and drain electrodes is Ti/Mo, it is transferred to a metal deposition chamber (CH B or CH E), and if the metal layer for source and drain electrodes is Al, it is transferred to a metal deposition chamber (CH C or CHD) transfer to

Then, metal layers for the corresponding source and drain electrodes are deposited in the corresponding metal deposition chamber (a process shown in FIG. 11).

As described above, a thin film transistor can be manufactured.

Meanwhile, a method of manufacturing a display device using the thin film transistor as described above will be described.

As shown in FIG. 12 , a planarization layer (or protective layer) 160 may be formed on the entire surface of the interlayer insulating layer 150 including the source electrode and the drain electrode. Since the planarization layer 160 is disposed on the interlayer insulating layer 150 to cover the source and drain electrodes, the pixel electrode 170 can be insulated from the source and drain electrodes.

The planarization layer 160 may include an organic insulating layer, an inorganic insulating layer, or a combination thereof. For example, the planarization layer 160 may have a single-layer or multi-layer structure of silicon nitride or silicon oxide, and may include polyimide, acrylic resin, or the like when including an organic insulating layer.

A contact hole is formed by selectively removing the planarization layer 160 to expose the drain electrode. A conductive layer may be deposited on the planarization layer 160 and selectively removed to form a pixel electrode 170 electrically connected to the drain electrode. In this way, an active matrix type thin film transistor is formed, and as shown in FIG. 13, an organic light emitting element is formed on the pixel electrode to form an organic light emitting display device, or a liquid crystal display device is formed as shown in FIG. 14. can

In the case of forming an organic light emitting display device, as shown in FIG. 13 , the pixel electrode 170 may be the first electrode of the organic light emitting device, and may be formed as a transmissive electrode or a reflective electrode depending on the light emitting type. It can be.

Accordingly, a pixel define layer (PDL) 180 may be formed on the planarization layer 160 . The pixel-defining layer 180 generally uses an organic insulating layer and may have an opening exposing at least a portion of the pixel electrode. After that, the organic emission layer 190 may be formed on the pixel electrode.

The organic emission layer 190 may be formed on the upper surface of the pixel electrode exposed by the opening of the pixel defining layer 180, may include a low molecular organic compound or a high molecular organic compound, and may be formed by a method such as deposition or inkjet printing. can

The organic light emitting layer 190 may emit red light, green light, or blue light, and in another embodiment, the organic light emitting layer 190 may emit white light.

Also, a second electrode that is the common electrode 200 may be formed on the organic light emitting layer 190 . The second electrode may be formed as a transmissive electrode or a reflective electrode according to the light emitting type of the display device.

When forming a liquid crystal display device, the pixel electrode 170 is generally formed of a transmissive metal (ITO or IZO).

As shown in FIG. 14 , a color filter array substrate 111 is positioned opposite to the thin film transistor array substrate 110 .

On the color filter array substrate 111, a black matrix layer 330 is formed in an area corresponding to each pixel area, and a red (R), green (G), and blue (B) color filter layer 32 corresponding to each pixel area. ) can be formed.

A common electrode 301 made of a transparent metal material is formed over the black matrix layer 330 and the color filter layer 320 . An alignment layer 340 is formed on the common electrode 301, and alignment of liquid crystal molecules may be induced by rubbing the alignment layer 340.

If necessary, planarization may be performed with a transparent material before forming the common electrode (not shown).

The common electrode 301 may be disposed on the thin film transistor array substrate 110 in IPS mode or FFS mode for improving viewing angle.

In order to secure a certain space between the thin film transistor array substrate 110 and the color filter array substrate 111, a column spacer (not shown) is formed on at least one of the thin film transistor array substrate 110 and the color filter array substrate 111. ) can be formed.

The thin film transistor array substrate 110 and the color filter array substrate 111 are formed so that the pixel electrode 170 of the thin film transistor array substrate 110 and the common electrode 301 of the color filter array substrate 111 face each other. bonded together with a sealing material. Then, a liquid crystal layer 350 is injected between the thin film transistor array substrate 110 and the color filter array substrate 111 .

Before bonding the thin film transistor array substrate 110 and the color filter array substrate 111, a liquid crystal layer is dropped on the thin film transistor array substrate 110 or the color filter array substrate 111, and then the thin film transistor The array substrate 110 and the color filter array substrate 111 may be bonded together.

In addition, a backlight (not shown) is positioned under the thin film transistor array substrate to provide a light source, and a polarizer 351 is attached to the rear surface of the thin film transistor array substrate 110 and the upper surface of the color filter array substrate 111 to emit light. can be polarized.

In this way, the thin film transistor controls the electric field of the pixel, and this electric field controls or blocks the amount of light coming in through the control of the liquid crystal induced in the alignment layer, emits light through the color filter, and displays the color combination of each pixel. can play a role

The above detailed description should not be construed as limiting in all respects and should be considered illustrative. The scope of the present invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the present invention are included in the scope of the present invention.

110, 111: substrate 120: buffer layer
130: amorphous silicon layer 135: polycrystalline silicon pattern
140: gate insulating film Gate: gate electrode
Source: source region Drain: drain region
150: interlayer insulating film 151: source and drain contact holes
160: planarization film 170: pixel electrode
180: pixel defining layer 190: light emitting layer
200, 301: common electrode 320: color filter layer
330: black matrix layer 340: alignment layer
350: liquid crystal layer

Claims (9)

forming an amorphous silicon layer on a substrate, crystallizing the amorphous silicon layer into polycrystalline silicon, and then patterning the polycrystalline silicon to form a polycrystalline silicon pattern, which is an active layer of a thin film transistor;
forming a gate insulating film on the entire surface of the substrate including the polysilicon pattern;
forming a gate electrode on the gate insulating film above the central portion of the polysilicon pattern;
forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode;
forming an interlayer insulating film on the entire surface of the substrate including the gate electrode;
forming source and drain contact holes by partially etching the interlayer insulating layer and the gate insulating layer to expose the source region and the drain region;
removing the natural oxide layer formed on the polysilicon pattern of the source and drain regions exposed by the source and drain contact holes by a dry etching method; and
and forming a source electrode and a drain electrode on the interlayer insulating film so as to be electrically connected to the source region and the drain region through the source and drain contact holes. According to claim 1,
The method of manufacturing a thin film transistor, characterized in that the gate insulating film or the interlayer insulating film comprises silicon oxide, silicon nitride or a combination thereof. According to claim 1,
The gate electrode or the source and drain electrodes are formed of a metal layer including aluminum, molybdenum, titanium, tantalum, and alloys thereof, and formed of a single metal layer or a multi-layer metal layer. Method of manufacturing a thin film transistor. According to claim 1,
The step of removing the natural oxide film formed on the polycrystalline silicon pattern of the source region and the drain region by a dry etching method uses one of a capacitive coupled plasma method, an inductively coupled plasma method, and an induction plasma method, or a combination thereof. A method for manufacturing a thin film transistor. According to claim 4,
When using the capacitively coupled plasma method, a method of manufacturing a thin film transistor, characterized in that using a PE mode or RIE method plasma. According to claim 4,
The plasma method uses a mixture of a source gas and a reaction gas, the source gas includes CF4, SF6, CHF3, NF3, and HF, and the reaction gas includes Ar, N2, and H2. manufacturing method. According to claim 1,
The step of removing the natural oxide film formed on the polysilicon pattern of the source and drain regions exposed by the source and drain contact holes and the step of forming the source and drain electrodes may be performed at least around one transfer chamber. A method of manufacturing a thin film transistor, characterized by using equipment consisting of one load-lock chamber, one plasma chamber, and at least one metal deposition chamber. forming an amorphous silicon layer on a substrate, crystallizing the amorphous silicon layer into polycrystalline silicon, and then patterning the polycrystalline silicon to form a polycrystalline silicon pattern, which is an active layer of a thin film transistor;
forming a gate insulating film on the entire surface of the substrate including the polysilicon pattern;
forming a gate electrode on the gate insulating film above the central portion of the polysilicon pattern;
forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode;
forming an interlayer insulating film on the entire surface of the substrate including the gate electrode;
forming source and drain contact holes by partially etching the interlayer insulating layer and the gate insulating layer to expose the source region and the drain region;
removing the natural oxide layer formed on the polysilicon pattern of the source and drain regions exposed by the source and drain contact holes by a dry etching method;
forming source and drain electrodes on the interlayer insulating film to be electrically connected to the source and drain regions through the source and drain contact holes;
forming a planarization layer on the entire surface of the interlayer insulating layer including the source electrode and the drain electrode, and forming a contact hole in the planarization layer to expose the drain electrode;
forming a first electrode on the planarization layer to be electrically connected to the drain electrode through the contact hole;
forming a pixel-defining layer on the planarization layer to expose the first electrode; and
and forming a light emitting layer on the first electrode and forming a second electrode on the light emitting layer. forming an amorphous silicon layer on a first substrate, crystallizing the amorphous silicon layer into polycrystalline silicon, and then patterning the polycrystalline silicon to form a polycrystalline silicon pattern that is an active layer of a thin film transistor;
forming a gate insulating film on the entire surface of the first substrate including the polysilicon pattern;
forming a gate electrode on the gate insulating film above the central portion of the polysilicon pattern;
forming a source region and a drain region with impurity ions in the polysilicon pattern on both sides of the gate electrode;
forming an interlayer insulating film on the entire surface of the substrate including the gate electrode;
forming source and drain contact holes by partially etching the interlayer insulating layer and the gate insulating layer to expose the source region and the drain region;
removing the natural oxide layer formed on the polysilicon pattern of the source and drain regions exposed by the source and drain contact holes by a dry etching method;
forming source and drain electrodes on the interlayer insulating film to be electrically connected to the source and drain regions through the source and drain contact holes;
forming a planarization layer on the entire surface of the interlayer insulating layer including the source electrode and the drain electrode, and forming a contact hole in the planarization layer to expose the drain electrode;
forming a pixel electrode on the planarization layer to be electrically connected to the drain electrode through the contact hole;
preparing a second substrate on which a black matrix layer is formed in an area corresponding to each pixel area and color filter layers are formed corresponding to each pixel area;
A method of manufacturing a display device comprising bonding the first and second substrates and forming a liquid crystal layer on the first and second substrates.

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