KR20230020039A - Display device, method of manufacturing the same and tiled display device including the same - Google Patents

Abstract

A display device is provided. Provided is a display device which comprises: a first substrate including a first contact hole; a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction; an alignment pattern disposed on the same layer as the pad portion; an alignment key disposed on the alignment pattern and surrounded by the alignment pattern on a plane; a thin film transistor layer disposed on the alignment key; and a flexible film disposed on a lower surface of the first substrate and electrically connected to the pad portion through the first contact hole. In addition, reflectance of the alignment key for light of a specific wavelength is different from reflectance of the alignment pattern, the pad portion, and the thin film transistor layer. Accordingly, reliability can be secured by improving a recognition rate of the alignment key.

Description

Display device, manufacturing method thereof, and tile-type display device including the same

The present invention relates to a display device, a manufacturing method thereof, and a tile-type display device including the same.

As the information society develops, demands for display devices for displaying images are increasing in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart televisions. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, an organic light emitting display device, and the like. Among such flat panel display devices, a light emitting display device includes a light emitting element capable of emitting light by itself in each of the pixels of the display panel, so that an image can be displayed without a backlight unit providing light to the display panel.

When a display device is manufactured in a large size, a defect rate of a light emitting device may increase due to an increase in the number of pixels, and productivity or reliability may decrease. To solve this problem, a tile-type display device may implement a large screen by connecting a plurality of display devices having a relatively small size. The tile-type display device may include a boundary portion called a seam between the plurality of display devices due to the non-display area or the bezel area of each of the plurality of display devices adjacent to each other. When a single image is displayed on the entire screen, the boundary portion between the plurality of display devices gives a sense of disconnection to the entire screen, reducing the immersion of the image.

The problem to be solved by the present invention is a display device capable of securing reliability by improving the recognition rate of an align key in an align process of a flexible film overlapping a display area under a substrate, a manufacturing method thereof, and a tile type including the same It is intended to provide a display device.

An object to be solved by the present invention is a tile-type display device capable of removing a sense of disconnection between a plurality of display devices and improving the immersion of an image by preventing a boundary portion or a non-display area between a plurality of display devices from being recognized. is to provide

The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment for solving the above problems includes a first substrate including a first contact hole, a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction, the same as the pad portion. An alignment pattern disposed on a layer, an alignment key disposed on the alignment pattern and surrounded by the alignment pattern on a plane, a thin film transistor layer disposed on the alignment key, and a lower surface of the first substrate and a flexible film disposed and electrically connected to the pad part through the first contact hole, wherein reflectance of the align key for light of a specific wavelength is determined by the alignment pattern, the pad part, and the thin film transistor layer. is different from the reflectance of

The align pattern may have a closed loop shape on a plane to form a pattern groove formed in an intaglio, and the align key may fill the pattern groove.

The display device may further include a barrier insulating layer that insulates the align key from the align pattern and forms an inner surface of the pattern groove.

A reflectance of the align key to light of the specific wavelength may be higher than reflectances of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or 0.1 or more.

The align key may include an organic material including a colored pigment or a metal.

The display device may further include a second substrate disposed on a layer between the align key and the thin film transistor layer, and the align key may be disposed on a layer between the align pattern and the second substrate.

The thin film transistor layer includes a connection wire connected to the pad portion, a light blocking layer disposed on the same layer as the connection wire, and a thin film transistor disposed on the connection wire and the light blocking layer and electrically connected to the connection wire. And, the reflectance of the align key for the light of the specific wavelength may be 0.2 or more higher or 0.1 or more lower than the reflectance of the connection wiring and the light blocking layer.

The thin film transistor includes an active layer, a drain electrode, and a source electrode disposed on the light blocking layer, and a gate electrode disposed on the active layer and insulated from the active layer, and The reflectance of the key may be higher than reflectances of the active layer, the drain electrode, the source electrode, and the gate electrode by 0.2 or more or 0.1 or more.

The display device further includes a light emitting element layer disposed on the thin film transistor layer and including a light emitting element, and the thin film transistor layer includes a connection electrode disposed on the gate electrode and connecting the thin film transistor and the light emitting element. The reflectance of the align key for light of the specific wavelength may be higher than that of the connection electrode by 0.2 or more or lower by 0.1 or more.

A display device according to an exemplary embodiment for solving the above problems includes a first substrate including a first contact hole, a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction, the same as the pad portion. An alignment pattern disposed on a layer, an alignment key disposed on the alignment pattern and surrounded by the alignment pattern on a plane, a second substrate disposed on the alignment key, and an alignment key disposed on the second substrate A thin film transistor layer and a flexible film disposed on a lower surface of the first substrate and electrically connected to the pad part through the first contact hole.

A reflectance of the align key to light of the specific wavelength may be higher than reflectances of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or 0.1 or more.

The align pattern may have a closed loop shape on a plane to form a pattern groove formed in an intaglio, and the align key may fill the pattern groove.

The display device may further include a barrier insulating layer that insulates the align key from the align pattern and forms an inner surface of the pattern groove.

A method of manufacturing a display device according to an exemplary embodiment for solving the above problems includes preparing a first substrate, forming a pad portion and an alignment pattern disposed on the first substrate, and disposing on the alignment pattern. Forming an align key surrounded by the alignment pattern on a plane, forming a thin film transistor layer disposed on the align key, patterning the first substrate to overlap the pad portion, and a first contact Forming a hole, aligning the flexible film on the pad part by irradiating light of a specific wavelength toward one surface of the align key facing the first substrate, and electrically electrically aligning the flexible film on the pad part. It includes the step of connecting to

The forming of the alignment pattern may include forming a pattern groove formed in a negative shape by forming an alignment pattern having a closed loop shape on a plane.

The manufacturing method of the display device may further include forming a barrier insulating layer directly covering the pad portion and the alignment pattern.

A reflectance of the align key to light of the specific wavelength may be higher than reflectances of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or 0.1 or more.

The manufacturing method of the display device may further include forming a second substrate disposed on the align key.

Forming the thin film transistor layer may include forming a connection wire disposed on the align key and connected to the pad portion, forming a light blocking layer disposed on the same layer as the connection wire, the connection wire and and forming a thin film transistor disposed on the light blocking layer and electrically connected to the connection wiring, wherein reflectance of the align key for light of the specific wavelength is determined by the connection wiring, the light blocking layer, and the thin film. It may be 0.2 or more higher than the reflectance of the transistor, or 0.1 or more lower than the reflectance of the transistor.

In order to solve the above problems, a tile-type display device according to an exemplary embodiment includes a plurality of display devices including a display area including a plurality of pixels and a non-display area surrounding the display area, and combining the plurality of display devices. A coupling member, and each of the plurality of display devices includes a first substrate including a first contact hole, a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction, and the pad portion; An alignment pattern disposed on the same layer, an alignment key disposed on the alignment pattern and surrounded by the alignment pattern on a plane, a thin film transistor layer disposed on the alignment key, and a lower surface of the first substrate and a flexible film disposed on and electrically connected to the pad part through the first contact hole, and reflectance of the align key for light of a specific wavelength is determined by the alignment pattern, the pad part, and the thin film transistor. It is different from the reflectance of the layer.

Other embodiment specifics are included in the detailed description and drawings.

According to the display device according to the embodiments, the manufacturing method thereof, and the tile-type display device including the same, it is possible to secure reliability by improving the recognition rate of an align key in an alignment process of a flexible film overlapping a display area under a substrate. can

According to the display device, manufacturing method thereof, and tile-type display device including the same according to the embodiments, the flexible film disposed under the substrate and the pad portion disposed on the substrate are electrically connected to each other, so that the non-display area of the display device is area can be minimized. Accordingly, the tile-type display device can prevent a user from recognizing a non-display area or a boundary between the plurality of display devices by minimizing the distance between the plurality of display devices.

Effects according to the embodiments are not limited by the contents exemplified above, and more various effects are included in this specification.

1 is a plan view illustrating a tile-type display device according to an exemplary embodiment.
2 is a plan view illustrating a display device according to an exemplary embodiment.
FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2 .
FIG. 4 is an enlarged view of area A1 of FIG. 3 .
5 is a bottom view illustrating a display device according to an exemplary embodiment.
6 to 14 are cross-sectional views illustrating a manufacturing process of a display device according to an exemplary embodiment.
15 is a plan view illustrating a coupling structure of a tile type display device according to an exemplary embodiment.
16 is a cross-sectional view taken along line II-II' of FIG. 15;

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs. It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as being "on" another element or layer, it includes all cases where another element or layer is directly on top of another element or another layer or other element intervenes therebetween. Like reference numbers designate like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative, and the present invention is not limited thereto.

Although first, second, etc. are used to describe various components, these components are not limited by these terms, of course. These terms are only used to distinguish one component from another. Accordingly, it goes without saying that the first element mentioned below may also be the second element within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in a related relationship. may be

Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

1 is a plan view illustrating a tile-type display device according to an exemplary embodiment.

Referring to FIG. 1 , a tile-type display device TD may include a plurality of display devices 10 . The plurality of display devices 10 may be arranged in a lattice shape, but is not limited thereto. The plurality of display devices 10 may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the tile-type display device TD may have a specific shape. For example, each of the plurality of display devices 10 may have the same size, but is not limited thereto. For another example, the plurality of display devices 10 may have different sizes.

Each of the plurality of display devices 10 may have a rectangular shape including a long side and a short side. The plurality of display devices 10 may be disposed with long or short sides connected to each other. Some of the display devices 10 may be disposed on the edge of the tile-type display device TD, forming one side of the tile-type display device TD. Another portion of the display device 10 may be disposed at a corner of the tile-type display device TD, and may form two adjacent sides of the tile-type display device TD. Another part of the display device 10 may be disposed inside the tiled display device TD and may be surrounded by other display devices 10 .

Each of the plurality of display devices 10 may include a display area DA and a non-display area NDA. The display area DA may display an image by including a plurality of pixels. Each of the plurality of pixels includes an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, and an inorganic light emitting diode including an inorganic semiconductor. , And may include at least one of a small light emitting diode (Micro LED). Hereinafter, it has been mainly described that each of a plurality of pixels includes an inorganic light emitting diode, but is not limited thereto. The non-display area NDA may be disposed around the display area DA to surround the display area DA and may not display an image.

The tile-type display device TD may have an overall planar shape, but is not limited thereto. The tile-type display device TD has a three-dimensional shape, so that it can give a user a three-dimensional effect. For example, when the tile-type display device TD has a three-dimensional shape, at least some of the display devices 10 among the plurality of display devices 10 may have a curved shape. As another example, since each of the plurality of display devices 10 has a planar shape and is connected to each other at a predetermined angle, the tile-type display device TD may have a three-dimensional shape.

The tile-type display device TD may include a coupling area SM disposed between the plurality of display areas DA. The tile-type display device TD may be formed by connecting non-display areas NDAs of adjacent display devices 10 to each other. The plurality of display devices 10 may be connected to each other through a coupling member or an adhesive member disposed in the coupling area SM. The coupling area SM of each of the plurality of display devices 10 may not include a pad portion or a flexible film attached to the pad portion. Accordingly, the distance between the display areas DA of each of the plurality of display devices 10 may be close enough that the coupling area SM between the plurality of display devices 10 is not recognized by the user. In addition, the external light reflectance of the display area DA of each of the plurality of display devices 10 and the external light reflectance of the coupling area SM between the plurality of display devices 10 may be substantially the same. Therefore, the tile-type display device TD prevents the user from perceiving the coupling area SM between the plurality of display devices 10, thereby improving the sense of disconnection between the plurality of display devices 10 and improving the immersion of the image. can improve

2 is a plan view illustrating a display device according to an exemplary embodiment.

Referring to FIG. 2 , the display device 10 may include a plurality of pixels arranged along a plurality of rows and columns in the display area DA. Each of the plurality of pixels may include a light emitting area LA defined by a pixel defining layer or a bank, and may emit light having a predetermined peak wavelength through the light emitting area LA. For example, the display area DA of the display device 10 may include first to third light emitting areas LA1 , LA2 , and LA3 . Each of the first to third light emitting areas LA1 , LA2 , and LA3 may be an area in which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10 .

The first to third light emitting regions LA1 , LA2 , and LA3 may emit light having a predetermined peak wavelength to the outside of the display device 10 . The first light emitting area LA1 can emit light of a first color, the second light emitting area LA2 can emit light of a second color, and the third light emitting area LA3 can emit light of a third color. can emit light. For example, the first color light may be red light having a peak wavelength ranging from 610 nm to 650 nm, the second color light may be green light having a peak wavelength ranging from 510 nm to 550 nm, and the third color light may be light having a peak wavelength ranging from 510 nm to 550 nm. It may be blue light having a peak wavelength in the range of 440 nm to 480 nm, but is not limited thereto.

The first to third light emitting regions LA1 , LA2 , and LA3 may be sequentially and repeatedly disposed along the first direction (X-axis direction) of the display area DA. For example, the area of the third light emitting region LA3 may be larger than that of the first light emitting region LA1, and the area of the first light emitting region LA1 may be larger than the area of the second light emitting region LA2. there is. For another example, the area of the first light emitting area LA1 , the area of the second light emitting area LA2 , and the area of the third light emitting area LA3 may be substantially the same.

The display area DA of the display device 10 may include a light blocking area BA surrounding the plurality of light emitting areas LA. The light blocking area BA may prevent color mixing of lights emitted from the first to third light emitting areas LA1 , LA2 , and LA3 .

FIG. 3 is a cross-sectional view taken along line II′ of FIG. 2 , FIG. 4 is an enlarged view of area A1 of FIG. 3 , and FIG. 5 is a bottom view of a display device according to an exemplary embodiment.

Referring to FIGS. 3 to 5 , the display area DA of the display device 10 may include first to third light emitting areas LA1 , LA2 , and LA3 . Each of the first to third light emitting areas LA1 , LA2 , and LA3 may be an area in which light generated by the light emitting element ED of the display device 10 is emitted to the outside of the display device 10 .

The display device 10 includes a first substrate SUB1, a first barrier insulating layer BIL1, a first metal layer MTL1, a second barrier insulating layer BIL2, an align key ALK, and a third barrier insulating layer BIL3. , a second substrate SUB2, a display layer DPL, an encapsulation layer TFE, an anti-reflection film ARF, a flexible film FPCB, and a display driver DIC.

The first substrate SUB1 may support the display device 10 . The first substrate SUB1 may be a base substrate or a base member. The first substrate SUB1 may be a flexible substrate capable of being bent, folded, or rolled. For example, the first substrate SUB1 may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the first substrate SUB1 may be a rigid substrate including a glass material.

The first substrate SUB1 may include a first contact hole CNT1. The first contact hole CNT1 may be etched from the lower surface of the first substrate SUB1 to pass through to the upper surface of the first substrate SUB1. For example, the lower width of the first contact hole CNT1 may be greater than the upper width of the first contact hole CNT1. The first contact hole CNT1 may overlap the alignment pattern ALP, the align key ALK, and the pad part PD in the thickness direction (Z-axis direction). The first contact hole CNT1 may expose a lower surface of the first barrier insulating layer BIL1 during the manufacturing process of the display device 10 . The first contact hole CNT1 may be formed for an attachment process of the flexible film FPCB using the align key ALK.

The first barrier insulating layer BIL1 may be disposed on the first substrate SUB1. The first barrier insulating layer BIL1 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the first barrier insulating layer BIL1 may include at least one of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is limited thereto. It doesn't work.

The first barrier insulating layer BIL1 may include a second contact hole CNT2 . The second contact hole CNT2 may be etched from the lower surface of the first barrier insulating layer BIL1 to penetrate the upper surface of the first barrier insulating layer BIL1. The second contact hole CNT2 may expose the lower surface of the pad part PD during the manufacturing process of the display device 10 .

The first metal layer MTL1 may be disposed on the first barrier insulating layer BIL1. The first metal layer MTL1 may include a pad portion PD and an alignment pattern ALP. The pad part PD and the alignment pattern ALP may be formed of the same material on the same layer, but are not limited thereto. For example, the first metal layer MTL1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), or palladium (Pd). , Indium (In), neodymium (Nd), and copper (Cu) may be formed of a single layer or multiple layers including at least one.

The pad part PD may be disposed on the first barrier insulating layer BIL1. The pad part PD may be disposed in the display area DA or may be disposed across the display area DA and the non-display area NDA. The display device 10 may minimize the area of the non-display area NDA by including the pad part PD, at least a portion of which is disposed in the display area DA. The pad part PD may electrically connect the flexible film FPCB and the connection line CWL. The pad part PD may be electrically connected to the flexible film FPCB through the connection film ACF. The pad part PD may be electrically connected to the thin film transistor TFT of the pixel through the connection line CWL. Accordingly, the pad part PD may supply the electric signal received from the flexible film FPCB to the thin film transistor TFT of the pixel through the connection line CWL.

The alignment pattern ALP may be disposed spaced apart from the pad part PD on the first barrier insulating layer BIL1. The alignment pattern ALP may be disposed in the display area DA or may be disposed across the display area DA and the non-display area NDA. The display device 10 may minimize the area of the non-display area NDA by including at least a portion of the alignment pattern ALP disposed in the display area DA. The alignment pattern ALP may have a closed loop shape on a plane. Since the alignment pattern ALP has a closed loop shape, a pattern groove PH surrounded by the alignment pattern ALP and formed in a negative shape may be formed. The alignment pattern ALP may determine the shape of the align key ALK filled in the pattern groove PH.

The second barrier insulating layer BIL2 may be disposed on the first barrier insulating layer BIL1 and the first metal layer MTL1. The second barrier insulating layer BIL2 covering the alignment pattern ALP may form an inner surface of the pattern groove PH. The second barrier insulating layer BIL2 may insulate the alignment pattern ALP and the alignment key ALK. The second barrier insulating layer BIL2 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the second barrier insulating layer BIL2 may include at least one of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is limited thereto. It doesn't work.

The align key ALK may be disposed in the pattern groove PH on the second barrier insulating layer BIL2. The align key ALK may be disposed on a layer between the first metal layer MTL1 and the second substrate SUB2. The align key ALK may be disposed on a layer between the first and second metal layers MTL1 and MTL2 . The align key ALK may be surrounded by an align pattern ALP on a plane. The planar shape of the align key ALK may be determined by the planar shape of the align pattern ALP. The align key ALK may have a '+' shape or a 'T' shape on a plane, but is not limited thereto. For example, the height of the upper surface of the align key ALK may be higher than that of the upper surface of the second barrier insulating layer BIL2 covering the alignment pattern ALP. For another example, the height of the upper surface of the align key ALK may be less than or equal to the height of the upper surface of the second barrier insulating layer BIL2 covering the alignment pattern ALP.

The reflectance of the align key ALK for light of a specific wavelength is determined by the first substrate SUB1, the alignment pattern ALP, the pad part PD, the first to third barrier insulating films BIL1, BIL2, and BIL3, It may be different from reflectance of the second substrate SUB2 and the thin film transistor layer TFTL. The reflectance of the align key ALK for light of a specific wavelength may be different from the reflectance of the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 and the active layer ACTL. Here, light of a specific wavelength may be radiated toward one surface of the align key ALK contacting the pattern groove PH in an alignment process between the flexible film FPCB and the pad part PD. Since the flexible film FPCB is disposed on one surface of the first substrate SUB1 and electrically connected to the pad part PD through the connection film ACF, the camera in the alignment process uses light of a specific wavelength to One side of the key (ALK) can be photographed. The reflectance of the align key (ALK) for light of a specific wavelength is higher or lower than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, MTL4) and the active layer (ACTL) by a certain level, so that the align key ( ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 of the display area DA and the active layer ACTL.

The align key ALK may include an organic material or a metal. When the align key ALK includes an organic material, the align key ALK may include at least one color pigment to have a certain level of reflectance. When the align key ALK includes a plurality of color pigments, reflectance of the align key ALK may be determined by reflectance and specific gravity of each of the color pigments. When the align key ALK includes a metal, the align key ALK may include a metal having a relatively high reflectance or a metal having a relatively low reflectance to have a certain level of reflectivity. When the align key ALK includes a plurality of metals, the reflectance of the align key ALK may be determined by the reflectance and specific gravity of each of the metals.

For example, the reflectance of the align key ALK for light of a specific wavelength is determined by the first substrate SUB1, the alignment pattern ALP, the pad part PD, and the first to third barrier insulating films BIL1 and BIL2. , BIL3), the second substrate SUB2, and the thin film transistor layer TFTL may be higher than reflectance by 0.2 or more. The reflectance of the align key (ALK) for light of a specific wavelength is higher than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, MTL4) and the active layer (ACTL) by 0.2 or more, so that the align key (ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 and the active layer ACTL. When the first to fourth metal layers MTL1, MTL2, MTL3, and MTL4 have a reflectance of 0.5 to 0.6 with respect to light having a wavelength of 550 nm, and the align key ALK has a reflectance of 0.8 or more, the align key ALK may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 . In this case, the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 may include at least one of titanium (Ti) and copper (Cu), and the align key ALK may include aluminum (Al) and silver (Ag) may include at least one, but is not limited thereto.

For another example, the reflectance of the align key ALK for light of a specific wavelength is determined by the first substrate SUB1, the alignment pattern ALP, the pad part PD, the first to third barrier insulating films BIL1, BIL2 and BIL3), the second substrate SUB2, and the thin film transistor layer TFTL may be 0.1 or more lower than reflectance. The reflectance of the align key (ALK) for light of a specific wavelength is lower than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, and MTL4) and the active layer (ACTL) by 0.1 or more, so that the alignment key (ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 and the active layer ACTL. With respect to light having a wavelength of 550 nm, the first to fourth metal layers MTL1, MTL2, MTL3, and MTL4 have a reflectance of 0.5 to 0.6, and the align key ALK has a reflectance of 0.4 or less, so that the align key ALK ) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 . In this case, the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 may include at least one of titanium (Ti) and copper (Cu), and the align key ALK may include gold (Au) and palladium. (Pd), and may include at least one of indium (In), but is not limited thereto.

Therefore, the display device 10 includes an align key ALK that can be easily recognized for light of a specific wavelength, so that the flexible film ( In the FPCB align process, the align key ALK is applied to the first substrate SUB1, the alignment pattern ALP, the pad part PD, the first to third barrier insulating films BIL1, BIL2, BIL3, It is easily distinguished from the second substrate SUB2 and the thin film transistor layer TFTL, and the flexible film FPCB and the pad part PD can be accurately aligned. The display device 10 may secure reliability by improving the recognition rate of the align key ALK.

The third barrier insulating layer BIL3 may be disposed on the align key ALK and the second barrier insulating layer BIL2. The third barrier insulating layer BIL3 may maintain the shape of the align key ALK. The third barrier insulating layer BIL3 may include an inorganic layer capable of preventing penetration of air or moisture. For example, the third barrier insulating layer BIL3 may include at least one of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is limited thereto. It doesn't work.

The second substrate SUB2 may be disposed on the third barrier insulating layer BIL3. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate capable of being bent, folded, or rolled. For example, the second substrate SUB2 may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto.

The second substrate SUB2 and the second and third barrier insulating layers BIL2 and BIL3 may include a third contact hole CNT3. The third contact hole CNT3 may be etched from the upper surface of the second substrate SUB2 to penetrate the lower surface of the second barrier insulating layer BIL2. For example, the upper width of the third contact hole CNT3 may be greater than the lower width of the third contact hole CNT3. During the manufacturing process of the display device 10, the upper surface of the pad part PD may be exposed through the third contact hole CNT3, and the upper surface of the pad part PD may be inserted into the third contact hole CNT3. It may contact the connection wire CWL.

The display layer DPL may be disposed on the second substrate SUB2. The display layer DPL may include a thin film transistor layer TFTL, a light emitting element layer EML, a wavelength conversion layer WLCL, and a color filter layer CFL. The thin film transistor layer TFTL includes a second metal layer MTL2, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a third metal layer MTL3, an interlayer insulating layer ILD, and a fourth metal layer MTL4. , a first passivation layer PV1, and a first planarization layer OC1.

The second metal layer MTL2 may be disposed on the second substrate SUB2. The second metal layer MTL2 may include a light blocking layer BML and a connection line CWL. The light blocking layer BML and the connection line CWL may be formed of the same material on the same layer, but are not limited thereto. For example, the second metal layer MTL2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), or palladium (Pd). , Indium (In), neodymium (Nd), and copper (Cu) may be formed of a single layer or multiple layers including at least one.

The light blocking layer BML may be disposed on the second substrate SUB2. For example, the light blocking layer BML may overlap the thin film transistor TFT in a thickness direction (Z-axis direction) to block external light incident on the thin film transistor TFT. For another example, the light blocking layer BML may include a data line or a power line.

The connection wire CWL may be disposed to be spaced apart from the light blocking layer BML on the second substrate SUB2. The connection wire CWL may be inserted into the third contact hole CNT3 and connected to the pad part PD. For example, the connection line CWL may be connected to a data line to supply a data voltage to the thin film transistor TFT. For another example, the connection line CWL may be connected to a power line to supply a power voltage to the thin film transistor TFT. As another example, the connection line CWL may be connected to a gate line to supply a gate signal to the thin film transistor TFT. Accordingly, the connection line CWL may supply the electric signal received from the pad part PD to the thin film transistor TFT of the pixel.

The buffer layer BF may be disposed on the second metal layer MTL2 and the second substrate SUB2. The buffer layer BF may include an inorganic material capable of preventing penetration of air or moisture. For example, the buffer layer BF may include a plurality of inorganic layers alternately stacked.

The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include the semiconductor region ACT, the drain electrode DE, and the source electrode SE of the thin film transistor TFT. The semiconductor region ACT may overlap the gate electrode GE in a thickness direction (Z-axis direction) and may be insulated from the gate electrode GE by the gate insulating layer GI. The drain electrode DE and the source electrode SE may be provided by making a material of the semiconductor region ACT conductive. The thin film transistor TFT may constitute a pixel circuit of each of a plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of a pixel circuit.

The gate insulating layer GI may be disposed on the active layer ACTL and the buffer layer BF. The gate insulating layer GI may insulate the semiconductor region ACT and the gate electrode GE of the thin film transistor TFT. The gate insulating layer GI may include a contact hole through which each of the first and second connection electrodes CNE1 and CNE2 pass.

The third metal layer MTL3 may be disposed on the gate insulating layer GI. The third metal layer MTL3 may include the gate electrode GE of the thin film transistor TFT. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween. The gate electrode GE may receive a gate signal from the gate line. For example, the third metal layer MTL3 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), or palladium (Pd). , Indium (In), neodymium (Nd), and copper (Cu) may be formed of a single layer or multiple layers including at least one.

An interlayer insulating layer ILD may be disposed on the third metal layer MTL3 . The interlayer insulating layer ILD may insulate the third and fourth metal layers MTL3 and MTL4 . The interlayer insulating layer ILD may include a contact hole through which each of the first and second connection electrodes CNE1 and CNE2 passes.

The fourth metal layer MTL4 may be disposed on the interlayer insulating layer ILD. The fourth metal layer MTL4 may include first and second connection electrodes CNE1 and CNE2 . The first and second connection electrodes CNE1 and CNE2 may be formed of the same material on the same layer, but are not limited thereto. For example, the fourth metal layer MTL4 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), or palladium (Pd). , Indium (In), neodymium (Nd), and copper (Cu) may be formed of a single layer or multiple layers including at least one.

The first connection electrode CNE1 may connect the data line or the power line and the drain electrode DE of the thin film transistor TFT. The first connection electrode CNE1 may contact the drain electrode DE through a contact hole provided in the interlayer insulating layer ILD and the gate insulating layer GI.

The second connection electrode CNE2 may connect the source electrode SE of the thin film transistor TFT and the first electrode RME1. The second connection electrode CNE2 may contact the source electrode SE through a contact hole provided in the interlayer insulating layer ILD and the gate insulating layer GI.

The first passivation layer PV1 may be disposed on the fourth metal layer MTL4 and the interlayer insulating layer ILD. The first protective layer PV1 may protect the thin film transistor TFT. The first passivation layer PV1 may include a contact hole through which the first electrode RME1 passes.

The first planarization layer OC1 is provided on the first passivation layer PV1 to planarize an upper end of the thin film transistor layer TFTL. For example, the first planarization layer OC1 may include a contact hole through which the first electrode RME1 passes. Here, the contact hole of the first planarization layer OC1 may be connected to the contact hole of the first passivation layer PV1. The first planarization layer OC1 may include an organic insulating material such as polyimide (PI).

The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML includes a protrusion pattern BP, a first electrode RME1, a second electrode RME2, a first insulating film PAS1, a sub bank SB, a light emitting element ED, and a second insulating film ( PAS2), a first contact electrode CTE1, a second contact electrode CTE2, and a third insulating layer PAS3.

The protrusion pattern BP may be disposed on the first planarization layer OC1. The protrusion pattern BP may protrude from the upper surface of the first planarization layer OC1. The plurality of protruding patterns BP may be disposed in the light emitting area LA or the opening area of each of the plurality of pixels. The plurality of light emitting devices ED may be disposed between the plurality of protruding patterns BP. The protruding pattern BP may have an inclined side surface, and light emitted from the plurality of light emitting devices ED may be reflected by the first and second electrodes RME1 and RME2 disposed on the protruding pattern BP. can For example, the protrusion pattern BP may include an organic insulating material such as polyimide (PI).

The first electrode RME1 may be disposed on the first planarization layer OC1 and the protrusion pattern BP. The first electrode RME1 may be disposed on the protrusion pattern BP disposed on one side of the plurality of light emitting elements ED. The first electrode RME1 may be disposed on the inclined side of the protruding pattern BP to reflect light emitted from the light emitting element ED. The first electrode RME1 may be inserted into a contact hole provided in the first planarization layer OC1 and the first passivation layer PV1 and connected to the second connection electrode CNE2 . The first electrode RME1 may be electrically connected to one end of the light emitting element ED through the first contact electrode CTE1. For example, the first electrode RME1 may receive a voltage proportional to the luminance of the light emitting element ED from the thin film transistor TFT of the pixel.

The second electrode RME2 may be disposed on the first planarization layer OC1 and the protrusion pattern BP. The second electrode RME2 may be disposed on the protrusion pattern BP disposed on the other side of the plurality of light emitting elements ED. The second electrode RME2 may be disposed on the inclined side of the protruding pattern BP to reflect light emitted from the light emitting element ED. The second electrode RME2 may be electrically connected to the other end of the light emitting element ED through the second contact electrode CTE2. For example, the second electrode RME2 may receive a low potential voltage supplied to all pixels from a low potential line.

The first and second electrodes RME1 and RME2 may include a conductive material having high reflectivity. For example, the first and second electrodes RME1 and RME2 may include at least one of aluminum (Al), silver (Ag), copper (Cu), nickel (Ni), and lanthanum (La). For another example, the first and second electrodes RME1 and RME2 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). For another example, the first and second electrodes RME1 and RME2 include a plurality of layers including a transparent conductive material layer and a metal layer with high reflectivity, or one layer including a transparent conductive material and a metal layer with high reflectivity. can include The first and second electrodes RME1 and RME2 may have a stacked structure of ITO/Ag/ITO/, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The first insulating layer PAS1 may be disposed on the first planarization layer OC1 and the first and second electrodes RME1 and RME2. The first insulating layer PAS1 may insulate the first and second electrodes RME1 and RME2 from each other while protecting them. The first insulating layer PAS1 may prevent damage due to direct contact between the light emitting element ED and the first and second electrodes RME1 and RME2 during the alignment process of the light emitting element ED.

The sub bank SB may be disposed in the light blocking area BA on the first insulating layer PAS1. The sub bank SB is disposed at the boundary of a plurality of pixels to distinguish the light emitting elements ED of each of the plurality of pixels. The sub bank SB may have a predetermined height and may include an organic insulating material such as polyimide (PI).

A plurality of light emitting devices ED may be disposed on the first insulating layer PAS1. The plurality of light emitting devices ED may be aligned in parallel with each other between the first and second electrodes RME1 and RME2. The length of the light emitting element ED may be longer than the length between the first and second electrodes RME1 and RME2. The light emitting device ED may include a plurality of semiconductor layers, and one end and the other end opposite to one end may be defined based on one semiconductor layer. One end of the light emitting element ED may be disposed on the first electrode RME1, and the other end of the light emitting element ED may be disposed on the second electrode RME2. One end of the light emitting element ED may be electrically connected to the first electrode RME1 through the first contact electrode CTE1, and the other end of the light emitting element ED may be electrically connected to the second electrode through the second contact electrode CTE2. (RME2).

The light emitting device ED may have a micrometer or nanometer size and may be an inorganic light emitting diode including an inorganic material. The inorganic light emitting diode may be aligned between the first and second electrodes RME1 and RME2 according to an electric field formed in a specific direction between the first and second electrodes RME1 and RME2 facing each other.

For example, the plurality of light emitting devices ED may include active layers made of the same material and emit light in the same wavelength range or the same color. Light emitted from each of the first to third light emitting regions LA1 , LA2 , and LA3 of the light emitting device layer EML may have the same color. For example, the plurality of light emitting devices ED may emit third color light or blue light having a peak wavelength in the range of 440 nm to 480 nm, but is not limited thereto.

The second insulating layer PAS2 may be disposed on the plurality of light emitting elements ED. For example, the second insulating layer PAS2 may partially cover the plurality of light emitting elements ED and may not cover both ends of each of the plurality of light emitting elements ED. The second insulating layer PAS2 may protect the plurality of light emitting elements ED, and may fix the plurality of light emitting elements ED in the manufacturing process of the display device 10 . The second insulating layer PAS2 may fill a space between the light emitting element ED and the first insulating layer PAS1.

The first contact electrode CTE1 may be disposed on the first insulating layer PAS1 and may be inserted into a contact hole provided in the first insulating layer PAS1 to be connected to the first electrode RME1. For example, the contact hole of the first insulating layer PAS1 may be provided on the protruding pattern BP, but is not limited thereto. One end of the first contact electrode CTE1 may be connected to the first electrode RME1 on the protrusion pattern BP, and the other end of the first contact electrode CTE1 may be connected to one end of the light emitting element ED. .

The second contact electrode CTE2 may be disposed on the first insulating layer PAS1 and may be inserted into a contact hole provided in the first insulating layer PAS1 to be connected to the second electrode RME2. For example, the contact hole of the first insulating layer PAS1 may be provided on the protruding pattern BP, but is not limited thereto. One end of the second contact electrode CTE2 may be connected to the other end of the light emitting element ED, and the other end of the second contact electrode CTE2 may be connected to the second electrode RME2 on the protrusion pattern BP. .

The third insulating layer PAS3 may be disposed on the first and second contact electrodes CTE1 and CTE2, the sub bank SB, and the first and second insulating layers PAS1 and PAS2. The third insulating layer PAS3 may be disposed on top of the light emitting device layer EML to protect the light emitting device layer EML.

The wavelength conversion layer WLCL may be disposed on the light emitting element layer EML. The wavelength conversion layer WLCL includes a first light blocking member BK1 , a first wavelength conversion unit WLC1 , a second wavelength conversion unit WLC2 , a light transmission unit LTU, a second passivation layer PV2 , and a second wavelength conversion unit WLC2 . A planarization layer OC2 may be included.

The first light blocking member BK1 may be disposed in the light blocking area BA on the third insulating layer PAS3. The first light blocking member BK1 may overlap the sub bank SB in the thickness direction (Z-axis direction). The first light blocking member BK1 may block transmission of light. The first light blocking member BK1 may improve color reproducibility of the display device 10 by preventing light from penetrating and mixing colors between the first to third light emitting regions LA1 , LA2 , and LA3 . The first light blocking member BK1 may be disposed in a lattice shape surrounding the first to third light emitting regions LA1 , LA2 , and LA3 on a plane.

The first wavelength converter WLC1 may be disposed in the first emission area LA1 on the third insulating layer PAS3. The first wavelength converter WLC1 may be surrounded by the first light blocking member BK1. The first wavelength converter WLC1 may include a first base resin BS1, a first scatterer SCT1, and a first wavelength shifter WLS1.

The first base resin BS1 may include a material having relatively high light transmittance. The first base resin BS1 may be made of a transparent organic material. For example, the first base resin BS1 may include at least one of organic materials such as an epoxy-based resin, an acrylic-based resin, a cardo-based resin, and an imide-based resin.

The first scattering material SCT1 may have a refractive index different from that of the first base resin BS1 and may form an optical interface with the first base resin BS1. For example, the first scattering material SCT1 may include a light scattering material or a light scattering particle that scatters at least a portion of transmitted light. For example, the first scattering material SCT1 is a metal such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2). It may contain an oxide or organic particles such as an acrylic resin or a urethane resin. The first scattering body SCT1 may scatter light in a random direction regardless of an incident direction of the incident light without substantially converting the peak wavelength of the incident light.

The first wavelength shifter WLS1 may convert or shift the peak wavelength of incident light into a first peak wavelength. For example, the first wavelength shifter WLS1 may convert blue light provided from the display device 10 into red light having a single peak wavelength in a range of 610 nm to 650 nm and emit the red light. The first wavelength shifter WLS1 may be a quantum dot, a quantum rod, or a phosphor. A quantum dot may be a particulate material that emits a specific color while electrons transition from a conduction band to a valence band.

A portion of the blue light provided from the light emitting element layer EML may pass through the first wavelength converter WLC1 without being converted into red light by the first wavelength shifter WLS1. Of the blue light provided from the light emitting element layer EML, light that is not converted by the first wavelength converter WLC1 and incident to the first color filter CF1 may be blocked by the first color filter CF1. Among the blue light provided from the light emitting element layer EML, the red light converted by the first wavelength converter WLC1 may pass through the first color filter CF1 and be emitted to the outside. Accordingly, the first light emitting area LA1 may emit red light.

The second wavelength converter WLC2 may be disposed in the second emission area LA2 on the third insulating layer PAS3. The second wavelength converter WLC2 may be surrounded by the first light blocking member BK1. The second wavelength converter WLC2 may include a second base resin BS2, a second scatterer SCT2, and a second wavelength shifter WLS2.

The second base resin BS2 may include a material having a relatively high light transmittance. The second base resin BS2 may be made of a transparent organic material. For example, the second base resin BS2 may be made of the same material as the first base resin BS1 or a material exemplified in the first base resin BS1.

The second scattering material SCT2 may have a refractive index different from that of the second base resin BS2 and may form an optical interface with the second base resin BS2. For example, the second scattering material SCT2 may include a light scattering material or a light scattering particle that scatters at least a portion of transmitted light. For example, the second scattering object SCT2 may be made of the same material as the first scattering object SCT1 or a material exemplified in the first scattering object SCT1.

The second wavelength shifter WLS2 may convert or shift the peak wavelength of incident light to a second peak wavelength different from the first peak wavelength of the first wavelength shifter WLS1. For example, the second wavelength shifter WLS2 may convert blue light provided from the display device 10 into green light having a single peak wavelength in the range of 510 nm to 550 nm and emit it. The second wavelength shifter WLS2 may be a quantum dot, a quantum rod, or a phosphor. The second wavelength shifter WLS2 may include the material exemplified in the first wavelength shifter WLS1. The wavelength conversion range of the second wavelength shifter WLS2 may be different from that of the first wavelength shifter WLS1 and may be formed of quantum dots, quantum rods, or phosphors.

The light transmitting unit LTU may be disposed in the third light emitting area LA3 on the third insulating layer PAS3. The light transmission unit LTU may be surrounded by the first light blocking member BK1. The light transmitting unit (LTU) may maintain and transmit a peak wavelength of incident light. The light transmitting unit LTU may include a third base resin BS3 and a third scattering material SCT3.

The third base resin BS3 may include a material having a relatively high light transmittance. The third base resin BS3 may be made of a transparent organic material. For example, the third base resin BS3 may be made of the same material as the first or second base resins BS1 and BS2, or may be made of the material exemplified in the first base resin BS1.

The third scattering body SCT3 may have a refractive index different from that of the third base resin BS3 and may form an optical interface with the third base resin BS3. For example, the third scattering material SCT3 may include a light scattering material or a light scattering particle that scatters at least a portion of transmitted light. For example, the third scattering body SCT3 may be made of the same material as the first or second scattering bodies SCT1 and SCT2, or may be made of the same material as the first scattering body SCT1.

Since the wavelength conversion layer WLCL is directly disposed on the third insulating layer PAS3 of the light emitting element layer EML, the display device 10 includes the first and second wavelength conversion units WLC1 and WLC2 and the light transmitting unit LTU. ) may not require a separate substrate. Therefore, the first and second wavelength conversion units WLC1 and WLC2 and the light transmitting unit LTU can be easily aligned with the first to third light emitting regions LA1 , LA2 and LA3 , respectively, and the display device 10 ) can be relatively reduced.

The second passivation layer PV2 may cover the first and second wavelength conversion units WLC1 and WLC2 , the light transmitting unit LTU, and the first light blocking member BK1 . For example, the second passivation layer PV2 seals the first and second wavelength conversion units WLC1 and WLC2 and the light transmission unit LTU to seal the first and second wavelength conversion units WLC1 and WLC2 and the light transmission unit LTU. (LTU) can be prevented from being damaged or contaminated. For example, the second passivation layer PV2 may include an inorganic material.

The second planarization layer OC2 is disposed on the second passivation layer PV2 to planarize upper ends of the first and second wavelength conversion units WLC1 and WLC2 and the light transmitting unit LTU. For example, the second planarization layer OC2 may include an organic insulating material such as polyimide (PI).

The color filter layer (CFL) may be disposed on the wavelength conversion layer (WLCL). The color filter layer CFL may include a second light blocking member BK2 , first to third color filters CF1 , CF2 , and CF3 , and a third passivation layer PV3 .

The second light blocking member BK2 may be disposed in the light blocking area BA on the second planarization layer OC2 of the wavelength conversion layer WLCL. The second light blocking member BK2 may overlap the first light blocking member BK1 or the sub bank SB in a thickness direction (Z-axis direction). The second light blocking member BK2 may block transmission of light. The second light blocking member BK2 may improve color reproducibility of the display device 10 by preventing light from penetrating and mixing colors between the first to third light emitting regions LA1 , LA2 , and LA3 . The second light blocking member BK2 may be disposed in a lattice shape surrounding the first to third light emitting regions LA1 , LA2 , and LA3 on a plane.

The first color filter CF1 may be disposed in the first emission area LA1 on the second planarization layer OC2. The first color filter CF1 may be surrounded by the second light blocking member BK2. The first color filter CF1 may overlap the first wavelength converter WLC1 in a thickness direction (Z-axis direction). The first color filter CF1 selectively transmits light of a first color (eg, red light), and selectively transmits light of a second color (eg, green light) and light of a third color (eg, red light). , blue light) can be blocked or absorbed. For example, the first color filter CF1 may be a red color filter and may include a red colorant.

The second color filter CF2 may be disposed in the second emission area LA2 on the second planarization layer OC2. The second color filter CF2 may be surrounded by the second light blocking member BK2. The second color filter CF2 may overlap the second wavelength converter WLC2 in a thickness direction (Z-axis direction). The second color filter CF2 selectively transmits light of a second color (eg, green light), and selectively transmits light of a first color (eg, red light) and light of a third color (eg, green light). , blue light) can be blocked or absorbed. For example, the second color filter CF2 may be a green color filter and may include a green colorant.

The third color filter CF3 may be disposed in the third emission area LA3 on the second planarization layer OC2. The third color filter CF3 may be surrounded by the second light blocking member BK2. The third color filter CF3 may overlap the light transmission unit LTU in the thickness direction (Z-axis direction). The third color filter CF3 selectively transmits light of a third color (eg, blue light), and transmits light of a first color (eg, red light) and light of a second color (eg, blue light). , green light) can be blocked or absorbed. For example, the third color filter CF3 may be a blue color filter and may include a blue colorant.

The first to third color filters CF1 , CF2 , and CF3 may absorb a portion of light introduced from the outside of the display device 10 to reduce reflected light caused by external light. Accordingly, the first to third color filters CF1 , CF2 , and CF3 may prevent color distortion due to external light reflection.

The first to third color filters CF1 , CF2 , and CF3 are directly disposed on the second planarization layer OC2 of the wavelength conversion layer WLCL, so that the display device 10 has the first to third color filters CF1 , CF2, CF3) may not require a separate substrate. Accordingly, the thickness of the display device 10 may be relatively reduced.

The third passivation layer PV3 may cover the first to third color filters CF1 , CF2 , and CF3 . The third passivation layer PV3 may protect the first to third color filters CF1 , CF2 , and CF3 .

The encapsulation layer TFE may be disposed on the third passivation layer PV3 of the color filter layer CFL. The encapsulation layer TFE may cover the upper and side surfaces of the display layer DPL. For example, the encapsulation layer TFE may include at least one inorganic layer to prevent penetration of oxygen or moisture. In addition, the encapsulation layer TFE may include at least one organic layer to protect the display device 10 from foreign substances such as dust.

The anti-reflection film ARF may be disposed on the encapsulation layer TFE. The anti-reflection film ARF may reduce visibility deterioration due to reflection of external light by preventing reflection of external light. The anti-reflection film ARF may protect the upper surface of the display device 10 . Optionally, the anti-reflection film (ARF) may be omitted. For another example, the anti-reflection film (ARF) may be replaced with a polarizing film.

The flexible film FPCB may be disposed under the first substrate SUB1. The flexible film FPCB may be attached to the lower surface of the first substrate SUB1 using the adhesive member ADM. Optionally, the adhesive member ADM may be omitted. The flexible film FPCB may support the display driver DIC disposed on the other side of the lower surface. One side of the flexible film FPCB may be electrically connected to the pad part PD through the connection film ACF. The other side of the flexible film FPCB may be connected to a source circuit board (not shown) below the first substrate SUB1. The flexible film FPCB may transmit signals of the display driver DIC to the display device 10 .

The display driver DIC may be an integrated circuit (IC). For example, the display driver DIC may convert digital video data into an analog data voltage based on a data control signal of the timing controller and supply the voltage to the data line of the display area DA through the flexible film FPCB. there is. For another example, the display driver DIC may generate a gate signal based on the gate control signal of the timing controller and supply the gate signal to the gate line of the display area DA through the flexible film FPCB. The display device 10 may minimize the area of the non-display area NDA by including the flexible film FPCB and the display driver DIC disposed under the first substrate SUB1.

6 to 14 are cross-sectional views illustrating a manufacturing process of a display device according to an exemplary embodiment.

In FIG. 6 , the first carrier substrate CG1 may support the display device 10 during the manufacturing process of the display device 10 . For example, the first carrier substrate CG1 may be a carrier glass, but is not limited thereto.

The first substrate SUB1 may be disposed on the first carrier substrate CG1. The first substrate SUB1 may be a base substrate or a base member. For example, the first substrate SUB1 may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto.

The first barrier insulating layer BIL1 may be disposed on the first substrate SUB1. The first barrier insulating layer BIL1 may include an inorganic layer capable of preventing penetration of air or moisture.

The first metal layer MTL1 may be disposed on the first barrier insulating layer BIL1. The first metal layer MTL1 may include a pad portion PD and an alignment pattern ALP. The pad part PD and the alignment pattern ALP may be formed of the same material on the same layer, but are not limited thereto. For example, the first metal layer MTL1 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), or palladium (Pd). , Indium (In), neodymium (Nd), and copper (Cu) may be formed of a single layer or multiple layers including at least one.

The pad part PD may be disposed on the first barrier insulating layer BIL1. The pad part PD may be disposed in the display area DA or may be disposed across the display area DA and the non-display area NDA. The display device 10 may minimize the area of the non-display area NDA by including the pad part PD, at least a portion of which is disposed in the display area DA.

The alignment pattern ALP may be disposed spaced apart from the pad part PD on the first barrier insulating layer BIL1. The alignment pattern ALP may be disposed in the display area DA or may be disposed across the display area DA and the non-display area NDA. The display device 10 may minimize the area of the non-display area NDA by including at least a portion of the alignment pattern ALP disposed in the display area DA. The alignment pattern ALP may have a closed loop shape on a plane.

In FIG. 7 , the second barrier insulating layer BIL2 may be disposed on the first barrier insulating layer BIL1 and the first metal layer MTL1. The second barrier insulating layer BIL2 covering the alignment pattern ALP may form an inner surface of the pattern groove PH. The second barrier insulating layer BIL2 may include an inorganic layer capable of preventing penetration of air or moisture.

The key forming material ALKM may be disposed on the second barrier insulating layer BIL2. The key forming material ALKM may be filled in the pattern groove PH surrounded by the alignment pattern ALP and the second barrier insulating layer BIL2. The key forming material ALKM may include an organic material or a metal. When the key forming material (ALKM) includes an organic material, the key forming material (ALKM) may include at least one colored pigment to have a certain level of reflectance. When the key forming material ALKM includes a plurality of colored pigments, reflectance of the key forming material ALKM may be determined by reflectance and specific gravity of each of the colored pigments. When the key forming material ALKM includes a metal, the key forming material ALKM may include a metal having a relatively high reflectance or a metal having a relatively low reflectance to have a certain level of reflectance. When the key forming material ALKM includes a plurality of metals, the reflectance of the key forming material ALKM may be determined by reflectance and specific gravity of each of the metals.

In FIG. 8 , the align key ALK may be formed by patterning the key forming material ALKM. The align key ALK may be surrounded by an align pattern ALP on a plane. The planar shape of the align key ALK may be determined by the planar shape of the align pattern ALP. The align key ALK may have a '+' shape or a 'T' shape on a plane, but is not limited thereto.

In FIG. 9 , the third barrier insulating layer BIL3 may be disposed on the align key ALK and the second barrier insulating layer BIL2. The third barrier insulating layer BIL3 may maintain the shape of the align key ALK. The third barrier insulating layer BIL3 may include an inorganic layer capable of preventing penetration of air or moisture.

The second substrate SUB2 may be disposed on the third barrier insulating layer BIL3. The second substrate SUB2 may be a base substrate or a base member. The second substrate SUB2 may be a flexible substrate capable of being bent, folded, or rolled. For example, the second substrate SUB2 may include an insulating material such as a polymer resin such as polyimide (PI), but is not limited thereto.

The second substrate SUB2 and the second and third barrier insulating layers BIL2 and BIL3 may include a third contact hole CNT3. The third contact hole CNT3 may be etched from the upper surface of the second substrate SUB2 to penetrate the lower surface of the second barrier insulating layer BIL2. For example, the upper width of the third contact hole CNT3 may be greater than the lower width of the third contact hole CNT3. An upper surface of the pad part PD may be exposed through the third contact hole CNT3.

In FIG. 10 , the display layer DPL may be stacked on the second substrate SUB2. The thin film transistor layer TFTL, the light emitting element layer EML, the wavelength conversion layer WLCL, and the color filter layer CFL may be sequentially stacked on the second substrate SUB2. The encapsulation layer TFE may cover the upper and side surfaces of the display layer DPL. The anti-reflection film ARF may be formed on the encapsulation layer TFE.

11 and 12 , the display device 10 under manufacture may be inverted vertically to form a flexible film (FPCB). The first carrier substrate CG1 may be removed from the first substrate SUB1. For example, the first carrier substrate CG1 may be removed from the lower surface of the first substrate SUB1 using a sacrificial layer (not shown) disposed between the first carrier substrate CG1 and the first substrate SUB1. may, but is not limited thereto.

The second carrier substrate CG2 may be disposed on one surface of the anti-reflection film ARF. The second carrier substrate CG2 may support the vertically inverted display device 10 . For example, the second carrier substrate CG2 may be a carrier glass, but is not limited thereto.

One surface of the first substrate SUB1 may perform at least one process of a dry etching process, a plasma etching process, and a laser etching process. For example, one surface of the first substrate SUB1 may be patterned through a plasma etching process using atmospheric pressure plasma (AP Plasma). Therefore, the first contact hole CNT1 may be provided in the first substrate SUB1 and overlap the pad part PD, the alignment pattern ALP, and the alignment key ALK. BIL1) can be exposed.

12 and 13, at least one of a dry etching process, a plasma etching process, and a laser etching process may be performed on one surface of the first barrier insulating film BIL1. there is. For example, one surface of the first barrier insulating layer BIL1 may be patterned through a plasma etching process using atmospheric pressure plasma (AP Plasma). Accordingly, the second contact hole CNT2 may be provided in the first barrier insulating layer BIL1 and may expose the pad part PD.

13 and 14 , the flexible film FPCB may be disposed on one surface of the first substrate SUB1 through an alignment process using light of a specific wavelength. Light of a specific wavelength may be radiated toward one surface of the align key ALK contacting the pattern groove PH in an alignment process between the flexible film FPCB and the pad part PD. Since the flexible film FPCB is disposed on one surface of the first substrate SUB1 and electrically connected to the pad part PD through the connection film ACF, the camera CAM in the alignment process uses light of a specific wavelength. Thus, one side of the align key (ALK) can be photographed. The reflectance of the align key (ALK) for light of a specific wavelength is determined by the first substrate (SUB1), the alignment pattern (ALP), the first to third barrier insulating films (BIL1, BIL2, BIL3), and the second substrate (SUB2). , and reflectance of the thin film transistor layer (TFTL). The reflectance of the align key (ALK) for light of a specific wavelength is higher or lower than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, MTL4) and the active layer (ACTL) by a certain level, so that the align key ( ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 of the display area DA and the active layer ACTL.

For example, the reflectance of the align key ALK for light of a specific wavelength is determined by the first substrate SUB1, the alignment pattern ALP, the pad part PD, and the first to third barrier insulating films BIL1 and BIL2. , BIL3), the second substrate SUB2, and the thin film transistor layer TFTL may be higher than reflectance by 0.2 or more. The reflectance of the align key (ALK) for light of a specific wavelength is higher than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, MTL4) and the active layer (ACTL) by 0.2 or more, so that the align key (ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 and the active layer ACTL. When the first to fourth metal layers MTL1, MTL2, MTL3, and MTL4 have a reflectance of 0.5 to 0.6 with respect to light having a wavelength of 550 nm, and the align key ALK has a reflectance of 0.8 or more, the align key ALK may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 . In this case, the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 may include at least one of titanium (Ti) and copper (Cu), and the align key ALK may include aluminum (Al) and silver (Ag) may include at least one, but is not limited thereto.

For another example, the reflectance of the align key ALK for light of a specific wavelength is determined by the first substrate SUB1, the alignment pattern ALP, the pad part PD, the first to third barrier insulating films BIL1, BIL2 and BIL3), the second substrate SUB2, and the thin film transistor layer TFTL may be 0.1 or more lower than reflectance. The reflectance of the align key (ALK) for light of a specific wavelength is lower than the reflectance of the first to fourth metal layers (MTL1, MTL2, MTL3, and MTL4) and the active layer (ACTL) by 0.1 or more, so that the alignment key (ALK) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 and the active layer ACTL. With respect to light having a wavelength of 550 nm, the first to fourth metal layers MTL1, MTL2, MTL3, and MTL4 have a reflectance of 0.5 to 0.6, and the align key ALK has a reflectance of 0.4 or less, so that the align key ALK ) may be distinguished from the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 . In this case, the first to fourth metal layers MTL1 , MTL2 , MTL3 , and MTL4 may include at least one of titanium (Ti) and copper (Cu), and the align key ALK may include gold (Au) and palladium. (Pd), and may include at least one of indium (In), but is not limited thereto.

The flexible film FPCB may be attached to one surface of the first substrate SUB1 by using an adhesive member ADM. Optionally, the adhesive member ADM may be omitted. The flexible film FPCB may support the display driver DIC. One side of the flexible film FPCB may be electrically connected to the pad part PD through the connection film ACF. The other side of the flexible film FPCB may be connected to a source circuit board (not shown) below the first substrate SUB1. The flexible film FPCB may transmit signals of the display driver DIC to the display device 10 .

Therefore, the display device 10 includes an align key ALK that can be easily recognized for light of a specific wavelength, so that the flexible film ( In the FPCB align process, the align key ALK is applied to the first substrate SUB1, the alignment pattern ALP, the pad part PD, the first to third barrier insulating films BIL1, BIL2, BIL3, It is easily distinguished from the second substrate SUB2 and the thin film transistor layer TFTL, and the flexible film FPCB and the pad part PD can be accurately aligned. The display device 10 may secure reliability by improving the recognition rate of the align key ALK.

15 is a plan view illustrating a coupling structure of a tile-type display device according to an exemplary embodiment, and FIG. 16 is a cross-sectional view taken along line II-II′ of FIG. 15 .

Referring to FIGS. 15 and 16 , the tile-type display device TD may include a plurality of display devices 10 , a coupling member 20 , and a cover member 30 . The plurality of display devices 10 may be arranged in a lattice shape, but is not limited thereto. The plurality of display devices 10 may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the tile-type display device TD may have a specific shape. For example, each of the plurality of display devices 10 may have the same size, but is not limited thereto. For another example, the plurality of display devices 10 may have different sizes.

The tile-type display device TD may include first to fourth display devices 10-1 to 10-4. The number and coupling relationship of the display device 10 is not limited to the embodiment of FIG. 15 . The number of display devices 10 may be determined according to the size of each of the display device 10 and the tile type display device TD. For example, the tile-type display device TD may include the display device 10 shown in FIG. 3 .

The display device 10 may include a display area DA and a non-display area NDA. The display area DA may display an image by including a plurality of pixels. The non-display area NDA may be disposed around the display area DA to surround the display area DA and may not display an image.

The tile-type display device TD may include a coupling area SM disposed between the plurality of display areas DA. The tile-type display device TD may be formed by connecting non-display areas NDAs of adjacent display devices 10 to each other. The plurality of display devices 10 may be connected to each other through a coupling member 20 or an adhesive member disposed in the coupling area SM. The coupling area SM of each of the plurality of display devices 10 may not include a pad portion or a flexible film attached to the pad portion. Accordingly, the distance between the display areas DA of each of the plurality of display devices 10 may be close enough that the coupling area SM between the plurality of display devices 10 is not recognized by the user. In addition, the external light reflectance of the display area DA of each of the plurality of display devices 10 and the external light reflectance of the coupling area SM between the plurality of display devices 10 may be substantially the same. Therefore, the tile-type display device TD prevents the user from perceiving the coupling area SM between the plurality of display devices 10, thereby improving the sense of disconnection between the plurality of display devices 10 and improving the immersion of the image. can improve.

The display device 10 may include a plurality of pixels arranged along a plurality of rows and columns in the display area DA. Each of the plurality of pixels may include a light emitting area LA defined by a pixel defining layer or a bank, and may emit light having a predetermined peak wavelength through the light emitting area LA. For example, the display area DA of the display device 10 may include first to third light emitting areas LA1 , LA2 , and LA3 . Each of the first to third light emitting areas LA1 , LA2 , and LA3 may be an area in which light generated by a light emitting element of the display device 10 is emitted to the outside of the display device 10 .

The first to third light emitting regions LA1 , LA2 , and LA3 may be sequentially and repeatedly disposed along the first direction (X-axis direction) of the display area DA. For example, the area of the third light emitting region LA3 may be larger than that of the first light emitting region LA1, and the area of the first light emitting region LA1 may be larger than the area of the second light emitting region LA2. there is. For another example, the area of the first light emitting area LA1 , the area of the second light emitting area LA2 , and the area of the third light emitting area LA3 may be substantially the same.

The display area DA of the display device 10 may include a light blocking area BA surrounding the plurality of light emitting areas LA. The light blocking area BA may prevent color mixing of lights emitted from the first to third light emitting areas LA1 , LA2 , and LA3 .

In the tile-type display device TD, side surfaces of adjacent display devices 10 may be coupled to each other using coupling members 20 disposed between the plurality of display devices 10 . The coupling member 20 may implement a tile-type display device TD by connecting side surfaces of the first to fourth display devices 10 - 1 to 10 - 4 arranged in a lattice shape. The coupling member 20 may include a side surface of the first substrate SUB1 of the display devices 10 adjacent to each other, a side surface of the first to third barrier insulating films BIL1 , BIL2 , and BIL3 , a side surface of the second substrate SUB2 , The side surface of the display layer DPL, the side surface of the encapsulation layer TFE, and the side surface of the anti-reflection film ARF may be combined.

For example, the coupling member 20 may be formed of an adhesive or a double-sided tape having a relatively thin thickness, thereby minimizing a gap between the plurality of display devices 10 . For another example, the coupling member 20 may be formed of a coupling frame having a relatively thin thickness, thereby minimizing the distance between the plurality of display devices 10 . Accordingly, the tile-type display device TD can prevent the user from perceiving the coupling area SM between the plurality of display devices 10 .

The cover member 30 may be disposed on upper surfaces of the plurality of display devices 10 and the coupling member 20 to cover the plurality of display devices 10 and the coupling member 20 . For example, the cover member 30 may be disposed on an upper surface of the anti-reflection film ARF of each of the plurality of display devices 10 . The cover member 30 may protect the upper surface of the tile-type display device TD.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. you will be able to understand Therefore, the embodiments described above should be understood as illustrative in all respects and not limiting.

TD: tiled display
10: display device 20: coupling member
30: cover member SUB1: first substrate
BIL1, BIL2, BIL3: first to third barrier insulating films
ALP: Align Pattern ALK: Align Key
PD: pad part SUB2: second substrate
CWL: connection wiring DPL: display layer
TFTL: thin film transistor layer EML: light emitting element layer
WLCL: wavelength conversion layer CFL: color filter layer
TFE: encapsulation layer ARF: antireflection film
FPCB: flexible film DIC: display driving unit

Claims (20)

a first substrate including a first contact hole;
a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction;
an alignment pattern disposed on the same layer as the pad part;
an align key disposed on the align pattern and surrounded by the align pattern on a plane;
a thin film transistor layer disposed on the align key; and
a flexible film disposed on a lower surface of the first substrate and electrically connected to the pad part through the first contact hole;
The reflectance of the align key for light of a specific wavelength is different from the reflectance of the alignment pattern, the pad part, and the thin film transistor layer. According to claim 1,
The alignment pattern has a closed loop shape on a plane to form a pattern groove formed in a negative shape,
The display device of claim 1 , wherein the align key fills the pattern groove. According to claim 2,
and a barrier insulating layer insulating the align key from the align pattern and forming an inner surface of the pattern groove. According to claim 1,
The display device of claim 1 , wherein a reflectance of the align key for light of the specific wavelength is higher than reflectances of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or 0.1 or more. According to claim 1,
The display device of claim 1 , wherein the align key includes an organic material including a colored pigment or a metal. According to claim 1,
a second substrate disposed on a layer between the align key and the thin film transistor layer;
The align key is disposed on a layer between the align pattern and the second substrate. According to claim 1,
The thin film transistor layer,
connection wires connected to the pad portion;
a light blocking layer disposed on the same layer as the connection wiring; and
A thin film transistor disposed on the connection wiring and the light blocking layer and electrically connected to the connection wiring;
The reflectance of the align key for the light of the specific wavelength is 0.2 or more higher than the reflectance of the connection wiring and the light blocking layer, or is 0.1 or more lower than the display device. According to claim 7,
The thin film transistor,
an active layer, a drain electrode, and a source electrode disposed on the light blocking layer; and
A gate electrode disposed on the active layer and insulated from the active layer;
A reflectance of the align key for light of the specific wavelength is higher than reflectances of the active layer, the drain electrode, the source electrode, and the gate electrode by 0.2 or more or 0.1 or more lower than reflectances of the active layer, the drain electrode, the source electrode, and the gate electrode. According to claim 8,
Further comprising a light emitting element layer disposed on the thin film transistor layer and including a light emitting element,
The thin film transistor layer further includes a connection electrode disposed on the gate electrode to connect the thin film transistor and the light emitting element,
The reflectance of the align key for the light of the specific wavelength is 0.2 or more higher than the reflectance of the connection electrode, or 0.1 or more lower than the display device. a first substrate including a first contact hole;
a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction;
an alignment pattern disposed on the same layer as the pad part;
an align key disposed on the align pattern and surrounded by the align pattern on a plane;
a second substrate disposed on the align key;
a thin film transistor layer disposed on the second substrate; and
and a flexible film disposed on a lower surface of the first substrate and electrically connected to the pad part through the first contact hole. According to claim 10,
The display device of claim 1 , wherein a reflectance of the align key for light of the specific wavelength is higher than reflectances of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or 0.1 or more. According to claim 10,
The alignment pattern has a closed loop shape on a plane to form a pattern groove formed in a negative shape,
The display device of claim 1 , wherein the align key fills the pattern groove. According to claim 12,
and a barrier insulating layer insulating the align key from the align pattern and forming an inner surface of the pattern groove. preparing a first substrate;
forming a pad part and an alignment pattern disposed on the first substrate;
forming an align key disposed on the align pattern and surrounded by the align pattern on a plane;
forming a thin film transistor layer disposed on the align key;
patterning the first substrate to form a first contact hole overlapping the pad portion;
aligning the flexible film to the pad portion by irradiating light of a specific wavelength toward one surface of the align key facing the first substrate; and
and electrically connecting the flexible film to the pad part. According to claim 14,
The forming of the alignment pattern includes forming a pattern groove formed in a negative shape by forming an alignment pattern having a closed loop shape on a plane. According to claim 14,
The method of manufacturing the display device further comprising forming a barrier insulating layer directly covering the pad portion and the alignment pattern. According to claim 14,
The reflectance of the align key for the light of the specific wavelength is higher than reflectance of the alignment pattern, the pad part, and the thin film transistor layer by 0.2 or more or is lower than 0.1 or more of the display device. According to claim 14,
The method of manufacturing the display device further comprising forming a second substrate disposed on the align key. According to claim 14,
Forming the thin film transistor layer,
forming a connection wire disposed on the align key and connected to the pad part;
forming a light blocking layer disposed on the same layer as the connection wiring;
Forming a thin film transistor disposed on the connection wiring and the light blocking layer and electrically connected to the connection wiring,
The reflectance of the align key for light of the specific wavelength is 0.2 or more higher or 0.1 or more lower than reflectances of the connection wiring, the light blocking layer, and the thin film transistor. a plurality of display devices including a display area including a plurality of pixels and a non-display area surrounding the display area; and
a coupling member coupling the plurality of display devices;
Each of the plurality of display devices,
a first substrate including a first contact hole;
a pad portion disposed on the first substrate and overlapping the first contact hole in a thickness direction;
an alignment pattern disposed on the same layer as the pad part;
an align key disposed on the align pattern and surrounded by the align pattern on a plane;
a thin film transistor layer disposed on the align key; and
a flexible film disposed on a lower surface of the first substrate and electrically connected to the pad part through the first contact hole;
The tile type display device of claim 1 , wherein a reflectance of the align key to light of a specific wavelength is different from reflectances of the alignment pattern, the pad part, and the thin film transistor layer.

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