KR20220056023A - Integrated circuit device and electronic system having the same - Google Patents

Abstract

An integrated circuit device according to the technical concept of the present invention comprises: a semiconductor substrate; a bonding insulating layer arranged on the semiconductor substrate; a first gate stack extending in a first direction and a second direction which are parallel to the main surface of the semiconductor substrate and intersect with each other on the bonding insulating layer and including a plurality of first gate electrodes and a plurality of first insulating layers which are alternately stacked along a third direction perpendicular to the main surface; a second gate stack extending in the first direction and the second direction on the first gate stack and including a plurality of second gate electrodes and a plurality of second insulating layers which are alternately stacked along the third direction; a lower channel hole extending through the bonding insulating layer in the third direction; a first channel hole extending to be arranged on the lower channel hole by passing through the first gate stack in the third direction; a second channel hole extending to be arranged on the first channel hole by passing through the second gate stack in the third direction; and a channel structure for filling the lower channel hole, the first channel hole, and the second channel hole, wherein the lower channel hole and the second channel hole have a larger width as the lower channel hole and the second channel hole are away from the semiconductor substrate in the third direction, and the first channel hole has a smaller width as the first channel hole is away from the semiconductor substrate in the third direction. According to the present invention, a first channel hole is formed in some gate stacks and a second channel hole is formed in the remaining gate stack so that the manufacturing cost can be reduced.

Description

INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME

The technical field of the present invention relates to an integrated circuit device and an electronic system including the same, and more particularly, to an integrated circuit device including a nonvolatile vertical memory device and an electronic system including the same.

In order to satisfy excellent performance and economy, it is required to increase the degree of integration of integrated circuit devices. In particular, the degree of integration of a memory device is an important factor determining the economic feasibility of a product. Since the degree of integration of a two-dimensional memory device is mainly determined by an area occupied by a unit memory cell, it is greatly affected by the level of a fine pattern forming technique. However, expensive equipment is required to form a fine pattern and the area of a chip die is limited, so although the degree of integration of the 2D memory device is increasing, it is still limited. Accordingly, there is a demand for a vertical type memory device having a three-dimensional structure.

The problem to be solved by the technical idea of the present invention is an integrated circuit device manufactured by forming a first channel hole in some gate stacks in a vertical memory device and forming a second channel hole in the remaining gate stacks in the opposite direction and to provide an electronic system including the same.

The problems to be solved by the technical spirit of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An integrated circuit device according to the technical concept of the present invention, a semiconductor substrate; a bonding insulating layer disposed on the semiconductor substrate; a plurality of first gate electrodes extending in first and second directions parallel to and intersecting with each other on the main surface of the semiconductor substrate on the bonding insulating layer and alternately stacked along a third direction perpendicular to the main surface; a first gate stack comprising a plurality of first insulating layers; a second gate on the first gate stack, including a plurality of second gate electrodes and a plurality of second insulating layers extending in the first direction and the second direction and alternately stacked in the third direction stack; a lower channel hole extending through the bonding insulating layer in the third direction; a first channel hole passing through the first gate stack in the third direction and extending to be disposed on the lower channel hole; a second channel hole passing through the second gate stack in the third direction and extending to be disposed on the first channel hole; and a channel structure filling the lower channel hole, the first channel hole, and the second channel hole, wherein the lower channel hole and the second channel hole are further away from the semiconductor substrate in the third direction. The width of the first channel hole becomes larger, and the width of the first channel hole becomes smaller as it moves away from the semiconductor substrate in the third direction.

An electronic system according to a technical concept of the present invention includes: a main board; an integrated circuit device on the main board; and a controller electrically connected to the integrated circuit device on the main board, wherein the integrated circuit device includes: a semiconductor substrate; a bonding insulating layer disposed on the semiconductor substrate; a plurality of first gate electrodes extending in first and second directions parallel to and intersecting with each other on the main surface of the semiconductor substrate on the bonding insulating layer and alternately stacked along a third direction perpendicular to the main surface; a first gate stack comprising a plurality of first insulating layers; a second gate on the first gate stack, including a plurality of second gate electrodes and a plurality of second insulating layers extending in the first direction and the second direction and alternately stacked in the third direction stack; a lower channel hole extending through the bonding insulating layer in the third direction; a first channel hole passing through the first gate stack in the third direction and extending to be disposed on the lower channel hole; a second channel hole passing through the second gate stack in the third direction and extending to be disposed on the first channel hole; and a channel structure filling the lower channel hole, the first channel hole, and the second channel hole, wherein the lower channel hole and the second channel hole are further away from the semiconductor substrate in the third direction. The width of the first channel hole becomes larger, and the width of the first channel hole becomes smaller as it moves away from the semiconductor substrate in the third direction.

The integrated circuit device according to the technical idea of the present invention is manufactured by a process of forming a first channel hole in some gate stacks in a vertical memory device and forming a second channel hole in the remaining gate stacks in the opposite direction, and manufacturing cost can have the effect of reducing

1 is a block diagram illustrating an integrated circuit device according to an embodiment of the technical idea of the present invention.
2 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept.
3A is a cross-sectional view showing components of an integrated circuit device according to an embodiment of the inventive concept, FIG. 3B is an enlarged view showing a portion BB of FIG. 3A, and FIG. am.
4 to 10 are cross-sectional views illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept according to a process sequence.
11 is a diagram illustrating an electronic system including an integrated circuit device according to an embodiment of the inventive concept.
12 is a perspective view illustrating an electronic system including an integrated circuit device according to an embodiment of the inventive concept.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an integrated circuit device according to an embodiment of the technical idea of the present invention.

Referring to FIG. 1 , the integrated circuit device 10 may include a memory cell array 20 and a peripheral circuit 30 .

The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, ..., BLKn. Each of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn may include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, ..., BLKn are connected to the peripheral circuit 30 through a bit line BL, a word line WL, a string select line SSL, and a ground select line GSL. can be connected

The memory cell array 20 may be connected to the page buffer 34 through a bit line BL, and a row decoder (GSL) through a word line WL, a string select line SSL, and a ground select line GSL. 32) can be connected. In the memory cell array 20 , each of the plurality of memory cells included in the plurality of memory cell blocks BLK1 , BLK2 , ..., BLKn may be a flash memory cell. The memory cell array 20 may include a three-dimensional memory cell array. The 3D memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells connected to a plurality of vertically stacked word lines WL.

The peripheral circuit 30 may include a row decoder 32 , a page buffer 34 , a data input/output circuit 36 , and a control logic 38 . Although not shown, the peripheral circuit 30 includes a voltage generation circuit for generating various voltages necessary for the operation of the integrated circuit device 10 , and an error correction circuit for correcting an error in data read from the memory cell array 20 . , and may further include various circuits such as an input/output interface.

The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the integrated circuit element 10 , and communicate with a device external to the integrated circuit element 10 . Data DATA may be transmitted/received.

The configuration of the peripheral circuit 30 will be described in detail as follows.

The row decoder 32 may select at least one of the plurality of memory cell blocks BLK1, BLK2, ..., BLKn in response to an address ADDR from the outside, and a word line WL and a string of the selected memory cell block. A selection line SSL and a ground selection line GSL may be selected. The row decoder 32 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

The page buffer 34 may be connected to the memory cell array 20 through the bit line BL. The page buffer 34 operates as a write driver during a program operation to apply a voltage according to data DATA to be stored in the memory cell array 20 to the bit line BL, and detects it during a read operation. It operates as an amplifier to sense data DATA stored in the memory cell array 20 . The page buffer 34 may operate according to a control signal PCTL provided from the control logic 38 .

The data input/output circuit 36 may be connected to the page buffer 34 through data lines DLs. The data input/output circuit 36 receives data DATA from a memory controller (not shown) during a program operation, and stores the program data DATA into a page buffer based on the column address C_ADDR provided from the control logic 38 . (34) can be provided. The data input/output circuit 36 may provide the read data DATA stored in the page buffer 34 to the memory controller based on the column address C_ADDR provided from the control logic 38 during a read operation. The data input/output circuit 36 may transmit an input address or command to the control logic 38 or the row decoder 32 .

The control logic 38 may receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 may provide a row address R_ADDR to the row decoder 32 and provide a column address C_ADDR to the data input/output circuit 36 . The control logic 38 may generate various internal control signals used in the integrated circuit device 10 in response to the control signal CTRL. For example, the control logic 38 may adjust the voltage level provided to the word line WL and the bit line BL when a memory operation such as a program operation or an erase operation is performed.

2 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept.

Referring to FIG. 2 , an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure is illustrated.

The memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA includes a plurality of bit lines BL, a plurality of word lines WL, at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. ) may be included.

A plurality of memory cell strings MS may be formed between the plurality of bit lines BL and the common source line CSL. Although the drawing illustrates a case in which each of the plurality of memory cell strings MS includes two string selection lines SSL, the technical spirit of the present invention is not limited thereto. For example, each of the plurality of memory cell strings MS may include one string selection line SSL.

Each of the plurality of memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, MCn. A drain region of the string select transistor SST may be connected to the bit line BL, and a source region of the ground select transistor GST may be connected to a common source line CSL. The common source line CSL may be a region in which the source regions of the plurality of ground selection transistors GST are commonly connected.

The string select transistor SST may be connected to the string select line SSL, and the ground select transistor GST may be connected to the ground select line GSL. The plurality of memory cell transistors MC1 , MC2 , ..., MCn-1 , MCn may be respectively connected to a plurality of word lines WL.

3A is a cross-sectional view illustrating components of an integrated circuit device according to an embodiment of the inventive concept, FIG. 3B is an enlarged view illustrating a portion BB of FIG. 3A, and FIG. am.

3A to 3C , the integrated circuit device 100 may include a semiconductor substrate 101 , a bonding insulating layer 110 , a gate stack GS, and a channel structure 160 .

The semiconductor substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon (Si) or germanium (Ge). The semiconductor substrate 101 may be provided as a bulk wafer or a wafer on which an epitaxial layer is formed. In other embodiments, the semiconductor substrate 101 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GeOI) substrate.

The bonding insulating layer 110 may be disposed on the semiconductor substrate 101 . In some embodiments, the bonding insulating layer 110 may be formed of an oxide-based material such as silicon oxide. The bonding insulating layer 110 may serve to bond the semiconductor substrate 101 to the gate stack GS.

The gate stack GS may extend on the bonding insulating layer 110 in a first direction (X direction) and a second direction (Y direction) parallel to the top surface of the bonding insulating layer 110 . The gate stack GS may include a lower first gate stack GS1 and an upper second gate stack GS2. The first gate stack GS1 and the second gate stack GS2 may meet at a gate boundary surface GSM.

The first gate stack GS1 may include a plurality of first gate electrodes 130 and a plurality of first insulating layers 140 , and a plurality of first gate electrodes 130 and a plurality of first insulating layers ( 140 may be alternately disposed along a third direction (Z direction) perpendicular to the upper surface of the bonding insulating layer 110 . In addition, a first oxide layer 120 may be included in the lowermost portion of the first gate stack GS1 . In some embodiments, the first oxide layer 120 may be a partial layer of the plurality of first insulating layers 140 .

The second gate stack GS2 may include a plurality of second gate electrodes 230 and a plurality of second insulating layers 240 , and include a plurality of second gate electrodes 230 and a plurality of second insulating layers ( 240 may be alternately disposed on the first gate stack GS1 in the third direction (Z direction). In addition, a second oxide layer 220 may be provided on an uppermost portion of the second gate stack GS2 . In some embodiments, the second oxide layer 220 may be a partial layer of the plurality of second insulating layers 240 .

The first gate electrode 130 and the second gate electrode 230 may include a buried conductive layer and an insulating liner surrounding the buried conductive layer, respectively. The buried conductive layer may include, for example, a metal such as tungsten, nickel, cobalt, tantalum, etc., a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, doped polysilicon, or a combination thereof. . The insulating liner may include, for example, a high-k material such as aluminum oxide. In some embodiments, a conductive barrier layer surrounding the top and side surfaces of the buried conductive layer may be further formed. The conductive barrier layer may include, for example, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

The plurality of first and second gate electrodes 130 and 230 select the ground selection line GSL, the word line WL, and at least one string constituting the memory cell string MS described with reference to FIG. 2 above. It may correspond to the line SSL. For example, the lowermost first gate electrode 130 functions as the ground selection line GSL, the uppermost second gate electrode 230 functions as the string select line SSL, and the remaining first and second The gate electrodes 130 and 230 may function as a word line WL. Accordingly, the memory cell string MS in which the ground selection transistor GST, the selection transistor SST, and the memory cell transistors MC1, MC2, ..., MCn-1, MCn therebetween are connected in series may be provided. In some embodiments, at least one of the plurality of first and second gate electrodes 130 and 230 may function as a dummy word line, but is not limited thereto.

The uppermost second gate electrode 230 may be planarly separated into two parts by a string separation insulating layer (not shown). The two parts may constitute the string selection line SSL described above with reference to FIG. 2 .

The plurality of channel holes 160H may include a lower channel hole 160HL, a first channel hole 160H1, and a second channel hole 160H2, respectively. Specifically, the lower channel hole 160HL extends through the bonding insulating layer 110 in the third direction (Z direction), and the first channel hole 160H1 connects the first gate stack GS1 to the third The second channel hole 160H2 penetrates through the second gate stack GS2 in the third direction (Z direction) and extends to be disposed on the lower channel hole 160HL. It extends to be disposed on the first channel hole 160H1.

Here, the lower channel hole 160HL and the second channel hole 160H2 have a greater width as they move away from the semiconductor substrate 101 in the third direction (Z direction), and the first channel hole 160H1 . The width of n may become smaller as it moves away from the semiconductor substrate 101 in the third direction (Z direction). In other words, as the distance from the first boundary M1 where the first channel hole 160H1 and the second channel hole 160H2 meet is increased, the first width W1 of the first boundary M1 is greater than the first width W1. The width 160W1 of the channel hole 160H1 and the width 160W2 of the second channel hole 160H2 gradually increase. In addition, as the distance from the second boundary M2 where the first channel hole 160H1 and the lower channel hole 160HL meet is increased, the first channel hole is larger than the second width W2 of the second boundary M2. The width 160W1 of 160H1 and the width 160WL of the lower channel hole 160HL gradually decrease.

That is, the lower channel hole 160HL, the first channel hole 160H1, and the second channel hole 160H2 may each have tapered sidewalls, and the channel hole 160H has different inclinations. The inclined sidewalls may have a continuous structure.

The structure of the channel hole 160H may be formed according to the method of manufacturing the integrated circuit device 100 of the present invention. A method of manufacturing the integrated circuit device 100 of the present invention will be described later.

A plurality of channel structures 160 may be formed in the plurality of channel holes 160H. The plurality of channel structures 160 may extend in a third direction (Z direction) from the top surface 101S of the semiconductor substrate 101 through the first and second gate electrodes 130 and 230 . The plurality of channel structures 160 may be arranged to be spaced apart from each other at predetermined intervals in the first direction (X direction) and the second direction (Y direction).

Each of the plurality of channel structures 160 may include a gate insulating layer 162 , a channel layer 164 , a buried insulating layer 166 , and a conductive plug 168 . A gate insulating layer 162 and a channel layer 164 may be sequentially disposed on sidewalls of the lower channel hole 160HL and the first and second channel holes 160H1 and 160H2 . For example, the gate insulating layer 162 is conformally disposed on sidewalls and bottoms of the lower channel hole 160HL and the first and second channel holes 160H1 and 160H2, and the channel layer 164 is formed on the lower side It may be conformally disposed on sidewalls of the channel hole 160HL and the first and second channel holes 160H1 and 160H2. A buried insulating layer 166 may be disposed on the channel layer 164 to fill the remaining spaces of the lower channel hole 160HL and the first and second channel holes 160H1 and 160H2. A conductive plug 168 may be disposed on an upper side of the second channel hole 160H2 to contact the channel layer 164 and block an entrance (eg, an uppermost end) of the second channel hole 160H2 . In other embodiments, the buried insulating layer 166 is omitted, and the channel layer 164 has a pillar shape that fills the remaining portions of the lower channel hole 160HL and the first and second channel holes 160H1 and 160H2. may be formed.

The plurality of channel structures 160 may contact the upper surface 101S of the semiconductor substrate 101 . In some embodiments, a portion of the upper surface 101S of the semiconductor substrate 101 is recessed 101R, so that the lowest level of the plurality of channel structures 160 is the upper surface ( 101S). In other embodiments, a portion of the upper surface 101S of the semiconductor substrate 101 is not recessed, and the lowest level of the plurality of channel structures 160 is the upper surface 101S of the semiconductor substrate 101 . may be substantially equal to the level of

The gate insulating layer 162 may have a structure including a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer on an outer wall of the channel layer 164 sequentially. The tunneling dielectric layer may include, for example, silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage layer is a region in which electrons passing through the tunneling dielectric layer from the channel layer 164 can be stored, and may include, for example, silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. there is. The blocking dielectric layer may be made of, for example, silicon oxide, silicon nitride, or metal oxide having a higher dielectric constant than silicon oxide.

The upper support layer TS may be formed to contact the top surface of the channel structure 160 and the top surface of the second oxide layer 220 . The bit line contact BLC may penetrate the upper support layer TS to contact the conductive plug 168 of the channel structure 160 , and on the upper support layer TS, the bit line contact BLC may be in contact with the bit line contact BLC. (BL) may extend in the second direction (Y direction).

In general, in a vertical memory device having two gate stacks, a first channel hole is formed in a first gate stack, the first channel hole is filled with a sacrificial layer, and a second gate stack is formed. Next, a second channel hole is formed in the second gate stack, and a sacrificial layer filling the first channel hole is removed. Accordingly, defects may occur in the process of forming and removing the sacrificial layer, which may decrease productivity and increase manufacturing cost.

In order to solve this problem, in the integrated circuit device 100 according to the technical idea of the present invention, the first channel hole 160H1 is first formed in the first gate stack GS1 in the vertical memory device, and the first channel hole 160H1 is turned over in the opposite direction. It is manufactured by a process of forming the second channel hole 160H2 in the second gate stack GS2 .

Ultimately, since the integrated circuit device 100 according to the technical idea of the present invention can manufacture the channel hole 160H by a process that does not require a sacrificial film, it is possible to prevent defects occurring in the process of forming and removing the sacrificial film to increase productivity. can be improved, and the effect of reducing manufacturing cost can be obtained.

4 to 10 are cross-sectional views illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept according to a process sequence.

Referring to FIG. 4 , a second sacrificial gate stack SGS2 and a first sacrificial gate stack SGS1 may be formed on the forming substrate 101P.

The forming substrate 101P may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon (Si) or germanium (Ge).

A second sacrificial gate stack ( SGS2) can be formed.

A first sacrificial gate is formed by alternately forming a plurality of first mold layers 131 and a plurality of first insulating layers 140 on the second sacrificial gate stack SGS2 and forming a first oxide layer 120 . A stack SGS1 may be formed.

Accordingly, a sacrificial interface SGSM may be formed between the first sacrificial gate stack SGS1 and the second sacrificial gate stack SGS2 .

The plurality of first mold layers 131 , the plurality of second mold layers 231 , the plurality of first insulating layers 140 , and the plurality of second insulating layers 240 are formed by chemical vapor deposition (CVD) and PECVD, respectively. (plasma enhanced CVD), or may be formed by an atomic layer deposition (ALD) process.

Referring to FIG. 5 , a first channel hole 160H1 passing through the first sacrificial gate stack SGS1 may be formed.

A photoresist pattern (not shown) is formed on the first oxide layer 120 positioned on the uppermost layer of the first sacrificial gate stack SGS1 by a photolithography process. Thereafter, the first sacrificial gate stack SGS1 may be etched using the photoresist pattern as an etch mask to form a first channel hole 160H1 exposing the sacrificial interface SGSM. Thereafter, the photoresist pattern may be removed by ashing and stripping processes.

Referring to FIG. 6 , the semiconductor substrate 101 may be attached on the first sacrificial gate stack SGS1 to face the forming substrate 101P, and the forming substrate 101P may be removed.

In order to facilitate attachment of the semiconductor substrate 101 on the first sacrificial gate stack SGS1 , a bonding insulating layer 110 is formed between the semiconductor substrate 101 and the first sacrificial gate stack SGS1 . can be The bonding insulating layer 110 is formed of the same oxide-based material as the first oxide layer 120 , so that the semiconductor substrate 101 can be excellently bonded to the first sacrificial gate stack SGS1 .

Referring to FIG. 7 , a second channel hole 160H2 passing through the second sacrificial gate stack SGS2 and a lower channel hole 160HL passing through the bonding insulating layer 110 may be formed.

A photoresist pattern (not shown) is formed on the second oxide layer 220 positioned on the uppermost layer of the second sacrificial gate stack SGS2 by a photolithography process. Thereafter, the second channel hole 160H2 exposing the first channel hole 160H1 may be formed by etching the second sacrificial gate stack SGS2 using the photoresist pattern as an etching mask.

In addition, by injecting an etching gas through the first channel hole 160H1 and the second channel hole 160H2 , the lower portion exposing the upper surface 101S of the semiconductor substrate 101 through the bonding insulating layer 110 . A channel hole 160HL may be formed. In some embodiments, the lower channel hole 160HL may be over-etched so that a portion of the upper surface 101S of the semiconductor substrate 101 may be recessed. Thereafter, the photoresist pattern may be removed by ashing and stripping processes.

Referring to FIG. 8 , a plurality of channel structures 160 may be formed to fill the plurality of channel holes 160H.

Each of the plurality of channel structures 160 may include a gate insulating layer 162 , a channel layer 164 , a buried insulating layer 166 , and a conductive plug 168 .

In some embodiments, a recess may be formed in the upper surface 101S of the semiconductor substrate 101 . Accordingly, the lowest level of the plurality of channel structures 160 may be lower than the level of the upper surface 101S of the semiconductor substrate 101 .

Referring to FIG. 9 , all of the plurality of first and second mold layers 131 and 231 (refer to FIG. 8 ) exposed on the sidewalls of the plurality of channel holes 160H may be removed.

As the plurality of first and second mold layers 131 and 231 (refer to FIG. 8 ) are selectively removed by a wet etching process, the plurality of first and second insulating layers 140 and 240 are disposed between the plurality of first and second insulating layers 140 and 240 . and second gate spaces 130S and 230S may be provided. A portion of the gate insulating layer 162 may be exposed through the plurality of first and second gate spaces 130S and 230S.

The process of forming the plurality of first and second gate spaces 130S and 230S is performed by using an etching recipe having an etching selectivity with respect to the plurality of first and second insulating layers 140 and 240 to form the plurality of first gate spaces 130S and 230S. and horizontally etching the second mold layers 131 and 231 (refer to FIG. 8 ). For example, when the plurality of first and second mold layers 131 and 231 (refer to FIG. 8 ) are silicon nitride and the plurality of first and second insulating layers 140 and 240 are silicon oxide, the horizontal etching The step may be performed using an etching solution containing phosphoric acid.

Referring to FIG. 10 , a plurality of first and second gate electrodes 130 and 230 may be formed in the plurality of first and second gate spaces 130S and 230S (refer to FIG. 9 ).

Each of the first and second gate electrodes 130 and 230 may include a buried conductive layer and an insulating liner surrounding the buried conductive layer.

Referring again to FIG. 3A , the upper support layer TS and the bit line contact BLC passing through the upper support layer TS to contact the conductive plug 168 of the channel structure 160 are formed, and the upper support layer The integrated circuit device 100 may be manufactured by forming the bit line BL contacting the bit line contact BLC on the TS.

As described above, in the method of manufacturing the integrated circuit device 100 according to the inventive concept, the first channel hole 160H1 is first formed in the first gate stack GS1 in the vertical memory device, and the first channel hole 160H1 is turned over in the opposite direction. It is manufactured by a process of forming the second channel hole 160H2 in the second gate stack GS2.

Ultimately, the method for manufacturing the integrated circuit device 100 according to the technical idea of the present invention can manufacture the integrated circuit device 100 by a process that does not require a sacrificial layer, so that defects occurring in the process of forming and removing the sacrificial layer are eliminated. By preventing this, productivity can be improved, and the effect of reducing manufacturing cost can be obtained.

11 is a diagram illustrating an electronic system including an integrated circuit device according to an embodiment of the inventive concept.

Referring to FIG. 11 , the electronic system 1000 may include an integrated circuit device 1100 and a controller 1200 electrically connected to the integrated circuit device 1100 .

The electronic system 1000 may be a storage device including one or a plurality of integrated circuit devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD) device including at least one integrated circuit device 1100, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device. .

The integrated circuit device 1100 may be a nonvolatile vertical memory device. For example, the integrated circuit device 1100 may be a NAND flash memory device including the integrated circuit device 100 described above with reference to FIGS. 3A to 3C . The integrated circuit device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 , a page buffer 1120 , and a logic circuit 1130 . The second structure 1100S includes a bit line BL, a common source line CSL, a plurality of word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. It may be a memory cell structure including LL1 and LL2 and a plurality of memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure 1100S, the plurality of memory cell strings CSTR include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, respectively; and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may be variously modified according to embodiments.

In some embodiments, the upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The plurality of gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2.

The common source line CSL, the plurality of gate lower lines LL1 and LL2, the plurality of word lines WL, and the plurality of gate upper lines UL1 and UL2 are connected to the second structure 1100F in the first structure 1100F. It may be electrically connected to the decoder circuit 1110 through a plurality of first connection wires 1115 extending up to 1100S. The plurality of bit lines BL may be electrically connected to the page buffer 1120 through a plurality of second connection wires 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130 .

The integrated circuit device 1100 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 . The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the electronic system 1000 may include a plurality of integrated circuit devices 1100 , and in this case, the controller 1200 may control the plurality of integrated circuit devices 1100 .

The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the integrated circuit device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that processes communication with the integrated circuit device 1100 . Through the NAND interface 1221 , a control command for controlling the integrated circuit device 1100 , data to be written to the plurality of memory cell transistors MCT of the integrated circuit device 1100 , and a plurality of the integrated circuit device 1100 . Data, etc. to be read from the memory cell transistor MCT of the may be transmitted. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230 , the processor 1210 may control the integrated circuit device 1100 in response to the control command.

12 is a perspective view illustrating an electronic system including an integrated circuit device according to an embodiment of the inventive concept.

Referring to FIG. 12 , the electronic system 2000 may include a main board 2001 , a controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and a DRAM 2004 . .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to a communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 is connected to any one of interfaces, such as USB, Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. It can communicate with an external host. In some embodiments, the electronic system 2000 may operate by power supplied from an external host through the connector 2006 . The electronic system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the electronic system 2000 . The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 by a plurality of wiring patterns 2005 formed on the main board 2001 .

The DRAM 2004 may be a buffer memory for reducing a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the DRAM 2004 is included in the electronic system 2000 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . The first and second semiconductor packages 2003a and 2003b are respectively a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, and an adhesive layer disposed on a lower surface of each of the plurality of semiconductor chips 2200 ( 2300 ), a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 and the package substrate 2100 , and molding covering the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100 . layer 2500 may be included.

The package substrate 2100 may be a printed circuit board including a plurality of package upper pads 2130 . Each of the plurality of semiconductor chips 2200 may include an input/output pad 2201 . The input/output pad 2201 may correspond to the input/output pad 1101 of FIG. 11 . Each of the plurality of semiconductor chips 2200 may include a plurality of gate stacks 3210 and a plurality of channel structures 3220 . Each of the plurality of semiconductor chips 2200 may include the integrated circuit device 100 described above with reference to FIGS. 3A to 3C .

In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2201 and the package upper pad 2130 . Accordingly, in the first and second semiconductor packages 2003a and 2003b , the plurality of semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100 . can be connected In some embodiments, in the first and second semiconductor packages 2003a and 2003b, the plurality of semiconductor chips 2200 includes a through silicon via (TSV) instead of the bonding wire type connection structure 2400 . They may be electrically connected to each other by a connecting structure including the .

In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the controller 2002 and a plurality of semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the controller 2002 by wiring formed on the interposer substrate. A plurality of semiconductor chips 2200 may be connected to each other.

In the above, embodiments of the technical idea of the present invention have been described with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can express the present invention into other specific shapes without changing the technical spirit or essential features. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10, 100: integrated circuit device
1000, 2000: electronic system
101: semiconductor substrate 110: bonding insulating layer
120: lower insulating layer 130: first gate electrode
140: first insulating layer 160: channel structure
220: upper insulating layer 230: second gate electrode
240: second insulating layer

Claims (10)

semiconductor substrate;
a bonding insulating layer disposed on the semiconductor substrate;
a plurality of first gate electrodes extending in first and second directions parallel to and intersecting with each other on the bonding insulating layer and alternately stacked in a third direction perpendicular to the main surface; and a first gate stack comprising a plurality of first insulating layers;
a second gate on the first gate stack, extending in the first direction and the second direction, and including a plurality of second gate electrodes and a plurality of second insulating layers alternately stacked in the third direction stack;
a lower channel hole extending through the bonding insulating layer in the third direction;
a first channel hole passing through the first gate stack in the third direction and extending to be disposed on the lower channel hole;
a second channel hole passing through the second gate stack in the third direction and extending to be disposed on the first channel hole; and
a channel structure filling the lower channel hole, the first channel hole, and the second channel hole;
The lower channel hole and the second channel hole have a greater width as they move away from the semiconductor substrate in the third direction;
The width of the first channel hole becomes smaller as it moves away from the semiconductor substrate in the third direction.
integrated circuit device. According to claim 1,
A first oxide layer bonded to the bonding insulating layer is disposed on a lowermost portion of the first gate stack. According to claim 1,
The integrated circuit device, characterized in that the level of the lowermost surface of the lower channel hole is lower than the level of the upper surface of the semiconductor substrate. 4. The method of claim 3,
A portion of the upper surface of the semiconductor substrate is recessed by the channel structure. According to claim 1,
The lower channel hole, the first channel hole, and the second channel hole form one channel hole,
The channel hole is an integrated circuit device, characterized in that the inclined sidewalls having different slopes are continuous. According to claim 1,
The channel structure is
channel hole;
a gate insulating layer and a channel layer sequentially disposed on sidewalls of the channel hole;
a buried insulating layer filling the remaining space of the channel hole; and
and a conductive plug blocking the entrance of the channel hole. According to claim 1,
The channel structure penetrates the bonding insulating layer and contacts the semiconductor substrate. According to claim 1,
The integrated circuit device, wherein the lower channel hole and the second channel hole are formed by a single etching process. main board;
an integrated circuit device on the main board; and
a controller electrically connected to the integrated circuit element on the main board;
The integrated circuit device comprises:
semiconductor substrate;
a bonding insulating layer disposed on the semiconductor substrate;
a plurality of first gate electrodes extending in first and second directions parallel to and intersecting with each other on the bonding insulating layer and alternately stacked in a third direction perpendicular to the main surface; and a first gate stack comprising a plurality of first insulating layers;
a second gate on the first gate stack, extending in the first direction and the second direction, and including a plurality of second gate electrodes and a plurality of second insulating layers alternately stacked in the third direction stack;
a lower channel hole extending through the bonding insulating layer in the third direction;
a first channel hole passing through the first gate stack in the third direction and extending to be disposed on the lower channel hole;
a second channel hole passing through the second gate stack in the third direction and extending to be disposed on the first channel hole; and
a channel structure filling the lower channel hole, the first channel hole, and the second channel hole;
The lower channel hole and the second channel hole have a greater width as they move away from the semiconductor substrate in the third direction;
The width of the first channel hole becomes smaller as it moves away from the semiconductor substrate in the third direction.
electronic system. 10. The method of claim 9,
The main board further includes wiring patterns electrically connecting the integrated circuit device and the controller,
In the integrated circuit device, a first oxide layer bonded to the bonding insulating layer is disposed on a lowermost portion of the first gate stack.

Images