KR20220008368A - Semiconductor devices and data storage systems including the same - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes: a substrate; a stacked structure including interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; channel structures penetrating the stack structure in a first direction perpendicular to an upper surface of the substrate and each including a channel layer; separation structures passing through the multilayer structure in the first direction and extending in a second direction perpendicular to the first direction; wirings disposed on the stack structure and electrically connected to the gate electrodes; and on the separation structures and the multilayer structure, vertically overlapping with at least one of the separation structures and the multilayer structure, extending in a third direction intersecting the second direction, and electrically isolated Includes dummy wires.

Description

Semiconductor device and data storage system including same

The present invention relates to a semiconductor device and a data storage system including the same.

In a data storage system requiring data storage, a semiconductor device capable of storing high-capacity data is required. Accordingly, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed.

One of the technical problems to be achieved by the present invention is to provide a semiconductor device with improved reliability.

One of the technical problems to be achieved by the present invention is to provide a data storage system including a semiconductor device with improved reliability.

A semiconductor device according to example embodiments may include a substrate; a stacked structure including interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; channel structures penetrating the stack structure in a first direction perpendicular to an upper surface of the substrate and each including a channel layer; separation structures passing through the multilayer structure in the first direction and extending in a second direction perpendicular to the first direction; wirings disposed on the stack structure and electrically connected to the gate electrodes; and on the separation structures and the multilayer structure, vertically overlapping with at least one of the separation structures and the multilayer structure, extending in a third direction intersecting the second direction, and electrically isolated It may include dummy wires.

A data storage system according to example embodiments may include a lower structure including a lower substrate and circuit elements on the substrate; an upper structure on the lower structure; and an input/output pad electrically connected to the circuit elements; and a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device, wherein the upper structure includes: an upper substrate; a stacked structure including interlayer insulating layers and gate electrodes that are alternately stacked on the upper substrate; channel structures penetrating the stack structure in a first direction perpendicular to an upper surface of the upper substrate and each including a channel layer; separation structures penetrating the stack structure in the first direction and extending in a second direction perpendicular to the first direction, each of the separation structures extending in the second direction and contacting the substrate; an insulating spacer covering side surfaces of the conductive layer; wirings disposed on the stack structure and electrically connected to the gate electrodes; and dummy wirings disposed on the isolation structures, extending to cross the isolation structures, and electrically insulated from the gate electrodes and the conductive layer.

By disposing dummy wires crossing the isolation structures on the isolation structures, a semiconductor device with improved reliability and a data storage system including the same may be provided.

Various and advantageous advantages and effects of the present invention are not limited to the above, and will be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic plan view of a semiconductor device according to example embodiments.
2A and 2B are schematic cross-sectional views of semiconductor devices according to example embodiments.
3 is a partially enlarged plan view illustrating a partial region of a semiconductor device according to example embodiments.
4A and 4B are schematic cross-sectional views of semiconductor devices according to example embodiments.
5A to 5F are partially enlarged plan views illustrating a partial region of a semiconductor device according to example embodiments.
6 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.
7 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.
8 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic plan view of a semiconductor device according to example embodiments. 1 schematically shows the layout of a semiconductor device in a plan view.

2A and 2B are schematic cross-sectional views of semiconductor devices according to example embodiments. FIG. 2A is a cross-sectional view taken along the cutting line I-I of region 'A' of the semiconductor device of FIG. 1, and FIG. 2B is a cross-sectional view taken along the cutting line II-II' of region 'B' of the semiconductor device of FIG. 1 . shows

1 to 2B , the semiconductor device 100 may include a first structure 1 and a second structure 2 disposed on the first structure 1 .

The first structure 1 includes a substrate 6 , circuit elements 20 on the substrate 6 , a lower wiring structure 30 electrically connected to the circuit elements 20 , and a lower capping layer 40 . may include The first structure 1 includes a region in which peripheral circuit regions for operation of memory cells of the semiconductor device 100 are disposed, and the first structure 1 provides a row decoder, a page buffer, and other peripheral circuits. can The first structure 1 is disposed below the second structure 2 , but may be arranged side by side with the second structure 2 in a horizontal direction according to an embodiment.

The second structure 2 is a stacked structure ST including an upper substrate 101 , interlayer insulating layers 120 alternately stacked on the upper substrate 101 , and gate electrodes 130 . It may include channel structures CH and dummy structures DS passing through ST, and separation structures MS penetrating through stack structure ST and extending in one direction. The second structure 2 includes an upper isolation structure SS, an upper capping layer 160 , first upper contacts 172c and 172g, first interconnections 182c and 182g, and second upper contacts 174c, 174g), second wirings 184c and 184g, and upper insulating layers 191, 192, 193, 194, and 195 may be further included. The second structure 2 may provide a region in which the memory cell arrays including the gate electrodes 130 and the channel structures CH are disposed.

The substrate 6 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The substrate 6 may be a single crystal silicon substrate. Device isolation layers 10 are disposed in the substrate 6 , and source/drain regions 28 including impurities are formed in a portion of the active region 15 defined between the device isolation layers 10 . can be placed.

The circuit elements 20 may each include a transistor including a circuit gate dielectric layer 22 , a circuit gate electrode 24 , and source/drain regions 28 . The source/drain regions 28 may be disposed on both sides of the circuit gate electrode 24 in the active region 15 . The spacer layer 26 may be disposed on both sides of the circuit gate electrode 24 to insulate the circuit gate electrode 24 and the source/drain regions 28 from each other. The circuit gate dielectric layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. The circuit gate electrode 24 is made of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), and tungsten silicon nitride (WSiN), tungsten ( W), copper (Cu), aluminum (Al), molybdenum (Mo), and may include at least one of ruthenium (Ru). The circuit gate electrode 24 may include a semiconductor layer, for example a doped polycrystalline silicon layer, and may include a material layer such as a metal-semiconductor compound. In an exemplary embodiment, the circuit gate electrode 24 may consist of two or more multilayers.

The lower wiring structure 30 may be electrically connected to the circuit gate electrodes 24 and the source/drain regions 28 of the circuit elements 20 . The lower wiring structure 30 may include lower contact plugs 35 having a cylindrical or truncated cone shape and lower wiring lines 37 having at least one region in the form of a line. Some of the lower contact plugs 35 may be connected to the source/drain regions 28 , and although not shown, other portions of the lower contact plugs 35 may be connected to the gate electrodes 24 . The lower contact plugs 35 may electrically connect the lower wiring lines 37 disposed at different levels from the upper surface of the substrate 6 to each other. The lower wiring structure 30 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), and the like, and each of the components includes titanium (Ti) and titanium. A diffusion barrier including at least one of nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN) may be further included. In example embodiments, the number of layers and the arrangement of the lower contact plugs 35 and the lower wiring lines 37 constituting the lower wiring structure 30 may be variously changed.

The lower capping layer 40 may be disposed to cover the substrate 6 , the circuit elements 20 , and the lower wiring structure 30 . The lower capping layer 40 may be made of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The lower capping layer 40 may include a plurality of insulating layers. The lower capping layer 40 may include an etch stop layer formed of silicon nitride.

The upper substrate 101 may be disposed on the first structure 1 . A stacked structure ST may be disposed on the upper substrate 101 . The upper substrate 101 may include a semiconductor material, for example, polycrystalline silicon containing an N conductivity type impurity. In the upper substrate 101 , a region formed of polycrystalline silicon including an N conductivity type impurity may include a common source region.

As illustrated in FIG. 1 , the stack structure ST may include a memory cell array area MCA and a step area CA surrounding at least one side of the memory cell array area MCA in a plan view.

The memory cell array region MCA may be a region in which the gate electrodes 130 are stacked to be spaced apart from each other in the Z direction, and the channel structures CH are disposed. The memory cell array region MCA may be a partial region of the stacked structure ST in which the uppermost gate electrode 130U of the gate electrodes 130 overlaps the stacked structure ST in the Z direction. For example, the memory cell array region MCA may be a partial region of the stacked structure ST in which an inner region between the ends EP of the uppermost gate electrode 130U overlaps the stacked structure ST in the Z direction. have.

The step area CA may be an area in which the gate electrodes 130 form a step structure. As illustrated in FIG. 1 , the step area CA may be disposed to surround the memory cell array area MCA in a plan view. The step area CA may be an area in which the gate electrodes 130 forming the step structure provide the pad area 130_P for connecting the gate contact plugs 172g. An insulating region passing through the stacked structure ST to electrically connect the gate contact plugs 172g to the circuit elements 20 of the first structure 1 may be provided in some of the step area CA. may be

The gate electrodes 130 may be stacked to be spaced apart from each other in the Z direction on the upper substrate 101 in the memory cell array region MCA. The gate electrodes 130 may be separated by the isolation structures MS to extend in the X direction. The gate electrodes 130 include lower gate electrodes 130L forming the gate of the ground select transistor, memory gate electrodes forming a plurality of memory cells, and upper gate electrodes 130U forming the gates of the string select transistors. can do. The storage capacity of the semiconductor device 100 may be determined according to the number of the memory gate electrodes constituting the memory cells. In example embodiments, the gate electrodes 130 are disposed above the upper gate electrodes and/or under the lower gate electrodes, and are subjected to an erase operation using a gate induced drain leakage (GIDL) phenomenon. It may further include a gate electrode constituting the erase transistor used.

The gate electrodes 130 may extend to have different lengths in the X direction to form a stepped structure in the form of a step. Due to the step structure, the lower gate electrode 130 of the gate electrodes 130 may have a pad region that is extended longer than the upper gate electrode 130 and is exposed upwardly. The step structure of the gate electrodes 130 is not particularly limited. For example, the gate electrodes 130 may form a stepped structure in the X direction and a stepped structure in the Y direction between the pair of separation structures MS.

The gate electrodes 130 may be disposed to be separated from each other in the Y direction by the separation structure MS extending in the X direction. The gate electrodes 130 between the pair of isolation structures MS may form one memory block, but the scope of the memory block is not limited thereto. The gate electrodes 130 may include a first layer and a second layer, respectively. The first layer may cover upper and lower surfaces of the second layer and may extend between the channel structure CH and the second layer. The first layer may include a high dielectric material such as aluminum oxide (AlO), and the second layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten ( W), and at least one of tungsten nitride (WN). In some embodiments, the gate electrodes 130 may include polycrystalline silicon or a metal-semiconductor compound.

The interlayer insulating layers 120 may be disposed between the gate electrodes 130 in the memory cell array region MCA. Like the gate electrodes 130 , the interlayer insulating layers 120 may be stacked apart from each other in the vertical direction Z, and may extend in the X direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Some of the interlayer insulating layers 120 may have different thicknesses.

The stacked structure ST includes a lower stacked structure and an upper stacked structure on the lower stacked structure, and each of the channel structures CH includes a lower channel structure penetrating the lower stacked structure and an upper portion penetrating the upper stacked structure. It may include a channel structure. In this case, each of the channel structures CH may include a bent portion due to a difference in width in a connection region where the lower stacked structure and the upper stacked structure are bonded to each other. This embodiment corresponds to a case in which the stacked structure ST is a double stacked structure, and the present invention may also include an embodiment of a multi-stack structure in which the stacked structure ST is a double or more stacked structure.

As shown in FIG. 1 , each of the channel structures CH forms one memory cell string and may be disposed to be spaced apart from each other while forming rows and columns in the memory cell area MCA. The channel structures CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction. The channel structures CH may have a columnar shape, and may have inclined side surfaces that are narrower in width as they approach the upper substrate 101 according to an aspect ratio.

A channel layer 140 may be disposed in the channel structures CH. In the channel structures CH, the channel layer 140 may be formed in an annular shape surrounding the inner core insulating layer 147 . The channel layer 140 may be in contact with the epitaxial layer 107 at a lower portion and may be electrically connected to the upper substrate 101 . The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

A channel pad 149 may be disposed on the channel layer 140 in the channel structures CH. The channel pad 149 may be disposed to cover the upper surface of the core insulating layer 147 and be electrically connected to the channel layer 140 . The channel pad 149 may include, for example, doped polycrystalline silicon. The channel pad 149 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, for example, may include doped polycrystalline silicon.

The gate dielectric layer 145 may be disposed between the gate electrodes 130 and the channel layer 140 . The gate dielectric layer 145 may include a tunneling layer, an information storage layer, and a blocking layer sequentially stacked from the channel layer 140 . The tunneling layer may tunnel charges into the information storage layer, and may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. . The information storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrodes 130 .

As shown in FIG. 2A , the channel structures CH may pass through the gate electrodes 130 of the stack structure ST in the Z direction and contact the upper substrate 101 . An epitaxial layer 107 may be disposed between the channel layer 140 and the upper substrate 101 in the channel structures CH. The epitaxial layer 107 contacts the upper substrate 101 and may be disposed adjacent to a side surface of the at least one gate electrode 130L. The epitaxial layer 107 may be disposed by partially recessing the upper substrate 101 . The height of the upper surface of the epitaxial layer 107 may be higher than the upper surface of the lowermost gate electrode 130 and lower than the lower surface of the upper gate electrode 130, but is not limited thereto. The epitaxial layer 107 may be connected to the channel layer 140 through the top surface. A lower insulating layer 108 may be disposed between the epitaxial layer 107 and the lower gate electrode 130L adjacent thereto.

The dummy vertical structure DS may be disposed in the step area CA as shown in FIG. 1 . The dummy vertical structures DS may be disposed to be spaced apart from each other in rows and columns similar to the channel structures CH, and may be disposed to form a grid pattern or disposed in a zigzag shape in one direction. The dummy vertical structure DS may have the same or similar structure to the channel structure CH, but may not perform a substantial function in the semiconductor device 100 . In an exemplary embodiment, the dummy vertical structure DS may have a structure different from that of the channel structure CH, and for example, an inside thereof may be formed of an insulating material such as silicon oxide. Also, a structure disposed to overlap the upper isolation region SS among the channel structures CH may be a dummy channel structure.

The separation structure MS penetrates the stack structure ST in the Z direction, It may be arranged to extend along the X direction. The separation structure MS may include a plurality of separation structures MS that are arranged side by side in the Y direction. The isolation structures MS may separate the gate electrodes 130 from each other in the Y direction. Based on the upper surface of the upper substrate 101 , the level of the upper surface of the isolation structure MS may be higher than the level of the upper surface of the channel structure CH. The isolation structure MS may vertically penetrate the entire stacked gate electrodes 130 and contact the upper substrate 101 . The separation structure MS may have a shape in which a width decreases as it approaches the upper substrate 101 due to a high aspect ratio. The isolation structure MS may include a conductive layer 105 and an isolation insulating layer 106 covering side surfaces of the conductive layer 105 . The conductive layer 105 may be formed of a conductive material, and the isolation insulating layer 106 may be formed of an insulating material. The conductive layer 105 may extend along the X direction and contact the upper substrate 101 . The conductive layer 105 may form a common source line together with the impurity region of the upper substrate 101 .

The upper separation structures SS may extend in the X direction between the separation structures MS. The upper isolation structure SS may separate the upper gate electrodes 130 including the uppermost gate electrodes 130U among the gate electrodes 130 in the Y direction. For example, the upper isolation structure SS may pass through the uppermost gate electrode 130U and the second upper gate electrode 130 disposed thereunder. The number of gate electrodes 130 separated by the upper isolation structure SS may be variously changed in embodiments. The upper gate electrodes 130 separated by the upper isolation structure SS may form different string selection lines in the semiconductor device 100 . The upper isolation structure SS may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

The upper capping layer 160 is disposed on the stack structure ST to cover a portion of side surfaces of the channel structures CH, the dummy structure DS, the isolation structure MS, and the upper isolation structure SS, respectively. It can be arranged to The upper surface of the upper capping layer 160 may be substantially coplanar with the upper surface of the channel structure CH and the upper surface of the channel structure DS. The upper capping layer 160 may be made of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

The first upper contacts 172c and 172g may be disposed on the stack structure ST. The first upper contacts 172c and 172g may include first channel contacts 172c and first gate contacts 172g. The first channel contacts 172c may be connected to the channel structures CH. The first gate contacts 172g may be connected to the pad areas 130_P of the gate electrodes 130 in the step area CA.

The second upper contacts 174c and 174g may be disposed on the first interconnections 182c and 184g. It may include second channel contacts 174c and second gate contacts 174g. The second channel contacts 174c may be connected to the first channel wires 182c. The second gate contacts 174g may be connected to the first gate lines 184g.

The first wirings 182 may be disposed on the first upper contacts 172c and 172g. The first wirings 182c and 184g may include first channel wirings 182c and first gate wirings 182g. The first channel wires 182c may be connected to the first channel contacts 172c. The first gate lines 182g may be connected to the first gate contacts 172g.

The second wirings 184 may be disposed on the second upper contacts 174c and 174g. The second wirings 184c and 184g may include second channel wirings 184c and second gate wirings 184g. The second channel wires 184c may be connected to the second channel contacts 174c. The second gate lines 184g may be connected to the second gate contacts 174g.

The upper contacts 172c, 172g, 174c, and 174g and the upper interconnections 182c, 182g, 184c, and 184g may form an upper interconnection structure. Each component constituting the upper wiring structure may include a conductive layer and a barrier layer covering the lower surface and side surfaces of the conductive layer. The barrier layer may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). have. The conductive layer may include a conductive material, for example, at least one of tungsten (W), copper (Cu), and aluminum (Al).

The upper insulating layers 191 , 192 , 193 , 194 , and 195 are disposed on the upper capping layer 160 , and the first upper insulating layer 191 , the second upper insulating layer 192 , and the third are sequentially stacked. It may include an upper insulating layer 193 , a fourth upper insulating layer 194 , and a fifth upper insulating layer 195 . Each of the upper insulating layers 191 , 192 , 193 , 194 , and 195 may be made of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

3 is a partially enlarged plan view illustrating a partial region of a semiconductor device according to example embodiments. 3 is an enlarged view of a partial area of the step area CA of the semiconductor device 100 of FIG. 1 , and for convenience of explanation, the dummy structure DS and the ends EP of the gate electrodes 130 . , and the gate contacts 172g are omitted.

4A and 4B are schematic cross-sectional views of semiconductor devices according to example embodiments. 4A and 4B show cross-sections taken along cutting lines III-III' and IV-IV' of FIG. 3, respectively.

3 and 4 , the second structure 2 of the semiconductor device 100 is disposed at the same level as the first wirings 182 , extends to cross the isolation structures MS, and is electrically It may further include electrically isolated dummy wires 182D. The dummy interconnections 182D may prevent cracks from occurring in the isolation structures MS or may prevent cracks from propagating from the isolation structures MS.

The dummy wirings 182D may be disposed on the step area CA of the stack structure ST, for example, on the separation structures MS extending in the X direction from the step area CA. can The dummy interconnections 182D may vertically overlap with at least one of the separation structures MS and the stacked structure ST on the stacked structure ST of the separation structures MS. The dummy wirings 182D are in an electrically floating state, and for example, may be electrically insulated from the gate electrodes 130 and the conductive layers 105 of the isolation structures MS. For example, in regions where the isolation structures MS and the dummy lines 182D intersect each other, upper contacts 172c and 172g are disposed between the isolation structures MS and the dummy lines 182D. it may not be Alternatively, the first wirings 182 may be electrically connected to the channel structures CH and the gate electrodes 130 . For example, as shown in FIG. 1 , some 182g of the first wirings 182 may be electrically connected to the gate electrodes 130 through the first gate contacts 172g, and the first Some 182c of the wirings 182 may be electrically connected to the channel structures CH through the first channel contacts 172c. The first wirings 182 may be electrically connected to the second wirings 184 through the second upper contacts 174 . Although not shown, some of the first wirings 182 may be electrically connected to the conductive layer 105 of the isolation structure MS in the memory cell array area MCA. Among the wirings, whether the components are electrically isolated dummy wirings 182D or the first wirings 182 to which an electrical signal is applied is determined whether the corresponding component is electrically connected to a conductive layer disposed above or below the component. You can check whether it is or not.

The dummy interconnections 182D may extend in a Y direction perpendicular to the X direction. For example, the length of the dummy wires 182D in the Y direction may be longer than the length in the X direction. The dummy wirings 182D may be arranged side by side along the X direction on the isolation structures MS. Some of the dummy wires 182D may be disposed between the first wires 182 , and some of the dummy wires 182 may be alternately arranged with the first wires 182 in the X direction. The adjacent dummy wirings 182D may be arranged at a uniform pitch or spacing from each other, but may be arranged at a different pitch or spacing as in other embodiments below. The dummy wires 182D may be spaced apart from the first wires 182 and may be appropriately arranged in a space where the first wires 182 are not disposed.

5A to 5F are partially enlarged plan views illustrating a partial region of a semiconductor device according to example embodiments. 5A to 5F are diagrams exemplarily illustrating the arrangement of dummy wirings.

Referring to FIG. 5A , the dummy wires 182Da of the semiconductor device 100A extend in a direction parallel to the top surface of the upper substrate 101 , and may extend in directions oblique to the X and Y directions. The dummy interconnections 182Da may be disposed on the separation structure MS and may extend at an angle to the extending direction of the separation structure MS.

Referring to FIG. 5B , the dummy wires 182Db of the semiconductor device 100B have a first pattern PA1 having a first width W1 and a second width W2 greater than the first width W1 . The second pattern PA2 may be included. The first pattern PA1 and the second pattern PA2 may be alternately arranged. However, the arrangement of the first pattern PA1 and the second pattern PA2 is not limited to the illustrated one, and may be variously changed according to embodiments.

Referring to FIG. 5C , the dummy wirings 182Dc of the semiconductor device 100C have first patterns PB1 disposed at a first interval D1 and a second interval D2 greater than the first interval D1 . It may include second patterns PB2 disposed as . An arrangement density of the first patterns PB1 may be different from an arrangement density of the second patterns PB2 . For example, the arrangement density of the first patterns PB1 may be less than the arrangement density of the second patterns PB2 .

Referring to FIG. 5D , the dummy wires 182Dd of the semiconductor device 100D may have a rectangular ring shape in plan view. For example, each of the dummy interconnections 182Dd includes a pair of first portions intersecting the isolation structures MS and a pair of second portions extending in a direction parallel to the isolation structures MS. may include

Referring to FIG. 5E , each of the dummy wirings 182De of the semiconductor device 100E includes first portions intersecting the isolation structures MS in a plan view, and the isolation structure MS connecting the first portions to each other. It may include second portions extending in a direction parallel to the .

Referring to FIG. 5F , some MS′ of the isolation structures MS of the semiconductor device 100F intermittently extend in the step area CA, and some 182D′ of the dummy wirings 182D are formed in the step area CA. Separation structures MS' may be disposed to overlap with regions separated from each other.

6 is a diagram schematically illustrating a data storage system including a semiconductor device according to example embodiments.

Referring to FIG. 6 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 . The data storage system 1000 may be a storage device including one or a plurality of semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive device (SSD) including one or a plurality of semiconductor devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device. .

The semiconductor device 1100 may be a nonvolatile memory device, for example, the NAND flash memory device described above with reference to FIGS. 1 to 11 . The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In example embodiments, the first structure 1100F may be disposed next to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 , a page buffer 1120 , and a logic circuit 1130 . The second structure 1100S includes a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1 and UL2, and first and second gate lower lines. It may be a memory cell structure including memory cell strings CSTR between the bits LL1 and LL2 and the bit line BL and the common source line CSL.

In the second structure 1100S, each of the memory cell strings CSTR includes lower transistors LT1 and LT2 adjacent to the common source line CSL and upper transistors UT1 adjacent to the bit line BL. UT2) and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified according to embodiments.

In example embodiments, the upper transistors UT1 and UT2 may include a string select transistor, and the lower transistors LT1 and LT2 may include a ground select transistor. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used for an erase operation of erasing data stored in the memory cell transistors MCT using the GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 are connected to the first structure ( It may be electrically connected to the decoder circuit 1110 through first connection wires 1115 extending from the inside 1100F to the second structure 1100S. The bit lines BL may be electrically connected to the page buffer 1120 through second connection lines 1125 extending from the first structure 1100F to the second structure 1100S.

In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130 . The semiconductor device 1000 may communicate with the controller 1200 through the input/output pad 1101 electrically connected to the logic circuit 1130 . The input/output pad 1101 may be electrically connected to the logic circuit 1130 through an input/output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1000 .

The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200 . The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220 . The NAND controller 1220 may include a NAND interface 1221 that handles communication with the semiconductor device 1100 . Through the NAND interface 1221 , a control command for controlling the semiconductor device 1100 , data to be written to the memory cell transistors MCT of the semiconductor device 1100 , and memory cell transistors ( Data to be read from the MCT) may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When receiving a control command from an external host through the host interface 1230 , the processor 1210 may control the semiconductor device 1100 in response to the control command.

7 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment.

Referring to FIG. 7 , a data storage system 2000 according to an exemplary embodiment of the present invention includes a main board 2001 , a controller 2002 mounted on the main board 2001 , one or more semiconductor packages 2003 , and DRAM 2004 . The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001 .

The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on a communication interface between the data storage system 2000 and the external host. In example embodiments, the data storage system 2000 includes an M-Phy for Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS), etc. can communicate with an external host according to any one of the interfaces of In example embodiments, the data storage system 2000 may operate by power supplied from an external host through the connector 2006 . The data storage system 2000 may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003 .

The controller 2002 may write data to or read data from the semiconductor package 2003 , and may improve the operating speed of the data storage system 2000 .

The DRAM 2004 may be a buffer memory for mitigating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003 . When the data storage system 2000 includes the DRAM 2004 , the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003 .

The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. Each of the first and second semiconductor packages 2003a and 2003b may be a semiconductor package including a plurality of semiconductor chips 2200 . Each of the first and second semiconductor packages 2003a and 2003b includes the package substrate 2100 , the semiconductor chips 2200 on the package substrate 2100 , and adhesive layers 2300 disposed on lower surfaces of the semiconductor chips 2200 , respectively. ), a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100. may include

The package substrate 2100 may be a printed circuit board including package upper pads 2130 . Each semiconductor chip 2200 may include an input/output pad 2210 . The input/output pad 2210 may correspond to the input/output pad 1101 of FIG. 6 . Each of the semiconductor chips 2200 may include gate stack structures 3210 and channel structures 3220 . Each of the semiconductor chips 2200 may include the semiconductor device described above with reference to FIGS. 1 to 5D .

In example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input/output pad 2210 and the package upper pads 2130 . Accordingly, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pads 2130 of the package substrate 2100 and may be electrically connected. According to embodiments, in each of the first and second semiconductor packages 2003a and 2003b , the semiconductor chips 2200 may include a through-electrode (through silicon via, TSV) instead of the bonding wire-type connection structure 2400 . It may be electrically connected to each other by a connection structure comprising a.

In example embodiments, the controller 2002 and the semiconductor chips 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chips are formed by wiring formed on the interposer substrate. 2200 may be connected to each other.

8 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment. 8 illustrates an exemplary embodiment of the semiconductor package 2003 of FIG. 7 , and conceptually shows a region cut along the cutting line V-V' of the semiconductor package 2003 of FIG. 7 .

Referring to FIG. 8 , in the semiconductor package 2003 , the package substrate 2100 may be a printed circuit board. The package substrate 2100 is disposed on the package substrate body 2120 , the package upper pads 2130 (refer to FIG. 7 ) disposed on the upper surface of the package substrate body 2120 , and on the lower surface of the package substrate body 2120 . lower pads 2125 exposed through the lower surface or through the lower surface, and internal wirings 2135 electrically connecting the upper pads 2130 and the lower pads 2125 in the package substrate body 2120. can The upper pads 2130 may be electrically connected to the connection structures 2400 . The lower pads 2125 may be connected to the wiring patterns 2005 of the main board 2010 of the data storage system 2000 as shown in FIG. 7 through conductive connectors 2800 .

Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 that are sequentially stacked on the semiconductor substrate 3010 . The first structure 3100 may include a peripheral circuit region including peripheral wirings 3110 . The second structure 3200 includes a common source line 3205 , a gate stacked structure 3210 on the common source line 3205 , channel structures 3220 passing through the gate stacked structure 3210 and isolation regions 3230 . , bit lines 3240 electrically connected to the memory channel structures 3220 , and gate contact plugs electrically connected to the word lines WL (refer to FIG. 6 ) of the gate stack structure 3210 . can As described above with reference to FIGS. 1 to 5F , each of the semiconductor chips 2200 includes a substrate 6 , an upper substrate 101 , an isolation pattern MS, first wirings 182 , and dummy wirings ( 182D).

Each of the semiconductor chips 2200 may include a through wiring 3245 electrically connected to the peripheral wirings 3110 of the first structure 3100 and extending into the second structure 3200 . The through wiring 3245 may be disposed outside the gate stacked structure 3210 , and may be further disposed to pass through the gate stacked structure 3210 . Each of the semiconductor chips 2200 may further include an input/output pad 2210 (refer to FIG. 7 ) electrically connected to the peripheral wirings 3110 of the first structure 3100 .

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various types of substitutions, modifications and changes and combinations of embodiments will be possible by those of ordinary skill in the art within the scope without departing from the spirit of the present invention described in the claims, and this is also the present invention will be said to be within the scope of

CA: stair area CH: channel structure
DS: dummy structure MCA: memory cell area
MS: Separation Structure ST: Laminate Structure
6: substrate 20: circuit element
30: lower wiring structure 40: lower capping layer
101: upper substrate 105: conductive layer
106: isolation insulating layer 120: interlayer insulating layer
130: gate electrode 140: channel layer
145: gate dielectric layer 147: core insulating layer
149: channel pad 160: upper capping layer
182: first wirings 182D: dummy wirings
184: second wirings 192, 192, 193, 194, 195: upper insulating layer

Claims (10)

Board;
a stacked structure including interlayer insulating layers and gate electrodes that are alternately stacked on the substrate;
channel structures penetrating the stack structure in a first direction perpendicular to an upper surface of the substrate and each including a channel layer;
separation structures passing through the multilayer structure in the first direction and extending in a second direction perpendicular to the first direction;
wirings disposed on the stack structure and electrically connected to the gate electrodes; and
an electrically isolated dummy, vertically overlapping with at least one of the separation structures and the multilayer structure, extending in a third direction intersecting the second direction, and electrically isolated on the separation structures and the stacked structure A semiconductor device comprising wires.
According to claim 1,
The multilayer structure includes a memory cell region in which the channel structures are arranged and a step region in which the gate electrodes form a step structure,
The dummy wirings are disposed on the step area.
According to claim 1,
Each of the separation structures includes a conductive layer extending in the second direction and in contact with the substrate and a separation insulating layer covering side surfaces of the conductive layer,
The dummy wirings are electrically insulated from the gate electrodes and the conductive layer.
According to claim 1,
In regions where the isolation structures and the dummy lines cross each other, contacts are not disposed between the isolation structures and the dummy lines.
According to claim 1,
The third direction is perpendicular to the first direction and the second direction.
According to claim 1,
The third direction is a direction oblique to the second direction.
According to claim 1,
The dummy wirings include first patterns having a first width and second patterns having a second width greater than the first width.
According to claim 1,
The dummy wirings may include first patterns disposed at a first interval and second patterns disposed at a second interval greater than the first interval.
a lower structure including a lower substrate and circuit elements on the substrate; an upper structure on the lower structure; and an input/output pad electrically connected to the circuit elements; and
a controller electrically connected to the semiconductor storage device through the input/output pad and controlling the semiconductor storage device;
The upper structure is
upper substrate;
a stacked structure including interlayer insulating layers and gate electrodes that are alternately stacked on the upper substrate;
channel structures penetrating the stack structure in a first direction perpendicular to an upper surface of the upper substrate and each including a channel layer;
separation structures penetrating the stack structure in the first direction and extending in a second direction perpendicular to the first direction, each of the separation structures extending in the second direction and contacting the substrate; an insulating spacer covering side surfaces of the conductive layer;
wirings disposed on the stack structure and electrically connected to the gate electrodes; and
and dummy wirings disposed on the isolation structures, extending to cross the isolation structures, and electrically insulated from the gate electrodes and the conductive layer.
10. The method of claim 9,
The multilayer structure includes a memory cell region in which the channel structures are arranged and a step region in which the gate electrodes form a step structure,
and the dummy wires are disposed on the step area.

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