KR20210089773A - Skew Compensation Method for Physical Layer Interface of Multi-Chip Modules - Google Patents

Abstract

A system, apparatus and method for implementing a skew correction method for a physical layer interface in a multi-chip module are disclosed. Circuitry coupled to the plurality of communication lanes trains each lane to synchronize the lane's local clock with a corresponding global clock at the beginning of a timing window. Next, the circuitry symbol rotates each lane in a single step in response to determining that all lanes of the plurality of lanes have incorrect symbol alignment. In response to determining that some but not all of the plurality of lanes have the correct symbol alignment, the circuitry symbol rotates the lanes with the incorrect symbol alignment in a single step. When the end of the timing window is reached, the circuit symbol rotates lanes with correct symbol alignment and adjusts the phase of the corresponding global clock to compensate for the missing symbol rotation.

Description

Skew Compensation Method for Physical Layer Interface of Multi-Chip Modules

Modern semiconductor chips contain various circuits and components that facilitate fast and efficient calculations. When transferring information between functional blocks of a semiconductor chip, electrical signals are typically transmitted as metal traces. The transmitter of the first functional block sends an electrical signal through the metal trace. The receiver of the second functional block receives the electrical signal. In some cases, both functional blocks are in the same die. In other cases, the two functional blocks are on separate dies.

The processing speed of information processing systems and devices continues to increase as new systems and devices are developed. When a data signal and a corresponding clock signal are transmitted between functional blocks, the signals may be misaligned with respect to each other. Signal reordering usually introduces a large amount of latency.

The advantages of the methods and mechanisms described herein may be better understood by reference to the following description in conjunction with the accompanying drawings, wherein:
1 is a block diagram of one implementation of a typical computer or communication system including a transmitter and a receiver;
2 is a block diagram of one implementation of a computing system.
3 is a diagram of one implementation of a physical layer interface connection.
4 is a block diagram of one implementation of a circuit for adjusting the phase of a local clock to achieve a synchronous clock-domain crossing.
5 is a block diagram of one implementation of a circuit for implementing an optional FIFO mode for increasing the available timing margin to achieve synchronous clock-domain crossing.
6 is a diagram of one implementation of a circuit for use in a deserializer.
7 is a timing diagram of one implementation using a barrel shifter in a deserializer to perform symbol locking.
8 is a timing diagram of one implementation at a point in time after the barrel shifter shifts the clock phase by a single step.
9 is a timing diagram of one implementation at a point in time after the barrel shifter shifts the clock phase to a second phase.
10 is a state diagram of one implementation for performing link width skew correction with minimal latency.
11 is a diagram of one implementation of a circuit for use in a deserializer.
12 is a diagram of one implementation of a two-dip FIFO circuit for increasing the timing margin to account for clock jitter.
13 is a generalized flow diagram illustrating one implementation of a method for performing training to align a local clock with a global clock.
14 is a generalized flow diagram illustrating one implementation of a method for achieving synchronous cross-domain crossing for a plurality of lanes.
15 is a generalized flow diagram illustrating one implementation of a method for skew correction across a plurality of lanes with reduced latency.
16 is a block diagram illustrating one implementation of a non-transitory computer-readable storage medium that stores a circuit representation.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the methods and mechanisms presented herein. However, one of ordinary skill in the art should recognize that various implementations may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail in order to avoid obscuring the approaches described herein. It will be understood that, for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others.

Various systems, apparatus, methods and computer readable media are disclosed for a method of deskewing for a physical layer interface of a multi-chip module implementing synchronous clock-domain crossing with reduced latency. . In one implementation, circuitry coupled to a plurality of communication lanes trains each lane to synchronize its local clock with a corresponding global clock at the beginning of a timing window. . A circuit symbol then rotates each lane in a single step in response to determining that all of the plurality of lanes have incorrect symbol alignment. In response to determining that some but not all of the plurality of lanes have the correct symbol alignment, the circuit symbol rotates the lanes with the incorrect symbol alignment in a single step. When the end of the timing window is reached, the circuit symbol rotates the lanes with correct symbol alignment and adjusts the phase of the corresponding global clock to compensate for the missing symbol rotation. The circuitry samples the plurality of data signals using the plurality of local clocks to generate a plurality of data sequences in response to determining that all of the plurality of lanes have correct symbol alignment.

In various implementations, techniques for implementing synchronous clock domain crossings with reduced latency are disclosed. In one implementation, the circuit generates a local clock while receiving a global clock and data signal. The circuit includes a register that samples the local clock with the global clock. The circuit also includes a barrel shifter that generates a phase-shifted version of the local clock with a single unit interval (UI) step size. The circuit also includes control logic that sweeps the local clock through all phases until an edge transition is detected using a barrel shifter. When an edge transition is detected, it indicates that the local clock is aligned with the global clock. Then, the control logic adjusts the phase of the local clock to meet the data signal sampling settings and maintain the requirements. Next, the data signal is sampled with a phase-adjusted local clock to generate a data sequence.

Referring now to FIG. 1 , a block diagram of one implementation of a typical computer or communication system 100 including a transmitter 105 and a receiver 110 is shown. In one implementation, the transmitter 105 transmits data to the receiver 110 over a communication channel 115 . Depending on the implementation, the communication channel 115 is a cable, a backplane, one or more metal traces, or another type of communication channel. For example, in one implementation, channel 115 is one or more metal traces between two chips of a multi-chip module. At the physical layer, communication between the transmitter 105 and the receiver device 110 may be unidirectional or bidirectional depending on a given transport protocol. It is noted that system 100 may include any number and type of other devices. Additionally, system 100 may include any number of transmitter-receiver pairs distributed throughout the system.

Transmitter 105 and receiver 110 may be any type of device depending on the implementation. For example, in one implementation, transmitter 105 is a processing unit (eg, central processing unit (CPU), graphics processing unit (GPU)) and receiver 110 is a memory device. Memory devices include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and/or low-power versions of SDRAM such as LPDDR2); It can be any type of memory, such as RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), or the like. Alternatively, the memory device may be mounted within a system-on-chip (SoC) or integrated circuit (IC) in a chip-on-chip configuration, package-on-package configuration, or multi-chip module (MCM) configuration.

In another implementation, the transmitter 105 is an input/output (I/O) fabric and the receiver 110 is a peripheral device. Peripheral devices may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning systems, and the like. Peripheral devices may also include additional storage including RAM storage, solid state storage, or disk storage. Peripheral devices may also include display screens such as touch display screens or multi-touch display screens, keyboards or other input devices, user interface devices such as microphones, speakers. In other implementations, transmitter 105 and receiver 110 are different types of devices. Note that system 100 may be any type of system, such as an IC, SoC, MCM, or the like.

Referring now to FIG. 2 , a block diagram of an implementation of a computing system 200 is shown. As shown, system 200 represents a chip, circuit, component, etc., of a desktop computer 210 , a laptop computer 220 , a server 230 , a mobile device 240 , or other device. Other devices are possible and contemplated. In the illustrated implementation, system 200 includes any number of pairs of transmitters 202A-N and receivers 203A-N.

Referring now to FIG. 3 , a diagram of one implementation of a physical layer interface connection is shown. A master physical coding sublayer (PCS) 305 shown on the left side of FIG. 3 is connected to a slave PCS 380 on the right side of FIG. 3 through a channel 340 . In one implementation, the master PCS 305 is located in a first integrated circuit (IC) (ie, chip) of a multi-chip module (MCM) and the slave PCS 380 is located in a second IC of the MCM. For example, in one implementation, the master PCS 305 is part of an input/output (I/O) semiconductor die and the slave PCS 380 is part of a core complex semiconductor die. In other implementations, master PCS 305 and slave PCS 380 are included along with other types of components or functional units.

In various implementations, the master PCS 305 includes a phase-locked loop (PLL) 310 for generating a clock coupled to a clock transmission module 325 and other modules within the master PCS 305 , or coupled to this The master PCS 305 includes an array of N receivers 315 and an array of M transmitters 335 , where N and M are positive integers, where the values of N and M vary from implementation to implementation. . A receive clock gating (RXCG) module 320 is coupled to the array of receivers 315 and a transmit clock gating (TXCG) module 330 is coupled to the array of transmitters 335 . In one implementation, the clock is forwarded from the master PCS 305 , which is used as the reference clock for the PLL 310 . The clock generated by PLL 310 is forwarded over channel 340 to be used as a reference clock for PLL 375 (of slave PCS 380 ) and downstream logic. In one implementation, a half rate architecture is used by the master PCS 305 and the slave PCS 380 , where the clock is half the frequency of the data rate and the data is sampled on the rising and falling edges of the clock. .

In one implementation, the array of transmitters 335 of the master 305 is coupled to corresponding lanes of the channel 340 having a width greater than 1000 microns (ie, micrometers) between the furthest lanes. Also, in one implementation, the array of receivers 315 of the master 305 is coupled to corresponding lanes of the package channel 340 having a width greater than 1000 microns between the furthest lanes. This causes drift between the clock edges of the different clocks transmitted in the lanes of channel 340 .

In one implementation, synchronous clock domain crossing is achieved across the array of transmitters 335 using one or more of the methods and mechanisms described herein. For example, even if the lanes of the array of transmitters 335 are separated by a distance greater than 1000 microns in width, using the technique presented herein (compared to the traditional approach) it adds a relatively small amount of latency to the interface. Synchronous clock domain crossing is achieved. In one implementation, to achieve synchronous clock domain crossing, the local clock of the slave PCS 380 is trained to align with the forwarded controller clock. As used herein, the term “local clock” is defined as a segmented version of the relatively fast PLL clock. Also, as used herein, the term “controller clock” is defined as a system-on-chip (SoC) master clock distributed across the lanes of a channel (eg, channel 340 ).

In one implementation, delay is added at 1 unit interval (UI) granularity to minimize transmission channel skew between lanes. In one implementation, an optional first-in, first-out (FIFO) mode is implemented to increase the available timing margin to achieve synchronous intersection. By enabling FIFO mode, more delay is available at the expense of more latency. However, this provides an additional tuning range that can be used to reduce transmission channel skew. In one implementation, prior to training, symbol start points are distributed across the various transmission lanes of channel 340 . After training, the symbol start points on the various transmission lanes of channel 340 are aligned within 1 UI of each other.

Referring now to FIG. 4 , a block diagram of one implementation of a circuit 400 for adjusting the phase of a local clock to achieve synchronous clock domain crossing is shown. In one implementation, for the physical layer (PHY) interface, the input controller clock is phase-locked, while the local clock is a divided version of the fast clock generated by the PLL 420 (divider 422). is used). The local clock is provided to a clock training unit 425 . An example of a clock training unit 425 is shown as control logic in block 405 . As shown in block 405 , the local clock is phase shifted using a barrel shifter 415 . In one implementation, a plurality of local clocks are trained to align with corresponding controller clocks, and then the trained local clocks are coupled to 10/2 serializers as shown in block 430 .

In one implementation, a two-step training method is performed to train the phase of the local clock to match the corresponding controller clock. If the phase relationship between the local clock and the controller clock is not known in the first step, a training step is performed to establish the phase relationship for the local clock of each lane to the controller clock. In the second step of the training method, the phase of each local clock is adjusted with respect to the controller clock to meet the setup and maintenance requirements.

In one implementation, the controller clock is used to sample the local clock in the sync register 417 and the output of the sync register 417 is provided to a clock train finite state machine (FSM) 410 . Using the barrel shifter 415, the local clock is swept across all phases until a shift of the sampler output (ie, the output of the sync register 417) from 0 to 1 is detected. When the sampler output detects a shift from 0 to 1, it indicates that the local clock is aligned within +/- 1 unit interval (UI) of the controller clock. In one implementation, 1 UI is 1/10th of a 1x clock, and 1 UI is the minimum resolution for clock sweeping. In one implementation, additional averaging is performed in the clock train FSM 410 to account for the delta due to the low frequency phase offset. Once the local clock is aligned with the controller clock, the phase of the local clock is adjusted to meet the setup and hold timing requirements. This method repeats for all lanes, so data coming from different lanes is synchronized to the controller clock with relatively low latency. Additionally, in one implementation, a delay is added between the lanes to minimize skew caused by the transmitter and the channel.

Using the approach illustrated in Figure 4, data is transferred from the controller clock domain to the local clock domain in flop-to-flop timing, reducing the latency present in existing designs. Timing diagram 440 represents an example of the pre-training timing of the local clock relative to the controller clock. Timing diagram 450 shows an example of timing achieved between a local clock and a controller clock after training and after the local clock has been adjusted relative to the controller clock to meet setup and maintenance requirements.

Referring now to FIG. 5 , shown is a block diagram of one implementation of a circuit 500 for implementing an optional FIFO mode for increasing the available timing margin to achieve synchronous clock domain crossing. In one implementation, the computing system potentially has a clock domain that crosses between a high-jitter controller clock and a lane-generated local clock. The controller clock is used as the parallel data launch clock from the master PCS and the lane-generated local clock (ie word clock) is used for parallel data capture at the PHY interface. In one implementation, the synchronous clock domain crossing from the controller clock to the lane-generated local clock is achieved via a clock training algorithm with an optional FIFO buffer. If the expected controller clock jitter is high enough that even the trained interface cannot meet the timing, one implementation uses a FIFO to increase jitter tolerance. In one implementation, a two-entry FIFO is used to double the jitter tolerance.

In one implementation, in the default mode, the local clock is adjusted to 1 UI resolution based on the initial average difference between the controller clock and the local clock to ensure an adequate timing margin for expected controller clock jitter. In one implementation, in the selective FIFO mode, the half rate version of the controller clock acts as the write pointer while the half rate version of the local clock is used as the read pointer. The clock training algorithm determines the initial average write/read pointer separation for the programmable placement of the read pointer. In one implementation, the read pointer placement is adjusted to 1 UI resolution to ensure proper timing margin while minimizing latency in the parallel data capture interface based on the expected controller clock jitter magnitude. In one implementation, if there is an adequate margin for pointer separation, the read pointer is further adjusted after initial clock training in 1 UI step size to reduce lane-to-lane skew. When the data is crossed into the local clock domain, the data is serialized and provided to the channel through the transmit lanes.

In one implementation, the input data is supplied via flops 510 in the Physical Coding Sublayer (PCS) 505 domain. A controller clock is provided to the clock inputs of flops 510 . In one implementation, the input data is 10 bits wide. However, in other implementations, the input data may have different bit widths. Similarly, the bit widths of different paths of circuit 500 may vary in different implementations. The output of flops 510 is provided in parallel to flops 515 and 520 of transmit macro domain 507 . The half rate controller clock is provided as a clock to the clock inputs of flops 515 and 520 . The outputs of flops 515 and 520 are provided to the input of multiplexer 525 . The outputs of multiplexer 525 are coupled to inputs of flops 535 . A 1x rate local clock is coupled to the clock inputs of flops 535 . The outputs of the flops 535 are provided to a serializer (not shown).

In one implementation, a high speed 5x rate clock is provided as input to the word clock barrel shifter 540 . In one implementation, word clock barrel shifter 540 generates ten distinct phases of the local 1x rate clock. The phase adjustment output of word clock barrel shifter 540 is then inverted and connected to the clock port of flop 530 . The output of flop 530 is inverted and then connected back to the input of flop 530 to generate a phased, half-rate local clock. A phase-adjusted, half-rate local clock is coupled to the select input of a multiplexer 525 . The 1x controller clock is inverted and coupled to the clock input of flop 545 . The output of flop 545 is inverted and then connected back to the input of flop 545 to generate a half rate controller clock. Note that the flops shown in circuit 500 (FIG. 5) may be implemented using any type of suitable registers (eg, type D flip-flops).

Referring now to FIG. 6 , a diagram of one implementation of a circuit 600 for use in a deserializer is shown. In one implementation, circuit 600 is implemented as part of a 2-to-10 deserializer. A 2-to-10 deserializer receives two input bits per input clock cycle and generates 10 output bits per output clock cycle. However, in other implementations, circuit 600 may be modified for use with other types of deserializers that receive other numbers of input bits per cycle and/or produce other numbers of output bits per cycle. In one implementation, circuit 600 performs symbol locking as part of a 2-to-10 deserializer with 1 UI granularity of 2 UI clock phases. In one implementation, symbol locking is performed as part of link training on a link between two separate functional units. Using this technique, incoming deserialized data is reordered into correct symbols with relatively low latency. In one implementation, there are two aspects associated with the use of this symbol locking technique. A first aspect is to have incoming serial data serialized using barrel shift clock phases. A second aspect is to differently pad the incoming serialized data to get the correct symbols.

As shown for circuit 600, the incoming serial data is sampled at both edges of the half-rate clock by flops 615A-B to obtain two bits of data, which are multiplexers 620 and 622. is transmitted to the flops 645 through In one implementation, after deserialization, the data is in the local clock domain and will be moved back to the controller clock domain. This is done by synchronous clock domain crossing as previously described in the discussion of FIG. 4 . In one implementation, the slave's controller clock is derived from a local PLL with a reference clock forwarded from the master.

For operation of circuit 600 , input data is received from channel 605 and coupled to two sets of flops 615A-B. The clock generation unit 610 generates a first clock having a phase of 0 degrees coupled to the input of the flop 615A. Clock generation unit 610 also generates a second clock having 180 degrees of phase coupled to the input of flop 615B. The 180 degree phase second clock coupled to the input of flop 615B is 180 degrees out of phase with the 0 degree phase first clock coupled to the input of flop 615A. The output of flop 615A is denoted as Data1 and is coupled to the “1” inputs of multiplexers 620 and 622 . The output of flop 615B is denoted as Data0 and is coupled to the “0” inputs of multiplexers 620 and 622 . Select signals for multiplexers 620 and 622 are generated by shift data counter 625 that is flipped at odd counts.

Logic 630 to determine if a symbol rotation is necessary generates shift data to rotate the clocks. The output from logic 630 is coupled to a shift data counter 625 and a barrel shifter 635 . The 5x rate clock is also coupled to a barrel shifter 635 . Barrel shifter 635 generates a plurality of 1x rate clocks with different phases based on the 5x rate clock input. A plurality of 1x clocks with different phases generated by barrel shifter 635 are provided to different flops between flops 645 . The output of the flops 645 is coupled to the inputs of the flops 650 . Flops 650 are clocked with the local clock, and the outputs of flops 650 are coupled to flop 655 , which is clocked with the controller clock. For odd shifts, the samples of the “0” flop 645 are delayed, so an additional flop 640 is present to ensure that the data is not overwritten by the incoming bits.

Referring now to FIG. 7 , a timing diagram 700 using the deserializer's barrel shifter to perform symbol locking is shown. Timing diagram 700 is intended to show an example of the timing of input serial data sampled using circuit 600 (FIG. 6). In one implementation, data from samplers is multiplexed as 2 bits of data to achieve a 0/1 UI delay in multiplexer selection as shown in timing diagram 700 . Two bits of data are sequentially filled into a 10-bit register with staggered clock phases. From the 10-bit register, the output is sampled with a local clock. The deserialized data is then analyzed to infer whether the data needs to be rotated to achieve correct symbol timing. As shown in row 710 for an illustration of timing diagram 700, the incoming data is sampled at a7:0 bits and x9:8 bits with the original, unphased clock timing, and "a" is the current symbol and "x" is the previous symbol. In order to have the correct symbol, the goal is to sample the input data with a9:0 bits. As shown in row 710, the next symbol is sampled with b7:0 bits and a9:8 bits.

Referring now to FIG. 8 , a timing diagram 800 is shown at a point in time after the barrel shifter has performed a single step of symbol rotation. Timing diagram 800 is intended to represent the timing of circuit 600 (of FIG. 6 ) for one particular implementation after a single symbol rotation step has been performed. The difference between timing diagram 800 and timing diagram 700 (of FIG. 7 ) represents the effect of performing symbol rotation. In the timing diagram 800, the phase has been shifted relative to the clocks of the odd registers. Register 9 gets the phase timing from previous register 0, register 1 gets the phase timing from previous register 2, and register 3 gets the phase timing from previous register 4. Thus, half of the registers have clocks shifted right by 2 UI. The local clock still remains the same while half of the clocks in the register are shifted right. After the 2 UI phase shift, a8:0 and x9 are the sampled data as shown in row 810 . For odd shifts, the sample from flop 0 is delayed, so there is an additional flop 0_delay so the data is not overwritten with the latest incoming bit a9.

Referring now to FIG. 9 , a timing diagram 900 is shown at a point in time after the barrel shifter has performed symbol rotation by a second step. Timing diagram 900 is intended to represent circuit 600 (of FIG. 6 ) after the clock phase has been shifted by a second symbol rotation step for one particular implementation. The difference between timing diagram 900 and timing diagram 800 (of FIG. 8 ) illustrates the effect of performing the second symbol rotation step. In the example initially shown in timing diagram 700 (of FIG. 7 ), two symbol rotation steps are needed to sample the correct symbols. Thus, the first phase clock phases of half of the registers are rotated twice by the barrel shifter to get the correct symbol. Also, every even rotation causes the local clock to move by two UI steps. For diagram 900, in effect 2 UI shifts occur and the data becomes a9:0 and multiplexers 620 and 622 are shifted back. With this technique, the symbol is locked by moving the symbol window by the correct number of UI steps without latency. As can be seen in diagrams 800 and 900, the phase is shifting to 1 UI by moving the other clock by 2 UIs.

Referring now to FIG. 10 , a state diagram 1000 of one implementation for performing link wide skew correction with minimal latency is shown. In one implementation, a method is implemented according to a state diagram 1000 for link training of a receive physical layer (PHY) interface. This method is performed to achieve synchronous data transmission by determining the position of a symbol eye for each lane of a plurality of lanes, aligning symbols to the lanes, and correcting them skew at the same time. "Symbol Eye" means the data valid period for a symbol based on bit transitions on the data lanes of the link. In the traditional approach, the source-locked clock scheme for skew correction uses additional steps to simplify the timing of capturing the correct symbol, and the additional steps result in relatively high latency. However, using the method associated with the state diagram 1000, the latency is significantly reduced compared to the existing approach. In one implementation, the approach associated with state diagram 1000 uses a symbol locking scheme with a 2-to-10 deserializer of 1 UI granularity of 2 UI clock phases as well as the previously described synchronous clock domain crossing scheme.

Prior to link training, each lane is trained using a synchronous clock domain crossing scheme so that the local clock timing to the controller clock is at the beginning of the timing window (ie, to meet the maximum hold, minimum set time). This step is repeated until the link is established. As used herein, the term “timing window” is defined as the period during which the corresponding data is valid. A timing window is defined by the leading and trailing edges of the data signal. Then, after the link is established, each lane is checked and one of the following options is used. If all lanes do not have the correct symbol, state diagram 1000 moves from reset state 1005 to out-eye state 1015 . At out-eye 1015, each lane is symbol rotated by one step using a barrel shifter, and the controller clock is also rotated by one step to maintain the established timing relationship. Then all lanes are checked. When some lanes are symbol locked, the state diagram moves to state 1010 . The local clocks for the symbol unlocked lanes in state 1010 are shifted by 1 UI. In one implementation, symbol unlocked lanes are shifted by 1 UI using a barrel shifter. Because the controller clock is static, the setup time increases by 1 UI and the hold time increases by 1 UI for the timing relationship between the controller clock and the local clock. This continues until the timing margin window until all lanes are symbol locked. If some lanes are still not symbol locked until the timing margin window is reached, the state diagram 1000 moves back to the reset state 1005 . Otherwise, if all lanes are symbol locked, state diagram 1000 moves to locked state 1030 .

If some lanes are symbol locked in reset state 1005 , state diagram 1000 moves to state 1010 . From state 1010 , state diagram 1000 moves to analysis state 1025 . The state diagram 1000 then moves to a begin_end_eye state 1020 where the local clock is shifted for the symbol aligned lanes. This method is used until the end of the timing window (ie, minimum hold time, maximum set time). At the end of the timing window, all locked lanes and the controller clock are rotated to compensate for the missing rotations. When a new locked lane is locked for a skew corrected symbol, the existing locked lanes and the controller clock except for the most recently locked lane are rotated to compensate for the missing rotations.

Referring now to FIG. 11 , a diagram 1100 of one implementation of symbol eye start points across four communication lanes 1105A-D is shown. Lanes 1105A-D represent any number of lanes included as part of a communication channel. Although four lanes are shown in FIG. 11 , it should be understood that this number is to provide one example for illustration. Other implementations may have other numbers of lanes and may continue to use the techniques described herein to align the symbol eye across multiple lanes. Symbol idles for lanes 1105A-D are indicated by shaded rectangles within lanes 1105A-D.

Due to mismatched lengths of the traces connected to lanes 1105A-D and/or other factors, the symbol eye for each lane will generally be different for other lanes 1105A-D prior to training. An IN_EYE starting point for reset is illustrated at the top of diagram 1100 to represent an example of an implementation of control logic that performs the method associated with state diagram 1000 (of FIG. 10 ). Control logic will attempt to lock the symbol eye for each lane 1105A-D by rotating the local clock for the unaligned lanes. If the control logic reaches the END_EYE point of the lanes before locking on the symbol eye of all lanes, the control logic resets and starts again when the next symbol is received in lanes 1105A-D. The goal of training is to adjust the phases of the local clocks of lanes 1105A-D so that the symbol eye of each lane is aligned with the symbol eyes of the other lanes.

Referring now to FIG. 12 , a diagram of one implementation of a two-entry FIFO circuit 1200 for increasing a timing margin to account for clock jitter is shown. In one implementation, data is received from the channel and provided to a sampler, where the sampler clock is a fast PLL clock (as compared to a word clock). To ensure that the data is sampled correctly, various algorithms are run, from clock data recovery (CDR) that establishes a lock between the incoming serial bit stream and the fast PLL clock. In one implementation, after establishing the lock, the input bitstream is deserialized into parallel data. In one implementation, the input serial bit stream is serialized into 10-bit parallel data. However, in other implementations a different number of parallel data bits are generated.

In one implementation, after deserialization, the data is in the local clock domain and must be moved to the controller clock domain. In one implementation, this is accomplished through the use of circuitry 1200 as well as using the synchronous clock domain crossing technique described previously. In one implementation, the clock domain crossing between the local clock (ie, word clock) and the potentially high jitter controller clock is achieved with the two-entry FIFO circuit 1200 . A half-rate local clock is used as the write pointer and a half-rate version of the controller clock serves as the read pointer. Both the write pointer and the local clock are generated from a common high-speed clock. In one implementation, the write pointer placement is adjusted to 1 UI resolution.

In one implementation, the input serial data is coupled to the inputs of flops 1205A-N. In one implementation, the input data includes 10 input lanes. However, it should be understood that other numbers of input lanes may be supported by circuit 1200 by adjusting the number of flops 1205A-N and the bit width of other components of circuit 1200 in other implementations. In one implementation, the word clock barrel shifter 1207 receives the high speed 5x rate clock that the word clock barrel shifter 1207 uses to generate a 1x rate clock output with 5 distinct phases and 2 UI resolution. This 1x rate clock with different phases is coupled to the clock port of flops 1205A-N. Data inputs to flops 1205A-N are sampled using a phase shift clock.

In one implementation, outputs from flops 1205A-N are coupled to input ports of flops 1210 . The word clock barrel shifter 1207 also generates a local lx rate clock coupled to the clock ports of the flops 1210 . The outputs of flops 1210 are coupled to input ports of flops 1215 and 1220 . A high speed 5x rate clock is also coupled to the write pointer generator 1240 . Write pointer generator 1240 generates a half rate local clock that is coupled to the clock ports of flops 1215 . The half rate local clock of write pointer generator 1240 is negated and coupled to the clock ports of flops 1220 . The outputs of flops 1215 are coupled to the “0” input of multiplexer 1225 , while the outputs of flops 1220 are coupled to the “1” input of multiplexer 1225 . The half rate controller clock generated by flops 1245 is coupled to the select port of multiplexer 1225 . The output lanes of multiplexer 1225 are coupled to input ports of flops 1235 . The 1x rate controller clock is coupled to the clock ports of flops 1235 . Parallel data outputs from flops 1235 are provided to a controller (not shown) or other component for further processing.

Referring now to FIG. 13 , shown is an implementation of a method 1300 of performing training to align a local clock with a global clock. For discussion purposes, the steps of this implementation and the steps of FIG. 14 are shown sequentially. It is noted, however, that in various implementations of the described method, one or more of the described elements are simultaneously performed in a different order than shown or are omitted entirely. Other additional elements are done as desired. Any of the various systems or apparatus described herein are configured to implement method 1300 .

The circuitry receives a global clock signal and a data signal (block 1305). Note that the global clock may also be referred to herein as a “controller clock”. In some implementations, the circuitry receives a plurality of global clocks and a plurality of data signals. In one implementation, the global clock and data signals are generated in a functional unit separate from the receive functional unit. The circuitry also generates a local clock signal (block 1310). For example, in one implementation, the circuit generates a local clock signal using a local PLL.

The circuit sweeps the local clock across phases in 1 UI steps with a barrel shifter while sampling the local clock into a register clocked by the global clock to detect an edge transition (block 1315). In one implementation, the output of the register is coupled to control logic that detects an edge transition. In one implementation, the control logic includes a finite state machine (FSM). In one implementation, the edge transition is a rising edge transition (ie, from low voltage to high voltage). Next, control logic determines that the local clock is aligned with the global clock in response to detecting the edge transition (block 1320). The phase of the local clock is then adjusted relative to the global clock to meet the setup and hold timing requirements (block 1325). Next, the data signal is sampled using a phased local clock (block 1330). The sampled data is then provided to a subsequent step for further processing and/or storage (block 1335). In one implementation, the sampled data is provided to a deserializer. After block 1335 , method 1300 ends.

Referring now to FIG. 14 , an implementation of a method for achieving synchronous cross-domain crossing for a plurality of lanes is shown. The circuitry receives a plurality of data signals and a plurality of corresponding global clock signals (block 1405). The circuitry also generates a plurality of local clock signals (block 1410). For example, in one implementation, the circuit uses a different local PLL to generate each local clock signal. The circuit sweeps each local clock over phases of 1 UI steps with a barrel shifter while sampling the local clock into a register clocked by the corresponding global clock to detect an edge transition (block 1415). In one implementation, the output of the register is coupled to control logic that detects an edge transition. In one implementation, the control logic includes a finite state machine (FSM). In one implementation, the edge transition is a rising edge transition (ie, a logic “0” to a logic “1”).

Next, control logic determines that each local clock is aligned with a corresponding global clock in response to detecting the edge transition (block 1420). The phase of each local clock is then adjusted relative to the corresponding global clock to meet the set and hold timing requirements (block 1425). Next, each data signal is sampled using a corresponding phase-adjusted local clock (block 1430). The sampled data is then provided to a subsequent step for further processing and/or storage (block 1435). In one implementation, the sampled data is provided to a deserializer. After block 1435 , method 1400 ends.

Referring now to FIG. 15 , an implementation of a method 1500 for skew correction across a plurality of lanes of reduced latency is shown. Each lane of the plurality of lanes is trained (ie, maximum hold, minimum set time) to synchronize each local clock with a global clock at the beginning of a timing window (block 1505). In one implementation, method 1400 (of FIG. 14 ) is performed to implement block 1505 . Next, the symbol timing of each lane is ascertained (block 1510). If no lanes have the correct symbol alignment (conditional block 1515, “no lane” bridge), then each lane is a symbol rotated by a single step (block 1520). In one implementation, the symbol for rotating each lane in a single step involves shifting all other clocks (of the barrel shifter generated clocks of lanes of staggered phases) by a single unit interval. Barrel shifter generated clocks of staggered phases are provided to a first column of flops that deserialize the captured data samples in the lane. After block 1520 , the method 1500 returns to block 1510 .

If some of the lanes have the correct symbol alignment (conditional block 1515, “some lanes” bridge), then the unlocked lanes are symbol rotated in a single step (block 1525). In one implementation, blocks 1520 and 1525 are performed using circuit 600 (of FIG. 6 ). After block 1525, when the end of the timing window is reached (conditional block 1530, “Yes” leg), all locked lanes and the global clock are rotated to compensate for the missed rotation (block 1535). After block 1535 , the method 1500 returns to block 1510 . If the end of the timing window has not been reached (conditional block 1530 , a “No” leg), the method 1500 returns to block 1525 . If all lanes have the correct symbol alignment (conditional block 1515, “all lanes”), the method 1500 ends.

Referring now to FIG. 16 , a block diagram illustrating one implementation of a non-transitory computer-readable storage medium 1600 that stores a circuit representation 1605 is shown. In one implementation, circuit manufacturing system 1610 processes circuit representation 1605 stored in non-transitory computer-readable storage medium 1600 and based on circuit representation 1605 any number of integrated circuits 1615A-N. ) is manufactured.

The non-transitory computer-readable storage medium 1600 may include any of a variety of suitable types of memory devices or storage devices. Media 1600 may be an installation medium (eg, a thumb drive, CD-ROM), computer system memory, or random access memory (eg, DRAM, DDR RAM, SRAM, EDO RAM, Rambus). RAM), non-volatile memory (eg, flash, magnetic media, hard drive, optical storage), registers, or other type of memory element. Media 1600 may include other types of non-transitory memory, as well as any combination thereof. Media 1600 may include two or more memory media residing in different locations (eg, on other computer systems coupled through a network).

In various implementations, circuit representation 1605 may be configured in any of a variety of suitable computer languages including, but not limited to, hardware description languages such as VHDL, Verilog, SystemC, SystemVerilog, RHDL, and the like. is specified using Circuit representation 1605 is usable by circuit manufacturing system 1610 to fabricate at least a portion of one or more of integrated circuits 1615A-N. The format of the circuit representation 1605 may be recognized by the at least one circuit manufacturing system 1610 . In some implementations, circuit representation 1605 includes one or more cell libraries that specify the composition and/or layout of integrated circuits 1615A-N.

Circuit fabrication system 1610 includes any of a variety of suitable elements configured to fabricate integrated circuits. This may include, for example, an element for depositing a semiconductor material (eg, a wafer that may include a masking), an element for removing material, an element for changing the shape of the deposited material, an element for changing the material ( for example, using material doping or UV treatment to change the dielectric constant), and the like. The circuit manufacturing system 1610 may also perform testing of the manufactured circuit for correct operation.

In various implementations, the integrated circuits 1615A-N operate according to the circuit design specified by the circuit representation 1605 , which may include performing the functions described herein. For example, the integrated circuits 1615A-N may include any of the various elements shown in the circuits illustrated herein and/or multiple instances of the circuit illustrated herein. In addition, the integrated circuits 1615A-N, along with other components, may perform various functions described herein. For example, the integrated circuits 1615A-N may be coupled to a voltage supply circuit configured to provide a supply voltage (eg, as opposed to including the voltage supply itself). Also, the functions described herein may be performed by multiple connected integrated circuits.

As used herein, "a circuit representation specifying the design of a circuit??" The phrase in the form does not imply that the circuit in question must be built to fulfill the element. Rather, this phrase indicates that the circuit representation describes a circuit that, when manufactured, includes components configured or designated to perform the indicated operations.

In various implementations, program instructions are used to implement the methods and/or mechanisms described herein. For example, program instructions that describe the operation or design of hardware are written. In one implementation, these program instructions are expressed in a hardware design language (HDL), such as Verilog. In various implementations, the program instructions are stored in any of a variety of non-transitory computer-readable storage media. The storage medium is accessible by the computing system during use to provide program instructions to the computing system for circuit manufacturing, program execution, or the like. Generally speaking, such a computing system includes at least one memory and one or more processors configured to execute program instructions.

It should be emphasized that the foregoing implementations are merely non-limiting examples of implementations. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed to cover all such variations and modifications.

Claims (20)

in the circuit,
a plurality of communication lanes; and
a control logic comprising:
determine whether each lane of the plurality of communication lanes has correct symbol alignment;
in response to determining that all lanes of the plurality of communication lanes have incorrect symbol alignment, symbol rotate each lane in a single step;
in response to determining that some but not all of the plurality of communication lanes have correct symbol alignment, symbol rotate lanes with incorrect symbol alignment in a single step; And
in response to determining that all lanes of the plurality of communication lanes have correct symbol alignment, sample the plurality of data signals using the plurality of local clocks to generate a plurality of data sequences; Circuit. The control logic of claim 1 , wherein in response to determining that an end of a first timing window has been reached before all lanes of the plurality of communication lanes have correct symbol alignment:
symbol rotate lanes with correct symbol alignment and adjust the phase of the corresponding global clock to compensate for missing symbol rotation; And
and determine, at the beginning of a second timing window, whether each lane of the plurality of communication lanes has correct symbol alignment. The method of claim 1 , wherein the circuit comprises:
a barrel shifter for each lane of the plurality of communication lanes, wherein each barrel shifter is configured to generate a plurality of clocks having staggered phases to serialize input data samples; and
and a plurality of columns of registers for each lane, wherein the plurality of clocks having staggered phases are coupled to a first column of registers to sample the input data samples. 4. The method of claim 3, wherein outputs from the first column of registers are coupled to inputs of a second column of registers, each register of the second column of registers clocked by a corresponding local clock of the lane. , Circuit. 4. The method of claim 3, wherein symbol rotating the lane by the single step comprises shifting the phase of all other ones of the plurality of clocks having staggered phases by a single unit interval. Circuit. 2. The method of claim 1, wherein, prior to determining whether each lane of the plurality of lanes has correct symbol alignment, the control logic synchronizes each lane to synchronize its local clock with a corresponding global clock at the beginning of a timing window. A circuit configured to train. 7. The method of claim 6, wherein training each lane to synchronize the local clock of the lane with the corresponding global clock at the beginning of the timing window comprises:
sampling, with a given register, the local clock with the corresponding global clock;
using a given barrel shifter, sweeping the local clock across phases until an edge transition is detected;
determining that the local clock is aligned with the corresponding global clock in response to detecting the edge transition; and
and adjusting the phase of the local clock to meet setup and maintenance timing requirements for sampling a data signal on the lane. In the method,
determining whether each lane of the plurality of communication lanes has correct symbol alignment;
symbol rotation of each lane in a single step in response to determining that all lanes of the plurality of communication lanes have incorrect symbol alignment;
in response to determining that some but not all of the plurality of communication lanes have correct symbol alignment, symbol rotating lanes with incorrect symbol alignment in a single step; and
in response to determining that all lanes of the plurality of communication lanes have correct symbol alignment, sampling a plurality of data signals using a plurality of local clocks to generate a plurality of data sequences. 9. The method of claim 8, wherein in response to determining that an end of a first timing window has been reached before all lanes of the plurality of communication lanes have correct symbol alignment:
symbol rotation of lanes with correct symbol alignment and adjusting phase of a corresponding global clock to compensate for missing symbol rotation; and
at the beginning of a second timing window, determining whether each lane of the plurality of communication lanes has correct symbol alignment. 9. The method of claim 8,
generating, with a barrel shifter for each lane of the plurality of communication lanes, a plurality of clocks having staggered phases to deserialize input data samples; and
receiving, by a first column of registers for each lane, a plurality of clocks having the staggered phases to sample the input data samples. 11. The method of claim 10, further comprising receiving, at inputs of a second column of registers, outputs from a first column of registers, each register in the second column of registers having a corresponding local in the lane. clocked by a clock. 11. The method of claim 10, wherein symbol rotating the lane in a single step comprises shifting the phase of all other ones of the plurality of clocks having staggered phases by a single unit interval. 9. The method of claim 8, wherein before determining whether each lane of the plurality of lanes has correct symbol alignment, the method trains each lane to synchronize its local clock with a corresponding global clock at the beginning of a timing window. A method comprising the step of 14. The method of claim 13, wherein training each lane to synchronize the local clock of the lane with the corresponding global clock at the beginning of the timing window comprises:
sampling the local clock with the corresponding global clock with a given register;
using a given barrel shifter, sweeping the local clock across phases until an edge transition is detected;
determining that the local clock is aligned with the corresponding global clock in response to detecting the edge transition; and
adjusting the phase of the local clock to meet setup and maintenance timing requirements for sampling a data signal on the lane. In the system,
a first functional unit;
a channel having a plurality of communication lanes;
a second functional unit coupled to the first functional unit via the channel;
The first functional unit comprises:
determine whether each lane of the plurality of communication lanes has correct symbol alignment;
in response to determining that all lanes of the plurality of communication lanes have incorrect symbol alignment, symbol rotate each lane in a single step;
in response to determining that some but not all of the plurality of communication lanes have correct symbol alignment, symbol rotate lanes with incorrect symbol alignment in a single step; And
and in response to determining that all lanes of the plurality of communication lanes have correct symbol alignment, sample the plurality of data signals using the plurality of local clocks to generate the plurality of data sequences. 16. The method of claim 15, wherein in response to determining that an end of a first timing window has been reached before all lanes of the plurality of communication lanes have correct symbol alignment, the first functional unit comprises:
symbol rotate lanes with correct symbol alignment and adjust the phase of the corresponding global clock to compensate for missing symbol rotation; And
and determine, at the beginning of a second timing window, whether each lane of the plurality of communication lanes has correct symbol alignment. 16. The method of claim 15, wherein the first functional unit comprises:
a barrel shifter for each lane of the plurality of communication lanes, wherein each barrel shifter is configured to generate a plurality of clocks having staggered phases to serialize input data samples; and
further comprising a plurality of columns of registers for each lane, wherein the plurality of clocks having staggered phases are coupled to a first column of registers to sample the input data samples. 18. The method of claim 17, wherein outputs from the first column of registers are coupled to inputs of a second column of registers, wherein each register in the second column of registers is clocked by a corresponding local clock of the lane. , system. 18. The method of claim 17, wherein symbol rotating the lane by the single step comprises shifting the phase of all other clocks of the plurality of clocks having staggered phase by a single unit interval. system. 16. The method of claim 15, wherein, prior to determining whether each lane of the plurality of lanes has correct symbol alignment, the first functional unit is configured to synchronize each lane's local clock with a corresponding global clock at the beginning of a timing window. A system configured to train a lane.

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