KR20210086021A - Display device - Google Patents

Abstract

A display device according to one embodiment of the present invention comprises: a substrate including a display area and a non-display area outside the display area; a planarization layer disposed on the substrate and having an opening in a portion thereof; a plurality of banks spaced apart from each other on the planarization layer; a first electrode disposed on the planarization layer disposed on one side of the opening; a light emitting layer disposed on a portion of the opening and a portion of the plurality of banks; and a second electrode disposed on a portion of the plurality of banks and the opening. The plurality of banks include a first bank disposed to cover an end of the first electrode, a second bank disposed on the planarization layer disposed on the other side of the opening, and a third bank. The upper surface of the third bank can be disposed at a lower position than the upper surface of the second bank. The present invention can reduce scratches by a mask and the inflow of foreign substances.

Description

display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a display device having improved reliability.

Recently, as we enter the information age in earnest, the field of display that visually expresses electrical information signals has developed rapidly, and in response to this, various flat display devices with excellent performance of thinness, light weight, and low power consumption (Flat Display) Device) has been developed and is rapidly replacing the existing cathode ray tube (CRT).

Specific examples of the flat panel display include a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), a plasma display (PDP), and an electrowetting display (EWD). have. In particular, an organic light emitting diode display is a next-generation display device having self-luminous characteristics, and has superior characteristics in terms of viewing angle, contrast, response speed, power consumption, and the like, compared to a liquid crystal display device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of reducing defects caused by scratches or foreign substances caused by a mask.

Another object of the present invention is to provide a display device with improved reliability.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area outside the display area, a planarization layer disposed on the substrate and having an opening in a portion thereof, and a planarization layer spaced apart from each other on the planarization layer. a plurality of banks, a first electrode disposed on the planarization layer disposed at one side of the opening, a light emitting layer disposed on a portion of the opening and a portion of the plurality of banks, and a portion of the plurality of banks and a second electrode disposed on the opening The plurality of banks includes a first bank disposed to cover the end of the first electrode, a second bank disposed on the planarization layer disposed on the other side of the opening, and a third bank, The upper surface may be disposed at a lower position than the upper surface of the second bank.

A display device according to another exemplary embodiment includes a substrate including a display area and a non-display area outside the display area, a first planarization layer disposed on the substrate to overlap the display area, and a first planarization layer disposed to be spaced apart from the first planarization layer. 2 planarization layer, a first electrode disposed on the first planarization layer, a first bank disposed on a portion of the first electrode, a second bank disposed adjacent to an end of the second planarization layer on the second planarization layer, a second planarization layer A third bank spaced apart from the second bank on the second planarization layer and having a top surface disposed at a lower position than the top surface of the second bank, a light emitting layer disposed between the first planarization layer and the second planarization layer and on the first bank, and It may include a second electrode disposed on the light emitting layer and the second bank.

The details of other embodiments are included in the detailed description and drawings.

According to the present invention, it is possible to reduce scratches by the mask and the inflow of foreign substances.

In addition, the present invention can improve the reliability of the display device.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is a plan view of a display device according to an exemplary embodiment.
FIG. 2 is a cross-sectional view taken along II-II′ of FIG. 1 .
3A to 3C are flowcharts illustrating a manufacturing process of a display device according to an exemplary embodiment.

Advantages and features of the present invention, and a method of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'include', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of another device.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are shown for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an exemplary embodiment. FIG. 2 is a cross-sectional view taken along II-II′ of FIG. 1 . In FIG. 1 , only the first substrate 101 and the plurality of sub-pixels SP among various components of the display device 100 are illustrated for convenience of description.

The first substrate 101 is a support member for supporting other components of the display device 100 , and may be made of an insulating material. For example, the first substrate 101 may be made of glass or resin. In addition, the first substrate 101 may include a polymer or plastic such as polyimide (PI), or may be made of a material having flexibility.

The first substrate 101 includes a display area AA and a non-display area NA.

The display area AA is an area for displaying an image. A plurality of sub-pixels SP for displaying an image and a circuit unit for driving the plurality of sub-pixels SP may be disposed in the display area AA. The circuit unit may include various thin film transistors, capacitors, and wires for driving the sub-pixels SP. For example, the circuit unit may include various components such as a driving thin film transistor, a switching thin film transistor, a storage capacitor, a gate line, and a data line, but is not limited thereto.

The non-display area NA is an area in which an image is not displayed, and is an area in which various wirings, driving ICs, and the like for driving the sub-pixels SP disposed in the display area AA are disposed. For example, various driving ICs such as a gate driver IC and a data driver IC may be disposed in the non-display area NA.

1 illustrates that the non-display area NA surrounds the display area AA, the non-display area NA may be an area extending from one side of the display area AA, but is not limited thereto.

A plurality of sub-pixels SP are disposed in the display area AA of the first substrate 101 . Each of the plurality of sub-pixels SP is an individual unit emitting light, and a light emitting device and a driving circuit are formed in each of the plurality of sub-pixels SP. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, but is not limited thereto, and the plurality of sub-pixels SP may further include a white sub-pixel. .

1 and 2 , a display device 100 according to an exemplary embodiment includes a first substrate 101 , a thin film transistor 120 , a planarization layer 107 , a light emitting device 130 , and a bank ( 110 ), a dam 180 , an encapsulation layer 150 , a filling layer 160 , and a second substrate 170 .

Referring to FIG. 2 , a first substrate 101 is a substrate for supporting and protecting various components of the display device 100 . The first substrate 101 may be made of glass or a plastic material having flexibility. When the first substrate 101 is made of a plastic material, it may be made of, for example, polyimide (PI). However, it is not limited thereto.

A buffer layer 103 is disposed on the first substrate 101 . The buffer layer 103 may improve adhesion between the layers formed on the buffer layer 103 and the first substrate 101 , and block alkali components leaking from the first substrate 101 . The buffer layer 103 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. The buffer layer 103 may be omitted based on the type and material of the first substrate 101 , the structure and type of the thin film transistor 120 , and the like.

The thin film transistor 120 is disposed on the first substrate 101 and the buffer layer 103 . The thin film transistor 120 may be used as a driving element of the display device 100 . The thin film transistor 120 includes a gate electrode 121 , an active layer 122 , a source electrode 123 , and a drain electrode 124 . In the display device 100 according to an embodiment of the present invention, in the thin film transistor 120 , an active layer 122 is disposed on a gate electrode 121 , and a source electrode 123 and a drain are disposed on the active layer 122 . As a structure in which the electrode 124 is disposed, the thin film transistor having a bottom gate structure in which the gate electrode 121 is disposed at the bottom, but is not limited thereto.

The gate electrode 121 of the thin film transistor 120 is disposed on the first substrate 101 and the buffer layer 103 . The gate electrode 121 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and It may be any one of copper (Cu), an alloy of two or more, or a multilayer thereof, but is not limited thereto.

A gate insulating layer 105 is disposed on the gate electrode 121 . The gate insulating layer 105 is a layer for electrically insulating the gate electrode 121 and the active layer 122 and may be made of an insulating material. For example, the gate insulating layer 105 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is limited thereto. it is not going to be

An active layer 122 is disposed on the gate insulating layer 105 . The active layer 122 is disposed to overlap the gate electrode 121 . For example, the active layer 122 may be formed of an oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or an organic semiconductor. can

A source electrode 123 and a drain electrode 124 are disposed on the active layer 122 . The source electrode 123 and the drain electrode 124 are spaced apart from each other on the same layer. The source electrode 123 and the drain electrode 124 may be electrically connected to the active layer 122 in a manner in contact with the active layer 122 . The source electrode 123 and the drain electrode 124 may be formed of various metal materials, for example, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), It may be any one of neodymium (Nd) and copper (Cu), an alloy of two or more thereof, or a multilayer thereof, but is not limited thereto.

A passivation layer 109 is disposed on the thin film transistor 120 . The passivation layer 109 may be formed of a single layer of inorganic silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto. The passivation layer 109 may extend to the non-display area NA to cover various wirings disposed in the non-display area NA. However, the passivation layer 109 may be omitted based on the structure and type of the thin film transistor 120 .

A planarization layer 107 is disposed on the thin film transistor 120 . The planarization layer 107 planarizes an upper portion of a partial region of the first substrate 101 . For example, the planarization layer 107 may be disposed in a portion of the display area AA and the non-display area NA.

The planarization layer 107 may be composed of a single layer or a multilayer, and may be made of an organic material. For example, the planarization layer 107 may be formed of an acryl-based organic material, but is not limited thereto.

The planarization layer 107 includes a first planarization layer 107a, a second planarization layer 107b, and an opening 107c.

The first planarization layer 107a may be disposed in a portion of the display area AA and the non-display area NA. The first planarization layer 107a may be disposed on one side of the opening 107c and include a contact hole for electrically connecting the thin film transistor 120 and the light emitting device 130 to each other.

The second planarization layer 107b is disposed to be spaced apart from the first planarization layer 107a. That is, the second planarization layer 107b may be disposed in the non-display area NA and disposed at the other side of the opening 107c. Accordingly, the second planarization layer 107b may be disposed to surround the first planarization layer 107a.

The opening 107c may be disposed between the first planarization layer 107a and the second planarization layer 107b. The opening 107c may be disposed in the non-display area NA to expose a portion of the passivation layer 109 . Also, the opening 107c may be disposed to overlap the link wiring 106 , but is not limited thereto.

In some embodiments, the planarization layer 107 does not include the opening 107c but may include a groove. That is, the planarization layer 107 connects the first planarization layer 107a and the second planarization layer 107b, and forms a portion thinner than the first planarization layer 107a and the second planarization layer 107b through the opening ( 107c) may be further included.

The light emitting device 130 is disposed on the planarization layer 107 . The light emitting device 130 is a self-emitting device that emits light, and may be driven by receiving a voltage from the thin film transistor 120 or the like. The light emitting device 130 includes a first electrode 131 , a light emitting layer 132 , and a second electrode 133 .

The first electrode 131 is disposed separately for each sub-pixel on the first planarization layer 107a. The first electrode 131 is electrically connected to the thin film transistor 120 through a contact hole formed in the first planarization layer 107a. The first electrode 131 is made of a conductive material capable of supplying holes to the emission layer 132 . For example, the first electrode 131 may include tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (Indium Zinc Tin). The reflective layer may be formed of a transparent conductive material such as oxide (ITZO) and a material having excellent reflectivity such as silver (Ag) or a silver alloy (Ag alloy), but is not limited thereto.

A plurality of banks 110 are disposed on the planarization layer 107 . The plurality of banks 110 are insulating layers for separating adjacent sub-pixels. The plurality of banks 110 may be formed of an organic insulating material.

The plurality of banks 110 includes a first bank 110a, a second bank 110b, and a third bank 110c. The first bank 110a, the second bank 110b, and the third bank 110c may be disposed to be spaced apart from each other.

The first bank 110a is disposed on the first planarization layer 107a. The first bank 110a may be disposed in a portion of the display area AA and the non-display area NA to cover a portion of the first electrode 131 . An end of the first bank 110a may be disposed adjacent to an end of the first planarization layer 107a, but is not limited thereto.

The first bank 110a may have an upper surface 107aa and two side surfaces 107ab and 107ac. For example, the two side surfaces 107ab and 107ac of the first bank 110a are disposed on the first surface 107ab adjacent to the end of the first planarization layer 107a and the end of the first electrode 131 . It may be composed of a second surface 107ac. In this case, the inclinations of the first surface 107ab and the second surface 107ac may be different from each other. For example, the slope of the first surface 107ab may be steeper than the slope of the second surface 107ac. Accordingly, when the light emitting layer 132 deposition process is performed, the light emitting layer 132 is not deposited on the first surface 107ab of the first bank 110a, and the light emitting layer 132 is formed on the upper surface 107aa and the second surface 107ac. 132) may be deposited.

The second bank 110b is disposed on the second planarization layer 107b. That is, the opening 107c of the planarization layer 107 may be disposed between the second bank 110b and the first bank 110a. The second bank 110b may be disposed adjacent to the opening 107c to cover an end of the connection electrode 112 .

The second bank 110b may have an upper surface 107ba and two side surfaces 107bb and 107bc. For example, the two side surfaces 107bb and 107bc of the second bank 110b are disposed on the first surface 107bb adjacent to the end of the second planarization layer 107b and the end of the connection electrode 112 . It may be composed of the second surface 107bc. In this case, the inclinations of the first surface 107bb and the second surface 107bc may be different from each other. For example, the inclination of the first surface 107bb may be gentler than the inclination of the second surface 107bc. However, the present invention is not limited thereto, and the inclination of the first surface 107bb and the second surface 107bc may be the same, or the inclination of the second surface 107bc may be gentler than that of the first surface 107bb.

The third bank 110c is disposed on the second planarization layer 107b to be spaced apart from the second bank 110b. The third bank 110c may be disposed on the connection electrode 112 .

The third bank 110c may have an upper surface 110ca and two side surfaces 110cb. For example, the two side surfaces 110cb of the third bank 110c may connect the upper surface 110ca of the third bank 110c and the upper surface of the connection electrode 112, respectively. In this case, the slope of the two side surfaces 110cb of the third bank 110c may be the same, but is not limited thereto, and the slopes of the two side surfaces 110cb of the third bank 110c may be different from each other. .

The height of the third bank 110c may be lower than the height of the second bank 110b. That is, the top surface 110ca of the third bank 110c may be disposed at a lower position than the top surface 110ba of the second bank 110b. For example, when the emission layer 132 deposition process is performed, the mask M1 may be disposed on the second bank 110b. At this time, when the height of the upper surface 110ca of the third bank 110c is equal to the height of the upper surface 110ba of the second bank 110b, the mask M1 is also applied to the upper surface 110ca of the third bank 110c. can be contacted That is, the contact area between the mask M1 and the bank 110 increases, so that there is a high possibility that a foreign material is generated due to the contact between the mask M1 and the bank 110 . Accordingly, the upper surface 110ca of the third bank 110c is disposed at a lower position than the upper surface 110ba of the second bank 110b, thereby reducing the contact area between the mask M1 and the bank 110, It is possible to reduce the generation of foreign substances by the mask M1 and the bank 110 .

A light emitting layer 132 is disposed on the first electrode 131 , a portion of the first bank 110a , and a portion of the passivation layer 109 . That is, the light emitting layer 132 is a portion of the top surface of the passivation layer 109 exposed through the opening 107c, the top surface 107aa and the second surface 107ac of the first bank 110a, and the first electrode 131 . It may be disposed to be in contact with the upper surface. In this case, the light emitting layer 132 disposed on a portion of the upper surface of the passivation layer 109 may not be connected to the light emitting layer 132 disposed on the upper surface of the first bank 110a while being spaced apart from each other. For example, when the light emitting layer 132 disposed on a portion of the upper surface of the passivation layer 109 and the light emitting layer 132 disposed on the first bank 110a are connected to each other, foreign matter introduced into the opening 107c It flows into the light emitting layer 132 disposed on the first bank 110a, and the light emitting layer 132 may be damaged. Accordingly, the emission layer 132 disposed on the first bank 110a may not be connected to the emission layer 132 on the passivation layer 109 . Meanwhile, in FIG. 2 , it is illustrated that the light emitting layer 132 is not disposed on the side surface of the first planarization layer 107a, but when the side surface of the first planarization layer 107a has a gentle slope, the light emitting layer 132 is formed on the second 1 It may also be disposed on a portion of the side surface of the planarization layer 107a. That is, a portion of the passivation layer 109 and the light emitting layer 132 disposed on the side surface of the first planarization layer 107a are formed from the first surface of the first bank 110a to the upper surface and the second surface of the first bank 110a. and spaced apart from the light emitting layer 132 disposed on the first electrode 131 .

The light emitting layer 132 may be composed of one light emitting layer 132 , or may have a structure in which a plurality of light emitting layers 132 emitting light of different colors are stacked. The emission layer 132 may further include a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Referring to FIG. 2 , the emission layer 132 is illustrated as being disposed as one layer over the entire sub-pixel, but the present invention is not limited thereto, and may be disposed separately in each sub-pixel. In addition, the emission layer 132 may be an organic emission layer made of an organic material, but is not limited thereto.

A second electrode 133 is disposed on the emission layer 132 , the planarization layer 107 , and the second bank 110b. Specifically, the second electrode 133 is a portion of the passivation layer 109 in which the emission layer 132 is not disposed in the opening 107c, the upper surface of the emission layer 132, the side surface of the second planarization layer 107b, and the second It may be disposed on the top surface 110ba and side surfaces 110ab and 110ac of the bank 110b and the side surface of the first planarization layer 107a. In addition, an end of the second electrode 133 may be disposed between the second bank 110b and the third bank 110c, but is not limited thereto. The second electrode 133 is made of a conductive material capable of supplying electrons to the emission layer 132 . For example, the second electrode 133 may be formed of a metal material such as copper (Cu), aluminum (Al), silver (Ag), or magnesium-silver alloy (MgAg). In addition, the second electrode 133 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (Zinc Oxide, ZnO) and tin oxide (Tin Oxide, TO)-based transparent conductive oxide or ytterbium (Yb) alloy, but is not limited thereto. Referring to FIG. 2 , the second electrodes 133 disposed in each sub-pixel are illustrated as being connected to each other, but like the first electrode 131 may be disposed separately for each sub-pixel, but is not limited thereto.

When the second electrode 133 is connected and disposed in each sub-pixel, the second electrode 133 may be disposed outside the non-display area NA. In this case, the second electrode 133 is disposed on the first substrate 101 through the connection electrode 112 disposed to cover the top and side surfaces of the second planarization layer 107b disposed on the outer portion of the first substrate 101 . It may be connected to the power wiring 114 disposed in the .

An encapsulation layer 150 is disposed on the light emitting device 130 . The encapsulation layer 150 is a sealing member that protects the light emitting device 130 from external moisture, oxygen, impact, and the like. The encapsulation layer 150 may be disposed to cover the entire display area AA in which the light emitting device 130 is disposed, and the encapsulation layer 150 may be a portion of the non-display area NA extending from the display area AA. It can be arranged to cover up to Accordingly, the encapsulation layer 150 may be disposed along the light emitting device 130 and the plurality of banks 110 . The encapsulation layer 150 is made of an inorganic material, for example, may be made of an inorganic material such as silicon nitride (SiNx) or silicon oxynitride (SiON), but is not limited thereto.

The circuit units 104 and 108 are disposed in the non-display area NA. The circuit units 104 and 108 may include various devices such as a switching thin film transistor for driving the light emitting device 130, a thin film transistor for compensation, a capacitor, and the like, and include a gate in panel (GIP) type device and various wirings. may include

The circuit parts 104 and 108 may be formed of the same material in the same process as that of the thin film transistor 120 . For example, the circuit parts 104 and 108 may be formed of the same material as the source electrode 123 and the drain electrode 124 or the gate electrode 121 of the thin film transistor 120 , but are not limited thereto.

A link wiring 106 extending from the circuit portions 104 and 108 is disposed on the buffer layer 103 . The link wiring 106 is disposed in the non-display area NA to connect the circuit units 104 and 108 and the gate wiring disposed in the display area AA. Accordingly, the link wiring 106 may be made of the same material in the same process as the gate electrode 121 of the thin film transistor 120 , but is not limited thereto.

A power supply wiring 114 is disposed outside the circuit portions 104 and 108 . The power wiring 114 may be a low level power VSS and may be disposed on the gate insulating layer 105 .

The power wiring 114 may be formed of the same material in the same process as that of the thin film transistor 120 . For example, the power wiring 114 may be formed of the same material as the source electrode 123 and the drain electrode 124 or the gate electrode 121 of the thin film transistor 120 , but is not limited thereto.

The power wiring 114 may be connected to the second electrode 133 by a connection electrode 112 disposed between the power wiring 114 and the second electrode 133 . In this case, the connection electrode 112 may be formed of the same material in the same process as the first electrode 131 of the light emitting device 130 , but is not limited thereto. In addition, the power wiring 114 may be directly connected to the second electrode 133 of the light emitting device 130 that descends along the side surface of the second bank 110b and the second planarization layer 107b.

A filling layer 160 is disposed on the encapsulation layer 150 . The filling layer 160 may fill the curvature between various structures disposed on the first substrate 101 to planarize the upper portion of the first substrate 101 . In addition, the filling layer 160 may adhere the second substrate 170 to the first substrate 101 . Accordingly, the filling layer 160 may be made of an organic material having an adhesive property, but is not limited thereto.

A second substrate 170 is disposed on the filling layer 160 . The second substrate 170 may be formed to have a size corresponding to that of the first substrate 101 to prevent external moisture from penetrating into the display device 100 .

A dam 180 is disposed between the first substrate 101 and the second substrate 170 . The dam 180 is disposed at the edges of the first substrate 101 and the second substrate 170 to prevent the filling layer 160 from leaking to the outside. Accordingly, the dam 180 may seal the inside of the display device 100 .

Hereinafter, for a more detailed description of a manufacturing process of a display device according to an exemplary embodiment, FIGS. 3A to 3C are also referred to.

3A to 3C are flowcharts illustrating a manufacturing process of a display device according to an exemplary embodiment. 3A is a cross-sectional view illustrating a process of forming the emission layer 132 , FIG. 3B is a cross-sectional view illustrating a process of forming the second electrode 133 , and FIG. 3C is a cross-sectional view of the display device 100 that has been manufactured.

Referring to FIG. 3A , a first mask M1 may be used to perform the process of forming the emission layer 132 . In this case, the first mask M1 may have openings corresponding to portions of the display area AA and the non-display area NA. Accordingly, in order to form the emission layer 132 , the first mask M1 may be disposed to contact the second bank 110b, and an end of the first mask M1 may be disposed on the opening 107c. That is, a process of forming the emission layer 132, for example, a deposition process, may be performed while the first mask M1 is disposed to contact the second bank 110b. Accordingly, the emission layer 132 may be formed on the top surface of the first electrode 131 , the top surface 110aa and the second surface 110ac of the first bank 110a , and a portion of the passivation layer 109 .

In the process of depositing the emission layer 132 , a distance between the first mask M1 and the first bank 110a may be secured. Specifically, since the first bank 110a and the second bank 110b are spaced apart from each other with the opening 107c therebetween, the first mask M1 is disposed on the second bank 110b, One end of the mask M1 may be disposed on the opening 107c. Accordingly, a distance between the end of the first mask M1 and the first bank 110a is secured to minimize contact between the first mask M1 and the light emitting layer 132 formed on the first bank 110a. Therefore, it is possible to minimize the generation of foreign substances due to the contact between the first mask M1 and the first bank 110a.

Also, during the light emitting layer 132 deposition process, the first mask M1 may not contact the upper surface 110ca of the third bank 110c. Specifically, since the top surface 110ca of the third bank 110c is disposed at a lower position than the top surface 110ba of the second bank 110b, during the light emitting layer 132 deposition process, the first mask M1 is applied to the second It may be arranged to contact only the upper surface 110ba of the bank 110b. That is, since the contact area between the first mask M1 and the bank 110 is reduced, generation of foreign matter due to the contact between the first mask M1 and the bank 110 may be reduced.

Next, referring to FIG. 3B , a second mask M2 may be used to perform a process of forming the second electrode 133 . In this case, the second mask M2 may have openings corresponding to portions of the display area AA and the non-display area NA. Accordingly, to form the second electrode 133, the second mask M2 is disposed to contact the third bank 110c, and ends of the second mask M2 have the second bank 110b and the third bank 110b. It may be disposed between 110c. That is, a process of forming the second electrode 133, for example, a deposition process, may be performed while the second mask M2 is disposed to contact the third bank 110c. Accordingly, the second electrode 133 may be formed on the first bank 110a, the second bank 110b, and the alc opening 107a of the first electrode 131 .

In the process of forming the second electrode 133 , a distance between the second mask M2 and the second bank 110b may be secured. Specifically, since the second bank 110b and the third bank 110c are spaced apart from each other, the second mask M2 is disposed on the third bank 110c, and the end of the second mask M2 is It may be disposed between the second bank 110b and the third bank 110c. Accordingly, a distance between the end of the second mask M2 and the second bank 110b is secured, so that contact between the second mask M2 and the second bank 110b can be minimized, and thus, the second It is possible to minimize the generation of foreign substances due to the contact between the mask M2 and the second bank 110b. Next, referring to FIG. 3C , both the light emitting layer 132 forming process and the second electrode 133 forming process are performed. After that, the encapsulation layer 150 and the filling layer 170 may be sequentially disposed on the first substrate 101 . Specifically, the encapsulation layer 150 may be disposed to cover upper portions of the structures disposed on the first substrate 101 along the top surface shape of the structures disposed on the first substrate 101 . Then, the dam 180 is disposed on the edge of the first substrate 101 , and the filling layer 160 is disposed on the encapsulation layer 150 , so that a gap between various structures disposed on the first substrate 101 is formed. The curvature may be filled and the upper portion of the first substrate 101 may be planarized. The display device 100 may be manufactured by disposing the second substrate 170 on the filling layer 160 and the dam 180 to correspond to the first substrate 101 .

In a general display device, a light emitting layer forming process is performed on a single bank structure. However, when the light emitting layer forming process is performed in a single bank structure, the mask makes surface contact with the bank and the contact area of the bank increases, so that the bank may be scratched or foreign matter may be generated due to the contact between the mask and the bank. possibility may increase. Accordingly, the generated foreign material may flow into the display area and cause damage to the display device. In addition, a seam is generated due to a scratching phenomenon occurring in the bank, and the seam may be a penetration path for gas generated in a subsequent process or a path for moisture or the like to easily penetrate from the outside.

Also, there is a possibility that the mask may come into contact with the previously deposited light emitting layer and damage the previously deposited light emitting layer. That is, in the process of depositing a plurality of organic layers constituting the emission layer, a phenomenon may occur in which a mask used to deposit one organic layer and then the next organic layer is in contact with the first deposited organic layer. In this case, the light emitting layer may be damaged in the process of removing the mask after the deposition process is completed, and the electrode and the encapsulation layer deposited on the light emitting layer may also be incompletely deposited. Accordingly, a shim is generated in the light emitting layer, and the shim may be a penetration path for gas generated in a subsequent process or a path through which moisture or the like easily penetrates from the outside. In addition, a white band stain in which the outside of the display area is visually recognized as white may occur due to such a seam.

Accordingly, in the display device 100 according to the exemplary embodiment of the present invention, the plurality of banks 110 are disposed to be spaced apart from each other, and the openings 107c are disposed in the planarization layer 107 to minimize the generation of foreign matter during the process. And even if a foreign material is generated, it is possible to reduce the movement of the generated foreign material. For example, during the process of forming the emission layer 132 and the second electrode 133 , foreign matter may be generated due to the contact between the first mask M1 , the second mask M2 , and the bank 110 . At this time, the foreign material flowing between the first bank 110a and the second bank 110b and between the second bank 110b and the third bank 110c enters the display area AA due to the step difference with the adjacent structure. movement can be reduced. That is, the space between the plurality of banks 110 and the opening 107c may act as an obstacle to reduce the movement of foreign matter. Accordingly, by arranging the plurality of banks 110 to be spaced apart from each other and disposing the openings 107c in the planarization layer 107 to suppress the movement of foreign substances, it is possible to reduce the inflow of foreign substances into the display area AA. , thereby improving the reliability of the display device 100 .

In addition, in the display device 100 according to an embodiment of the present invention, the first bank 110a and the second bank 110b are disposed to be spaced apart from each other so that, during the light emitting layer 132 forming process, the first mask M1 is used. It is possible to reduce foreign matter and damage to the light emitting layer 132 caused by the contact of the first bank 110a with the first bank 110a. For example, in the process of forming the light emitting layer 132 in a structure in which the first bank 110a and the second bank 110b are disposed to be spaced apart from each other, the first mask M1 is disposed on the second bank 110b and an end of the first mask M1 may be disposed on the opening 107c. Accordingly, a distance may be secured between the first mask M1 and the emission layer 132 formed on the first bank 110a. That is, it is reduced that the first mask M1 damages the light emitting layer 132 previously formed on the first bank 110a or that foreign matter is generated due to the contact between the first mask M1 and the first bank 110a. can do. Accordingly, by disposing the first bank 110a and the second bank 110b to be spaced apart, the light emitting layer 132 is damaged by the first mask M1 or foreign substances are removed due to contact with the first mask M1. By reducing the occurrence, reliability of the display device 100 may be improved.

In addition, in the display device 100 according to the exemplary embodiment of the present invention, the contact area between the first mask M1 and the bank 110 is reduced, so that the contact between the first mask M1 and the bank 110 is caused. Generation|occurrence|production of a foreign material can be reduced. Specifically, the upper surface 110ca of the third bank 110c may be disposed at a lower position than the upper surface 110ba of the second bank 110b. Accordingly, during the process of forming the emission layer 132 , the first mask M1 may be disposed to contact the top surface 110ba of the second bank 110b and to contact the top surface 110ca of the third bank 110c . may not Accordingly, the upper surface 110ca of the third bank 110c is disposed at a lower position than the upper surface 110ba of the second bank 110b, thereby reducing the contact area between the first mask M1 and the bank 110 . Thus, it is possible to reduce the occurrence of foreign substances due to the contact between the first mask M1 and the bank 110 .

Display devices according to embodiments of the present invention may be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display area and a non-display area outside the display area, a planarization layer disposed on the substrate and having an opening in a portion thereof, and a planarization layer spaced apart from each other on the planarization layer. a plurality of banks, a first electrode disposed on the planarization layer disposed at one side of the opening, a light emitting layer disposed on a portion of the opening and a portion of the plurality of banks, and a portion of the plurality of banks and a second electrode disposed on the opening The plurality of banks includes a first bank disposed to cover the end of the first electrode, a second bank disposed on the planarization layer disposed on the other side of the opening, and a third bank, The upper surface may be disposed at a lower position than the upper surface of the second bank.

According to another feature of the present invention, the opening may be disposed between the first bank and the second bank, and the second bank may be disposed adjacent to the opening.

According to another feature of the present invention, the display device further includes a thin film transistor disposed on the substrate, and an inorganic insulating layer disposed on the thin film transistor, and the inorganic insulating layer may be exposed in the opening.

According to another feature of the present invention, a portion of the light emitting layer may be disposed on the inorganic insulating layer exposed in the opening.

According to another feature of the present invention, a portion of the light emitting layer disposed in the opening may be disposed to be spaced apart from the light emitting layer disposed on a portion of the plurality of banks.

According to another feature of the present invention, the first bank may overlap the display area, and the second bank and the third bank may overlap the non-display area.

According to still another feature of the present invention, in a display device, an encapsulation layer disposed on the second electrode, a filling layer disposed on the encapsulation layer, a second substrate disposed on the filling layer to correspond to the first substrate, and the first substrate and a dam disposed between the first substrate and the second substrate at an edge of the second substrate.

According to another feature of the present invention, the first bank includes a first surface adjacent to the end of the planarization layer disposed on one side of the opening and a second surface disposed on the end of the first electrode, The slope may be gentler than the slope of the first surface.

A display device according to another embodiment of the present invention includes a substrate including a display area and a non-display area outside the display area, a first planarization layer disposed on the substrate to overlap the display area, and a first planarization layer disposed to be spaced apart from the first planarization layer. 2 planarization layer, a first electrode disposed on the first planarization layer, a first bank disposed on a portion of the first electrode, a second bank disposed adjacent to an end of the second planarization layer on the second planarization layer, a second planarization layer A third bank spaced apart from the second bank on the second planarization layer and having a top surface disposed at a lower position than the top surface of the second bank, a light emitting layer disposed between the first planarization layer and the second planarization layer and on the first bank, and It may include a second electrode disposed on the emission layer and the second bank.

According to another feature of the present invention, the display device further includes a thin film transistor disposed on a substrate, and an inorganic insulating layer disposed on the thin film transistor, wherein the inorganic insulating layer is exposed between the first planarization layer and the second planarization layer can be

According to another feature of the present invention, the light emitting layer may be disposed between the first planarization layer and the second planarization layer to be in contact with the inorganic insulating layer.

According to another feature of the present invention, the light emitting layer disposed in contact with the inorganic insulating layer may be disposed to be spaced apart from the light emitting layer disposed on the first bank.

According to still another feature of the present invention, the display device further includes a connection electrode disposed on a portion and a side surface of the top surface of the second planarization layer, the connection electrode being electrically connected to the second electrode between the second bank and the third bank. can be connected to

According to another feature of the present invention, the first planarization layer and the second planarization layer may be connected to each other, and the emission layer and the second electrode may be disposed on the connected first planarization layer and the second planarization layer.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
101: substrate
103: buffer layer
104: circuit part
105: gate insulating layer
106: circuit part
107: planarization layer
107a: first planarization layer
107b: second planarization layer
107c: opening
108: circuit part
109: passivation layer
110: bank
110a: first bank
110aa: top surface of the first bank
110ab, 110ac: side of the first bank
110b: second bank
110ba: top surface of the second bank
110bb, 110bc: side of the second bank
110c: third bank
110ca: the top surface of the third bank
110bb: side of the second bank
112: connecting electrode
114: power wiring
120: thin film transistor
121: gate electrode
122: active layer
123: source electrode
124: drain electrode
130: light emitting element
131: first electrode
132: light emitting layer
133: second electrode
150: encapsulation layer
160: filling layer
170: second substrate
180: dam
SP: sub pixel
AA: display area
NA: non-display area
M1: first mask
M2: second mask

Claims (14)

a substrate including a display area and a non-display area outside the display area;
a planarization layer disposed on the substrate and having an opening in a portion thereof;
a plurality of banks spaced apart from each other on the planarization layer;
a first electrode disposed on the planarization layer disposed at one side of the opening;
a light emitting layer disposed on a portion of the opening and a portion of the plurality of banks;
a second electrode disposed on a portion of the plurality of banks and the opening;
The plurality of banks,
a first bank disposed to cover an end of the first electrode;
a second bank disposed on the planarization layer disposed on the other side of the opening; and a third bank;
and an upper surface of the third bank is disposed at a lower position than an upper surface of the second bank. According to claim 1,
The opening is disposed between the first bank and the second bank,
and the second bank is disposed adjacent to the opening. According to claim 1,
a thin film transistor disposed on the substrate; and
Further comprising an inorganic insulating layer disposed on the thin film transistor,
and the inorganic insulating layer is exposed through the opening. 4. The method of claim 3,
a portion of the light emitting layer is disposed on the inorganic insulating layer exposed in the opening. 5. The method of claim 4,
A portion of the emission layer disposed in the opening portion is disposed to be spaced apart from the emission layer disposed on a portion of the plurality of banks. According to claim 1,
the first bank overlaps the display area;
and the second bank and the third bank overlap the non-display area. According to claim 1,
an encapsulation layer disposed on the second electrode;
a filling layer disposed on the encapsulation layer;
a second substrate disposed on the filling layer to correspond to the first substrate; and
and a dam disposed between the first substrate and the second substrate at edges of the first substrate and the second substrate. According to claim 1,
The first bank may include a first surface adjacent to an end of the planarization layer disposed on one side of the opening; and a second surface disposed on an end of the first electrode,
and a slope of the second surface is gentler than a slope of the first surface. a substrate including a display area and a non-display area outside the display area;
a first planarization layer disposed on the substrate to overlap the display area;
a second planarization layer spaced apart from the first planarization layer;
a first electrode disposed on the first planarization layer;
a first bank disposed on a portion of the first electrode;
a second bank disposed adjacent to an end of the second planarization layer on the second planarization layer;
a third bank spaced apart from the second bank on the second planarization layer and having an upper surface disposed at a lower position than the upper surface of the second bank;
a light emitting layer disposed between the first planarization layer and the second planarization layer and on the first bank; and
and a second electrode disposed on the light emitting layer and the second bank. 10. The method of claim 9,
a thin film transistor disposed on the substrate; and
Further comprising an inorganic insulating layer disposed on the thin film transistor,
and the inorganic insulating layer is exposed between the first planarization layer and the second planarization layer. 11. The method of claim 10,
The light emitting layer is disposed between the first planarization layer and the second planarization layer to be in contact with the inorganic insulating layer. 12. The method of claim 11,
The light emitting layer disposed in contact with the inorganic insulating layer is disposed to be spaced apart from the light emitting layer disposed on the first bank. 10. The method of claim 9,
Further comprising a connection electrode disposed on a portion and side of the upper surface of the second planarization layer,
and the connection electrode is electrically connected to the second electrode between the second bank and the third bank. 10. The method of claim 9,
The first planarization layer and the second planarization layer are connected to each other,
The light emitting layer and the second electrode are disposed on the connected first planarization layer and the second planarization layer.

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