KR20210083946A - Light Emitting Display Device and Driving Method of the same - Google Patents

Abstract

The present invention provides a light emitting display device, which includes: a display panel for displaying an image; a switch circuit unit having an even transistor and an odd transistor on the display panel; and a compensation circuit unit connected to the switch circuit unit, wherein by alternating operation of the even transistor and the odd transistor, sub-pixels of the display panel are divided into a voltage-charging sub-pixel is charged with a voltage in order to provide a sensing value to the sub-pixels of the display panel, and a current emitting sub-pixels from which current is emitted to display black. Therefore, it is possible to improve video response speed (MPRT) and display quality by newly implementing a black frame insertion technique.

Description

Light Emitting Display Device and Driving Method of the Same

The present invention relates to a light emitting display device and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as a light emitting display (LED), a quantum dot display (QDD), and a liquid crystal display (LCD) is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixel transmits light or emits light directly, thereby displaying an image. .

Meanwhile, among the display devices described above, the light emitting display device has many advantages, such as electrical and optical characteristics with a fast response speed, high luminance, and a wide viewing angle, and mechanical characteristics that can be implemented in a flexible form.

The present invention is to improve video response speed (MPRT) and display quality by newly implementing a black frame insertion technique that can express black even during a blank section in which no video is displayed. In addition, the present invention is to facilitate bad pixel compensation by sharing a reference line for sensing deterioration of a device included in the sub-pixel and using a driving method that can change driving conditions of the sub-pixels connected to the sub-pixels.

As a means for solving the above problems, the present invention provides a display panel for displaying an image; a switch circuit unit having an even transistor and an odd transistor on the display panel; and a compensation circuit unit connected to the switch circuit unit, wherein the sub-pixels of the display panel are charged with a voltage to provide a sensed value by alternating operation of the even transistor and the odd transistor, and a voltage charging sub-pixel displaying black In order to do this, there is provided a light emitting display device divided into current emitting sub-pixels from which current is emitted.

The voltage charging and current emission of the sub-pixels may be performed during a blank period in which an image is not displayed on the display panel.

The voltage charging to the voltage charging sub-pixel and the current discharging to the current emitting sub-pixel may be simultaneously performed during the blank period.

The voltage charging sub-pixel and the current emitting sub-pixel may be changed to alternate in each blank period.

The voltage charging sub-pixel and the current emitting sub-pixel may be sub-pixels sharing one channel of the compensation circuit unit via the switch circuit unit.

In the first even transistor, a gate electrode is connected to an even signal line, a first electrode is connected to a first reference line of a first sub-pixel, a second electrode is connected to an N-th channel of the compensation circuit unit, and the first odd The transistor may have a gate electrode connected to the odd signal line, a first electrode connected to a second reference line of the second sub-pixel, and a second electrode connected to an Nth channel of the compensation circuit unit.

The compensation circuit unit may include a first switch that is turned on to discharge a current of the selected sub-pixel on the display panel, and a second switch that is turned on to acquire a sensed value of the selected sub-pixel on the display panel. .

In another aspect, the present invention provides a method comprising: applying a data voltage to sub-pixels; and charging a voltage to provide a sensed value for at least one of the sub-pixels, and emitting a current to display black in at least one of the sub-pixels.

The voltage charging and current emission of the sub-pixels may be performed during a blank period in which an image is not displayed on the display panel.

The positions of the sub-pixel charged with voltage and the sub-pixel from which current is emitted may be alternated in each blank section.

In another aspect, the present invention provides a display panel including a first sub-pixel and a second sub-pixel; a switch circuit unit having an even transistor electrically connected to the first subpixel and an odd transistor electrically connected to the second subpixel; and a compensation circuit part electrically connected to the switch circuit part, wherein during a first period of the display panel, the even transistor is turned off, the odd transistor is turned on, and the current of the second sub-pixel is discharged; , during a second period of the display panel, the even transistor is turned on, the odd transistor is turned off to sense the first subpixel, and during a third period of the display panel, the even transistor is turned on -on, the odd transistor is turned off to discharge the current of the first subpixel, and during a fourth period of the display panel, the even transistor is turned off, the odd transistor is turned on, and the A light emitting display device in which a second sub-pixel is sensed is provided.

A first period and a second period of the display panel may be included in a first blank period of the display panel, and a third period and a fourth period of the display panel may be included in a second blank period of the display panel.

A data driver for applying a data voltage to the first sub-pixel and the second sub-pixel may be further included, and the compensation circuit and the switch circuit may be included in the data driver.

The compensation circuit unit senses a threshold voltage or mobility of a driving transistor of the first sub-pixel during a second period of the display panel, and the compensation circuit unit operates the second sub-pixel during a fourth period of the display panel. The threshold voltage or mobility of the driving transistor may be sensed.

The present invention has the effect of improving the video response speed (MPRT) and display quality by newly implementing a black frame insertion technique that can express black even during a blank section in which no image is displayed. In addition, the present invention shares a reference line for sensing deterioration of a device included in the sub-pixels and provides an effect of easily compensating for bad pixels by using a driving method that allows different driving conditions for sub-pixels connected thereto there is

FIG. 1 is a block diagram schematically illustrating an organic light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1 .
3 is an exemplary diagram schematically illustrating a configuration of a device related to an externally compensated sub-pixel according to the first embodiment of the present invention, and FIG. 4 is an externally compensated sub-pixel according to the first embodiment of the present invention. It is an exemplary diagram for schematically explaining the characteristics of.
5 is a diagram illustrating a module configuration of a light emitting display device having an external compensation type sub-pixel according to a first embodiment of the present invention, and FIG. 6 shows an external compensation type sub-pixel and sensing the same according to the first embodiment of the present invention. It is an exemplary diagram showing a switch circuit for It is a diagram for explaining the advantages of a light emitting display device having pixels.
9 is a circuit configuration diagram illustrating an externally compensated sub-pixel according to a second embodiment of the present invention, and FIG. 10 is a detailed configuration of a device related to the externally compensated sub-pixel according to the second embodiment of the present invention. It is the circuit configuration diagram shown, and FIG. 11 is a waveform diagram for explaining the operation relationship of the apparatus shown in FIG.
12 is a waveform diagram for explaining a driving method according to a third embodiment of the present invention, and FIGS. 13 to 16 are diagrams for illustrating an operation of the circuit according to the driving method of FIG. 12 .

The display device according to the present invention may be implemented as a television, an image player, a personal computer (PC), a home theater, an electric vehicle, a smart phone, and the like, but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device or the like. Hereinafter, for convenience of explanation, a light emitting display device that displays an image by emitting light directly is taken as an example. The light emitting display device may be implemented based on an inorganic light emitting diode or based on an organic light emitting diode. Hereinafter, for convenience of description, an example implemented based on an organic light emitting diode will be described.

In addition, although it will be described that the sub-pixel described below includes an n-type thin film transistor as an example, it may be implemented as a p-type thin film transistor or a form in which both n-type and p-type exist. A thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the thin film transistor. That is, in the thin film transistor, the flow of carriers flows from the source to the drain.

In the case of the n-type thin film transistor, since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. On the other hand, in the case of the p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. However, the source and drain of the thin film transistor may be changed according to an applied voltage. Reflecting this, in the following description, any one of the source and the drain will be described as the first electrode, and the other one of the source and the drain will be described as the second electrode.

FIG. 1 is a block diagram schematically illustrating an organic light emitting display device according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1 .

1 and 2 , in the organic light emitting display device according to the first embodiment of the present invention, an image supply unit 110 , a timing control unit 120 , a scan driver 130 , a data driver 140 , The display panel 150 and the power supply unit 180 are included.

The image supply unit 110 (or the host system) outputs various driving signals together with the image data signal supplied from the outside or the image data signal stored in the internal memory. The image supply unit 110 may supply a data signal and various driving signals to the timing control unit 120 .

The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 , a data timing control signal DDC for controlling the operation timing of the data driver 140 , and various synchronization signals ( It outputs the vertical sync signal (Vsync) and the horizontal sync signal (Hsync).

The timing control unit 120 supplies the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140 . The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 outputs a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 supplies a scan signal to the sub-pixels included in the display panel 150 through the scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be formed directly on the display panel 150 in a gate-in-panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital data signal to analog data based on the gamma reference voltage. It is converted to voltage and output.

The data driver 140 supplies a data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and may be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates and outputs a high potential first power EVDD and a low potential second power EVSS based on an external input voltage supplied from the outside. The power supply unit 180 includes the first and second power sources (EVDD, EVSS) as well as voltages (eg, scan high voltage and scan low voltage) required for driving the scan driver 130 or the data driver 140 . It is possible to generate and output a voltage (drain voltage, half-drain voltage) and the like.

The display panel 150 includes a driving signal including a scan signal and a data voltage output from the driver including the scan driver 130 and the data driver 140 , and first and second power ( EVDD, EVSS) to display the image. The sub-pixels of the display panel 150 directly emit light.

The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, or the like. In addition, the sub-pixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

For example, one sub-pixel SP includes a pixel circuit PC including a switching transistor SW, a driving transistor, a storage capacitor, an organic light emitting diode, and the like. Since the sub-pixel SP used in the organic light emitting display device directly emits light, the circuit configuration is complicated. In addition, there are various types of compensation circuits for compensating for deterioration of organic light emitting diodes that emit light as well as driving transistors that supply driving current to the organic light emitting diodes.

3 is an exemplary diagram schematically illustrating a configuration of a device related to an externally compensated sub-pixel according to the first embodiment of the present invention, and FIG. 4 is an externally compensated sub-pixel according to the first embodiment of the present invention. It is an exemplary diagram for schematically explaining the characteristics of.

As shown in FIG. 3 , when the display panel includes the external compensation type sub-pixel SP, the data driver 140 applies the data voltage Vdata through the data line DL1 of the sub-pixel SP. ) along with the compensation circuit unit 160 for acquiring the sensing value Vsen including the device degradation information through the reference line VREF1 of the sub-pixel SP.

After obtaining the sensing value Vsen, the compensation circuit unit 160 may prepare a compensation value Dsen corresponding to deterioration information of a device included in the sub-pixel SP, and then transmit the compensation value Dsen to the data driver 140 . In addition, the data driver 140 may perform a compensation operation for compensating for deterioration of a device included in the sub-pixel SP based on the compensation value Dsen.

Meanwhile, although not shown, the compensation circuit unit 160 and the data driving unit 140 may cooperate with the timing control unit 120 of FIG. 1 to obtain the sensing value Vsen and then provide the compensation value Dsen. And in the above description, the compensation circuit unit 160 and the data driver 140 have been described as separate devices. However, in the first embodiment of the present invention, the compensation circuit unit 160 and the data driver 140 are included in one IC as an example.

However, it is noted that at least one of the compensation circuit unit 160 , the data driver 140 , and the timing control unit 120 may be integrated into one device depending on the implementation method of the light emitting display device. Therefore, the above description should be interpreted as a description for schematically understanding how sensing and compensation for externally compensated sub-pixels are performed.

As shown in FIG. 4 , the externally compensated sub-pixel may share one reference line by at least two sub-pixels. For example, the first and second sub-pixels SP1 and SP2 adjacent to each other may share the first reference line VREF1, and the third and fourth sub-pixels SP3 and SP4 adjacent to each other may be shared. ), the second reference line VREF2 may be shared.

The first reference line VREF1 may be defined as a sensing line for sensing deterioration characteristics of devices included in the first and second sub-pixels SP1 and SP2 , and the second reference line VREF2 is the third and a sensing line for sensing deterioration characteristics of devices included in the fourth sub-pixels SP3 and SP4.

As described above, if the pixel array circuit is implemented so that at least two sub-pixels share one reference line, the number of sensing channels required for the compensation circuit unit 160 of FIG. It has various advantages such as simplifying the design complexity and reducing the implementation cost.

5 is a diagram illustrating a module configuration of a light emitting display device having an external compensation type sub-pixel according to a first embodiment of the present invention, and FIG. 6 shows an external compensation type sub-pixel and sensing the same according to the first embodiment of the present invention. It is an exemplary diagram showing a switch circuit part for, Figure 7 is a waveform diagram for explaining the operation of the switch circuit part according to the first embodiment of the present invention, Figure 8 is an external compensation type sub according to the first embodiment of the present invention It is a diagram for explaining the advantages of a light emitting display device having pixels.

5, the light emitting display device having external compensation sub-pixels according to the first embodiment of the present invention includes a display panel 150, flexible circuit boards 141a to 141n, and data drivers 140a to 140n. , printed circuit boards 160a to 160b , a control board 115 , and a timing controller 110 , and the like.

The timing controller 110 may be mounted on the control board 115 . The control board 115 may be electrically connected to the plurality of printed circuit boards 160a and 160b through cables 161a and 161b. The data drivers 140a to 140n may be mounted on a plurality of flexible circuit boards 141a to 141n. The display panel 150 and the plurality of printed circuit boards 160a and 160b may be electrically connected to each other by the plurality of flexible circuit boards 141a to 141n.

The display panel 150 may include a switch circuit unit 155 . The switch circuit unit 155 may be located in a non-display area adjacent to the display area AA of the display panel 150 . The switch circuit unit 155 may be positioned between the display area AA of the display panel 150 and the plurality of flexible printed circuit boards 141a to 141n. The switch circuit unit 155 may operate in response to a control signal output from the timing control unit 110 or the data driving units 140a to 140n.

6 to 8 , red, blue, green, and white sub-pixels SPR, SPB, SPG, and SPW may be disposed in the display area AA of the display panel 150, and the non-display area A switch circuit unit 155 may be disposed at (NA).

Red and blue sub-pixels SPR and SPB are disposed on the first scan line GL1 to share the first reference line VREF1 , and the second scan line GL2 to share the first reference line VREF1 . Green and white sub-pixels SPG and SPW may be disposed. The sub-pixels SPR, SPB, SPG, and SPW may also be disposed on the second to fourth reference lines VREF2 to VREF4 in the same manner as described above. That is, the red, blue, green, and white sub-pixels SPR, SPB, SPG, and SPW may be arranged to form one pixel based on one reference line and two scan lines. However, the arrangement diagram of the sub-pixels SPR, SPB, SPG, and SPW is only an example, and the present invention is not limited thereto.

The switch circuit unit 155 includes the even-line transistors TE1 and TE2 and the odd-line transistors TO1 and TO2 positioned between the sensing channels 160_CHn and CHn+1 and the reference lines VREF1 to VREF4 of the compensation circuit unit. ) may be included.

The even line transistors TE1 and TE2 may be turned on/off in response to the even signal Sio_e output through the even signal line SIO_E. The even-line transistors TE1 and TE2 may be turned on in response to the logic-high even signal Sio_e and may be turned off in response to the logic-low even signal Sio_e.

The odd line transistors TO1 and TO2 may be turned on/off in response to the odd signal Sio_o output through the odd signal line SIO_O. The odd line transistors TO1 and TO2 may be turned on in response to the logic high odd signal Sio_o, and may turn off in response to the logic low odd signal Sio_o.

The time when the even signal Sio_e and the odd signal Sio_o have a logic high may be divided without overlapping each other. In FIG. 7 , the even signal Sio_e has a logic high and falls to a logic low, and then the odd signal Sio_o has a logic high as an example, but this may be reversed.

When the first even line transistor TE1 is turned on by the logic high even signal Sio_e, characteristic values of the sub-pixels SPR, SPB, SPG, and SPW connected to the first reference line VREF1 may be sensed. . When the first odd line transistor TO1 is turned on by the logic high odd signal Sio_o, characteristic values of the sub-pixels SPR, SPB, SPG, and SPW connected to the second reference line VREF2 may be sensed. . That is, the turn-on times and turn-off times of the first even-line transistor TE1 and the first odd-line transistor TO1 alternate. Similarly, the turn-on times and turn-off times of the second even-line transistor TE2 and the second odd-line transistor TO2 also alternate.

Referring to the above description, the two reference lines share one sensing channel included in the compensation circuit unit, but can be utilized to perform different functions as the transistors between them alternately operate.

For example, in the first embodiment of the present invention, the sensing operation is performed on the sub-pixels connected to one reference line in accordance with the operation of the even-line transistor and the odd-line transistor that operate alternately, and the sub-pixel connected to the other reference line is operated. It causes the pixels to emit (discharge) a current.

In the case of the above operation, as shown in FIG. 8 , an image may be displayed on the display panel during the active time period and black may be displayed on the display panel during the blank time period as shown in FIG. 8 . A blank time is a section in which an image is not displayed on the display panel. An explanation for this is added as follows:

During the blank time of the Even Frame, a sensing operation is performed on the sub-pixels connected to the even-numbered reference line, and a current discharge (discharge) operation is performed on the sub-pixels connected to the odd-numbered reference line. Conversely, during the blank time of the odd frame, the sensing operation is performed on the sub-pixels connected to the odd-numbered reference line, and the current discharge (discharge) operation is performed on the sub-pixels connected to the even-numbered reference line. .

When the device is operated under the above conditions, the sensing operation and the current emitting operation alternate at each blank time, and black may be expressed on the display panel by the sub-pixels in which the current is emitted. It should be noted that the even-line transistor and the odd-line transistor alternately operate during one blank period, so that the black that can be expressed at this time is defined as "1/2 black". Accordingly, according to the present invention, one frame of black can be expressed for every two frames.

As in the first embodiment of the present invention, if a black frame capable of expressing black even during the blank time is implemented, a video response is performed along with a compensation operation for sensing and compensating for deterioration of the device included in the sub-pixel. Speed (Motion Picture Response Time; MPRT) and display quality can be improved. Also, as in the first embodiment, if the reference line is shared and the driving conditions of the sub-pixels connected thereto are changed, bad pixel compensation can be easily performed through the selective driving method for each sub-pixel. This is because, since voltage charging and sensing of the same sub-pixel is possible, it is easy to compensate for a bad pixel, and a problem of increasing visibility as other sub-pixels are darkened can be prevented.

Meanwhile, during the blank time, a compensation operation for sensing and compensating for deterioration of the element included in the sub-pixel and an operation for expressing black are performed, while during the active time, an operation for expressing a normal image is performed. . The even-line transistor and the odd-line transistor do not need to operate alternately during the active time period for expressing a normal image. Accordingly, during the active time period, the even-line transistor and the odd-line transistor receive the logic high odd signal Sio_o and the even signal Sio_e or apply the logic low odd signal Sio_o and the even signal Sio_e. can receive

In addition, in adopting the driving method as in the first embodiment, a method of improving the internal operating frequency of the device by using a frame memory to further secure a blank time may be used, but the present invention is not limited thereto.

Hereinafter, an example in which the present invention is applied to an external compensation type sub-pixel including three transistors, one storage capacitor, and one organic light emitting diode will be described.

9 is a circuit configuration diagram illustrating an externally compensated sub-pixel according to a second embodiment of the present invention, and FIG. 10 is a detailed configuration of a device related to the externally compensated sub-pixel according to the second embodiment of the present invention. It is the circuit configuration diagram shown, and FIG. 11 is a waveform diagram for explaining the operation relationship of the apparatus shown in FIG.

As shown in FIG. 9 , the external compensation type sub-pixel SP according to the second embodiment of the present invention includes a switching transistor SW, a driving transistor DT, a storage capacitor CST, a sensing transistor ST, and It may include an organic light emitting diode (OLED).

The switching transistor SW may have a gate electrode connected to the first A scan line GL1a, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The driving transistor DT may have a gate electrode connected to the storage capacitor CST, a first electrode connected to the first power line EVDD, and a second electrode connected to an anode electrode of the organic light emitting diode OLED.

The storage capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light emitting diode OLED. The organic light emitting diode OLED may have an anode electrode connected to the second electrode of the driving transistor DT and a cathode electrode connected to the second power line EVSS. The sensing transistor ST has a gate electrode connected to the first B scan line GL1b, a first electrode connected to a first reference line VREF1, and a second electrode of the driving transistor DT and an organic light emitting diode OLED. The second electrode may be connected to the sensing node to which the anode electrode is connected.

The sensing transistor ST is a compensation circuit added to the inside of the sub-pixel SP to compensate for deterioration or threshold voltage of the driving transistor DT and the organic light emitting diode OLED. The sensing transistor ST may acquire a sensing value through a sensing node defined between the driving transistor DT and the organic light emitting diode OLED. The sensed value obtained from the sensing transistor ST may be transmitted to the compensation circuit unit through the first reference line VREF1.

The first A scan line GL1a connected to the gate electrode of the switching transistor SW and the 1B scan line GL1b connected to the gate electrode of the sensing transistor ST do not have a separate structure as shown in the figure, but are connected in common. can also take A structure in which the gate electrode of the switching transistor SW and the gate electrode of the sensing transistor ST are commonly connected to one scan line can reduce the number of scan lines and also prevent reduction in the aperture ratio due to the addition of the sensing transistor for compensation. can do.

10 , the display panel 150 may include a first red sub-pixel SPR1 and a second red sub-pixel SPR2. The first red sub-pixel SPR1 and the second red sub-pixel SPR2 may be defined as sub-pixels positioned on one scan line, adjacent to each other, and emitting the same color, but is not limited thereto.

As described with reference to FIG. 9 , the first red sub-pixel SPR1 and the second red sub-pixel SPR2 include the switching transistor SW, the driving transistor DT, the storage capacitor CST, the sensing transistor ST, and the organic light emitting diode. Each of the diodes (OLED) may be included.

The first red sub-pixel SPR1 may be defined between the first data line DL1 and the first reference line VREF1, and the second red sub-pixel SPR2 is formed between the second data line DL2 and the second data line DL2. It may be defined by the two reference lines VREF2.

The first red sub-pixel SPR1 and the second red sub-pixel SPR2 are separately connected to the first data line DL1 and the second data line DL2, respectively, and the two data lines DL1 and DL2 are They are also physically separated. Therefore, the first red sub-pixel SPR1 and the second red sub-pixel SPR2 may receive different data voltages from the data driver 140 .

The first red sub-pixel SPR1 and the second red sub-pixel SPR2 are separately connected to the first reference line VREF1 and the second reference line VREF2, respectively, and the two reference lines VREF1 and VREF2 are physically is also separated. However, by the turn-on or turn-off operation of the transistors TE1 and TO1 included in the switch circuit unit 155, the N-th channel CHn of the compensation circuit unit 160 may be connected to share or separated to monopolize any selected one. have.

The switch circuit unit 155 may include a first even transistor TE1 and a first odd transistor TO1 . The first even transistor TE1 has a gate electrode connected to the even signal line SIO_E, a first electrode connected to a first reference line VREF1, and a second electrode connected to the N-th channel CHn of the compensation circuit unit 160 . This can be connected The first odd transistor TO1 has a gate electrode connected to the odd signal line SIO_O, a first electrode connected to a second reference line VREF2, and a second electrode connected to the N-th channel CHn of the compensation circuit unit 160 . This can be connected

The compensation circuit unit 160 is configured to sense deterioration information of devices included in the first red sub-pixel SPR1 or the second red sub-pixel SPR2, and includes a first switch VPRE, a voltage source VRE, and a second It may include a switch (SAM), a converter (ADC), and the like.

The first switch VPRE may perform a switching operation for applying a pre-charge voltage to the sub-pixel connected to the N-th channel CHn or for discharging a current of the sub-pixel. The voltage source VRE may form a discharge path capable of transferring a pre-charge voltage or discharging a current to the first switch VPRE.

The second switch SAM may perform a switching operation for acquiring (sampling) a sensing value from a sub-pixel connected to the N-th channel CHn. The converter ADC may perform an operation of converting the sensed value in the analog form acquired by the operation of the second switch SAM into the sensed value in the digital form. Meanwhile, it is noted that the compensation circuit unit 160 has a plurality of channels, but only a portion related to the N-th channel CHn is illustrated due to the characteristics of the drawing. In addition, it should be noted that “DAC” in FIG. 10 means a digital-to-analog converter that outputs a data voltage inside the data driver 140 .

As shown in FIGS. 10 and 11 , the second switch signal Sam for driving the second switch SAM is set at logic high at least twice during a period in which the scan signal and the data voltage Scan & Vdata are applied. can occur In addition, the even signal Sio_e may be generated to be logic high in synchronization with the logic high section of the first second switch signal Sam, and the odd signal Sio_o may be generated in synchronization with the logic high section of the second second switch signal Sam. may occur as logic high. The second switch signal Sam falls to a logic low after the first switch signal Vpre for driving the first switch VPRE is generated at a logic high simultaneously with the application of the scan signal and the data voltages Scan & Vdata. It may occur after a certain delay time.

When the pre-charge voltage is applied together with the scan signal and data voltage Scan & Vdata, the voltage can be charged to the second reference line VREF2 of the first red sub-pixel SPR1 and the second red sub-pixel SPR2. have.

The first reference line VREF1 of the first red sub-pixel SPR1 and the second reference line VREF2 of the second red sub-pixel SPR2 have a low voltage level due to the pre-charge voltage, but the data voltage Vdata This shows a charging pattern in which the voltage level increases.

However, the charging behavior at this time may be affected by a deterioration component (threshold voltage variation) of the driving transistor. Therefore, the voltage charged in the first reference line VREF1 of the first red sub-pixel SPR1 and the second reference line VREF2 of the second red sub-pixel SPR2 is applied to the deterioration component (threshold voltage change) of the driving transistor. can be expressed as "Vdata - Vth_even" and "Vdata - Vth_odd" respectively. At this time, "Vdata - Vth_even" is charged in the first line capacitor CP1 of the first reference line VREF1 of the first red sub-pixel SPR1, and "Vdata - Vth_odd" is the second red sub-pixel SPR2. may be charged in the second line capacitor CP2 of the second reference line VREF2.

The compensation circuit unit 160 acquires "Vdata - Vth_even" charged in the first line capacitor CP1 of the first reference line VREF1 of the first red sub-pixel SPR1 as the first sensing value Vsen_e, "Vdata - Vth_odd" charged in the second line capacitor CP2 of the second reference line VREF1 of the second red sub-pixel SPR2 may be acquired as the second sensing value Vsen_o. The compensation circuit unit 160 may set compensation values for the first red sub-pixel SPR1 and the second red sub-pixel SPR2 based on the first sensing value Vsen_e and the second sensing value Vsen_o.

Since the first even transistor TE1 and the first odd transistor TO1 are alternately turned on, the first sensed value Vsen_e is sensed for the first time and the second sensed value Vsen_o is the second sensed value after the first time. It can be sensed for 2 hours.

Therefore, according to the second embodiment of the present invention, voltage charging of the first and second red sub-pixels SPR1 and SPR2 connected to the first even transistor TE1 and the first odd transistor TO1 is simultaneously performed, and then sequentially Sampling for sensing can be performed. In addition, the present invention allows one reference line to be shared, but since voltage charging can be performed simultaneously and then sequential sensing can be performed, it prevents an increase in the time required for a compensation operation (eg, after the device is turned off) to prevent the tact time (tact time). time) can be reduced.

12 is a waveform diagram for explaining a driving method according to a third embodiment of the present invention, and FIGS. 13 to 16 are diagrams for illustrating an operation of the circuit according to the driving method of FIG. 12 .

In the third embodiment of the present invention, black may be displayed on the display panel during a blank time by controlling the switch circuit unit 155 and the compensation circuit unit 160 to improve the video response speed (MPRT).

12 and 13 , the first odd line transistor TO1 is turned on by the logic high odd signal Sio_o during the first period of the first blank period (the first blank period). and the first even line transistor TE1 may be turned off by the logic low even signal Sio_e.

The first red sub-pixel SPR1 and the second red sub-pixel SPR2 are in a state in which the sensing data voltage is supplied through the first data line DL1 and the second data line DL2 . However, since the first odd-line transistor TO1 is turned on during the first period of the first blank time, the second line capacitor (VREF2) of the second reference line (VREF2) of the second red sub-pixel (SPR2) is turned on. CP2) is not charged with voltage.

The reason is that the first switch VPRE of the N-th channel CHn of the compensation circuit unit 160 is turned on by the first switch signal Vpre, and the voltage source VRE is the second red sub-pixel SPR2. This is because it operates as a discharge source capable of emitting the current applied to the second reference line VREF2. Contrary to this, since the first even-line transistor TE1 is turned off during the first period of the first blank time, the first even-line transistor TE1 of the first reference line VREF1 of the first red sub-pixel SPR1 is A voltage may be charged in the line capacitor CP1.

In summary, during the first period of the first blank period, the second red sub-pixel SPR2 (current emitting sub-pixel) has a current emitting period capable of displaying black on the display panel while the first red sub-pixel SPR2 has a current emitting period for displaying black on the display panel. It can be described that the sub-pixel SPR1 (voltage charging sub-pixel) has a voltage charging period for providing a sensing value necessary for external compensation.

12 and 14 , the first even line transistor TE1 is turned on by the logic high even signal Sio_e during the second period of the first blank period (the second blank period). and the first odd line transistor TO1 may be turned off by the logic low odd signal Sio_o.

Accordingly, a sensing operation for sensing a charged voltage is performed for the first red sub-pixel SPR1 during the second period of the first blank time, but the second red sub-pixel (SPR1) without a charged voltage For SPR2), black is displayed during the second period following the first period of the first blank period.

12 and 15 , during the first period (third period) of the second blank period, the first even line transistor TE1 is turned on by the logic high even signal Sio_e, and , the first odd line transistor TO1 may be turned off by the odd signal Sio_o of logic low.

The first red sub-pixel SPR1 and the second red sub-pixel SPR2 are in a state in which the sensing data voltage is supplied through the first data line DL1 and the second data line DL2 . However, since the first even line transistor TE1 is turned on during the first period of the second blank time, the first line capacitor (VREF1) of the first reference line VREF1 of the first red sub-pixel SPR1 is turned on. CP1) is not charged with voltage.

The reason is that the first switch VPRE of the N-th channel CHn of the compensation circuit unit 160 is turned on by the first switch signal Vpre, and the voltage source VRE is the first red sub-pixel SPR1. This is because it operates as a discharge source capable of emitting the current applied to the first reference line VREF1. Contrary to this, since the first odd line transistor TO1 is turned off during the first period of the second blank time, the second reference line VREF2 of the second red sub-pixel SPR2 is A voltage may be charged in the line capacitor CP2 .

In summary, during the first period of the second blank period, the first red sub-pixel SPR1 has a current emission period for displaying black on the display panel, while the second red sub-pixel SPR2 It can be described as having a voltage charging period to prepare a sensing value necessary for external compensation. That is, circuits related to the first red sub-pixel SPR1 and the second red sub-pixel SPR2 operate under conditions opposite to those of the first period of the first blank time.

12 and 16, during the second period (fourth period) of the second blank period, the first odd-line transistor TO1 is turned on by the odd signal Sio_o of logic low, and , the first even line transistor TE1 may be turned off by the logic high even signal Sio_e.

Accordingly, a sensing operation for sensing a charged voltage is performed with respect to the second red sub-pixel SPR2 during the second period of the second blank time, but the first red sub-pixel ( SPR2 ) without a charged voltage is performed. For SPR1), black is displayed for the second period following the first period of the second blank period (Blank Time).

As can be seen from the waveform of FIG. 12 , the current emission time of the selected sub-pixel during the first period of the blank period may correspond to a spare time generated in the voltage charging time for sensing. The slack time generated during the voltage charging time may be defined as the time before the first switch signal Vpre is generated at logic high and then falls to logic low and then before the second switch signal Sam is generated at logic high. .

The current emission time of the selected sub-pixel during the first period of the blank time may be defined to be longer than the sensing time of the selected sub-pixel during the second period of the blank time for sufficient black expression. .

As described above, the present invention has the effect of improving the video response speed (MPRT) and display quality by newly implementing a black frame insertion technique that can express black even during a blank section in which no image is displayed. In addition, the present invention shares a reference line for sensing deterioration of a device included in the sub-pixels and provides an effect of easily compensating for bad pixels by using a driving method that allows different driving conditions for sub-pixels connected thereto there is

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

150: display panel 155: switch circuit part
140: data driver 160: compensation circuit unit
Sio_e: Even signal Sio_o: Odd signal
TE1, TE2: Even-Line Transistors
TO1, TO2: Offline Transistors

Claims (14)

a display panel for displaying an image;
a switch circuit unit having an even transistor and an odd transistor on the display panel; and
Comprising a compensation circuit unit connected to the switch circuit unit,
By alternating operation of the even transistor and the odd transistor, the sub-pixels of the display panel are divided into a voltage-charged sub-pixel that is charged with a voltage to provide a sensed value, and a current-emitting sub-pixel that emits a current to display black. light emitting display device. According to claim 1,
Voltage charging and current emission for the sub-pixels are
A light emitting display device formed during a blank period in which no image is displayed on the display panel. 3. The method of claim 2,
A light emitting display device in which voltage charging to the voltage charging sub-pixel and current emitting to the current emitting sub-pixel are simultaneously performed during the blank period. 3. The method of claim 2,
The voltage charging sub-pixel and the current emitting sub-pixel are
A light emitting display device that is changed to be alternated for each blank section. 3. The method of claim 2,
The voltage charging sub-pixel and the current emitting sub-pixel are
and sub-pixels sharing one channel of the compensation circuit unit via the switch circuit unit. According to claim 1,
In the first even transistor, a gate electrode is connected to an even signal line, a first electrode is connected to a first reference line of a first sub-pixel, and a second electrode is connected to an N-th channel of the compensation circuit part;
In the first odd transistor, a gate electrode is connected to an odd signal line, a first electrode is connected to a second reference line of a second sub-pixel, and a second electrode is connected to an N-th channel of the compensation circuit unit. According to claim 1,
the compensation circuit
a first switch that turns on to emit current of a selected sub-pixel on the display panel;
and a second switch that is turned on to acquire a sensing value of the selected sub-pixel on the display panel. applying a data voltage to the sub-pixels; and
and charging a voltage to provide a sensed value for at least one of the sub-pixels and emitting a current to display black in at least one of the sub-pixels. 9. The method of claim 8,
Voltage charging and current emission for the sub-pixels are
A method of driving a light emitting display device during a blank period in which no image is displayed on the display panel. 10. The method of claim 9,
A method of driving a light emitting display device in which positions of a sub-pixel charged with voltage and a sub-pixel from which current is emitted are alternated in each blank section. a display panel including a first sub-pixel and a second sub-pixel;
a switch circuit unit having an even transistor electrically connected to the first sub-pixel and an odd transistor electrically connected to the second sub-pixel; and
Comprising a compensation circuit part electrically connected to the switch circuit part,
During the first period of the display panel, the even transistor is turned off, the odd transistor is turned on, and the current of the second subpixel is discharged;
During the second period of the display panel, the even transistor is turned on, the odd transistor is turned off, and the first subpixel is sensed;
During a third period of the display panel, the even transistor is turned on, the odd transistor is turned off, and the current of the first sub-pixel is discharged;
During a fourth period of the display panel, the even transistor is turned off and the odd transistor is turned on to sense the second subpixel. 12. The method of claim 11,
The first period and the second period of the display panel are included in a first blank period of the display panel, and the third period and the fourth period of the display panel are included in a second blank period of the display panel. . 12. The method of claim 11,
a data driver for applying a data voltage to the first sub-pixel and the second sub-pixel;
The compensation circuit unit and the switch circuit unit are included in the data driver. 12. The method of claim 11,
the compensation circuit unit senses a threshold voltage or mobility of a driving transistor of the first sub-pixel during a second period of the display panel;
The compensation circuit unit senses a threshold voltage or mobility of a driving transistor of the second sub-pixel during a fourth period of the display panel.

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