KR20210075930A - Memory error detection and correction - Google Patents

Abstract

A memory device such as an MRAM memory device comprises a plurality of memory macros, and each of the plurality of memory macros comprises an array of memory cells and a first ECC circuit configured to detect data errors within each of the memory macros. A second ECC circuit which is distant from the plurality of memory macros is communicatively coupled with each of the plurality of memory macros. The second ECC circuit receives the data error detected from the first ECC circuit of the plurality of memory macros, and corrects the data error.

Description

MEMORY ERROR DETECTION AND CORRECTION

The present invention relates to memory error detection and correction.

Memory is widely used to store information (both data and programs) in digital systems. During system operation, information (bits) stored in memory can be corrupted for various reasons. One possible cause of corruption is environmental events both inside and outside of memory. One such external event is particle collision. Besides environmental events, there are other reasons that cause bit damage (failure). If a bit is corrupted, the information being stored is lost, resulting in system failure or data loss. It is therefore important to protect the integrity of the memory contents. Various means have been used to protect memory contents from corruption. Error Correction Codes (ECC) have the advantage of being able to detect errors in code words (both data fields and check bits) and correct errors.

Aspects of the present disclosure may be best understood by reading the following detailed description in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of description. Moreover, the drawings are illustrative by way of illustration of embodiments of the invention and are not intended to be limiting.
1 is a block diagram generally illustrating an exemplary MRAM device having a plurality of MRAM arrays each having dedicated and simplified ECC circuitry in accordance with one embodiment.
2 is a block diagram generally illustrating an exemplary MRAM cell within an MRAM array in accordance with one embodiment.
3 is a block diagram generally illustrating an exemplary ECC logic process for MRAM error correction in accordance with one embodiment.
4 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
5 is a block diagram generally illustrating an exemplary ECC logic process for MRAM error correction in accordance with one embodiment.
6 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
7 is a block diagram generally illustrating an exemplary ECC logic process for MRAM error correction in accordance with one embodiment.
8 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to an embodiment.
9 is a block diagram generally illustrating an exemplary ECC logic process for MRAM error correction in accordance with one embodiment.
10 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
11 is a block diagram generally illustrating an exemplary ECC logic process for MRAM error correction in accordance with one embodiment.
12 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
13 is a block diagram generally illustrating an example ECC logic process for MRAM error correction in accordance with one embodiment.
14 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
15 is a block diagram generally illustrating an example ECC logic process for MRAM error correction in accordance with one embodiment.
16 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to an embodiment.
17 is a block diagram generally illustrating an example ECC logic process for MRAM error correction in accordance with one embodiment.
18 is a flowchart of a method of correcting an MRAM error using an ECC logic process according to one embodiment.
19 is a flowchart of a method of correcting an MRAM error using a hierarchical ECC logic process according to an embodiment.

The disclosure below provides many different embodiments or examples for implementing various features of the disclosure. Certain examples of constituent elements and arrangements are described below to simplify the present disclosure. Of course, this is merely an example and is not intended to be limiting. For example, in the following description the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and wherein the additional features are first and embodiments formed between the second features so that the first and second features do not directly contact. In addition, this disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the sake of simplicity and clarity, and does not in itself represent a relationship between the various embodiments and/or configurations being discussed.

Also, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. In describing a relationship between one illustrated element or feature and another element(s) or feature(s), it may be used for convenience of description. Spatially relative terms encompass other orientations of the device in use or operation in addition to the orientations shown in the figures. The device may be positioned in other orientations (rotated 90 degrees or rotated in other directions), and spatially relative descriptors used in this disclosure may likewise be interpreted accordingly.

Memory devices are used to store information in semiconductor devices and systems. A widely used Dynamic Random Access Memory (DRAM) cell includes a switch and a capacitor. DRAM does not retain data when power is turned off. Non-volatile memory devices can retain data even after power is cut off. Examples of non-volatile memory devices include flash memory, Magnetic Random Access Memories (MRAM), Ferroelectric Random Access Memories (FRAM), and Phase-Change Random Access Memories (PRAM). ) is included. MRAM stores data using a change in magnetization direction in a tunnel junction. FRAM stores data using the polarization characteristics of ferroelectrics. PRAM stores data using a change in resistance due to a phase change in a particular material.

Memory is typically arranged in a two-dimensional array. A memory array may be a device on its own or embedded in other devices, and may also contain many memory bit cells. Each memory bit cell can typically store one bit of information. A memory macro may include one or more bit cell arrays and other logic circuitry such as drivers, buffers, clock fan-out circuitry, ECC circuitry, and other peripheral circuitry.

Certain types of memory devices, such as MRAM, have more than one resistance state depending on the magnetization alignment state between two or more layers of magnetic material, such as a ferromagnetic material. More specifically, MRAM stores data in memory cells having two overlapping layers of magnetic material separated by an insulating thin film. The layer structure forms the magnetic tunnel junction (“MTJ” or “MTJ component”) of the MRAM cell. The two layers include a magnetic layer that is permanently magnetized in a fixed magnetic field alignment direction (this layer is referred to as a "pinned layer") and a magnetic layer that is changeably magnetized (this layer is referred to as a "free layer"). The free layer may be magnetized in one of two orientations relative to the permanently magnetized layer. The two orientations are characterized by distinctly different series resistances through the overlapping layers of the MTJ. The magnetic field orientation of the changeable layer may be aligned with the orientation of the permanent magnet layer (parallel) or opposite to the orientation of the permanent magnet layer (antiparallel). The parallel alignment state has a relatively low resistance, and the antiparallel alignment state has a higher resistance.

The two states of an MRAM cell can be sensed from relatively high or low resistances (RH, RL) representing different binary logic values of the bits stored in the memory. For example, RL (or high cell current) may be assigned a logical “1” (“data-1”); RH (or low cell current) can be specified as a logical “0” (“Data-0”). In certain embodiments, a reference voltage may be applied to the MRAM cell, and the resulting cell current may be used to determine whether the cell is in a low resistance state or a high resistance state. In certain embodiments, a sense amplifier may be used to compare the cell current to a reference current.

Data errors, such as soft errors that are not permanent or indicative of physical damage to the device, can occur due to disturbance errors, radiation effects, or thermal effects. These errors may be judgmental or may be due to a probabilistic process. Data error rates including soft errors may require the use of an Error Correction Code Scheme (ECC) embedded in an MRAM device chip. ECC can be used to detect and correct bit errors that are stored in memory. ECC encodes data by generating ECC check bits, such as redundancy bits or parity bits, that are stored with the data in a memory device. The data and parity bits together form a code word. For example, ECC, which generates eight parity bits for 64-bit data, uses 64, commonly known as the SECDED (Single-Error Correcting (SEC) and Double-Error Detecting (DED)) codes. It is possible to detect two bit errors in bit data and correct one bit error.

Additional memory space may be required to store the check bits used with ECC. Accordingly, an additional memory device or devices (eg, an additional chip or chips) may be needed to store the check bit to provide ECC capability. In some memory arrays, additional columns may be added to the array to store check bits (also called parity bits). Data included in one row of the memory array may be referred to as a word. The code word refers to a data string including a word added to additional column(s) and a parity bit. If a code word contains a word portion with K bits and M parity bits, the code word length N will be N = K+M. For example, an ECC memory capable of providing 8-bit parity for each 32-bit data word may include a 40-bit wide interface for accessing a 40-bit code word with 32-bit data. Similarly, an ECC memory capable of providing 8-bit parity for each 64-bit data word may include a 72-bit wide interface for accessing a 72-bit code word with 64-bit data.

Providing ECC circuitry for every memory array or macro increases the area requirement for the device. An alternative way to minimize the area requirement for ECC circuitry is to provide global ECC circuitry that is shared between memory arrays or macros. However, the approach of using shared ECC circuitry for a memory array or macro is compared to providing ECC circuitry for all memory arrays or macros, the energy expended in moving or propagating data to or from the memory array and ECC circuitry. to increase

Detection of bit errors in code words requires less operation than bit error correction, and thus requires less circuitry to support fewer operations. According to the disclosed embodiment, the first portion of the ECC circuitry is provided locally to each memory macro, while the second portion is implemented as a shared, global ECC accessed by all memory macros of the memory device. For example, the error detection aspect of the ECC circuit may be implemented as a first local ECC for each MRAM macro or a small group of macros. The error correction aspect of ECC is implemented as a second or global ECC that supports many MRAM macros. In this way, for error correction, only memory errors detected by the local ECC should be sent to the global ECC.

This hierarchical ECC structure with local and global ECC implementations reduces the area of overhead ECC circuitry compared to providing local full ECC to all memory arrays or macros, and also reduces the area of overhead ECC circuitry compared to providing shared global full ECC. By reducing global data communication energy, it is possible to effectively balance the area requirements and power consumption of the device with respect to error correction. For correction, global data communication energy is reduced by moving or propagating only detected memory errors to global ECC circuitry, by providing only detection ECC circuitry per every memory array or macro while error correction circuitry is provided by shared global ECC circuitry Device area requirements are minimized.

1 is a block diagram generally illustrating an example memory device having a plurality of memory arrays each having dedicated and simplified ECC circuitry, in accordance with some embodiments of the present disclosure. In the example shown in FIG. 1 , the memory device may be an MRAM device 100 , although other memory types are within the scope of the present disclosure. The MRAM device 100 includes a plurality of memory arrays 102a - n , a local ECC circuit 140a - n coupled to each memory array 102 , each memory array 102 and coupled to the ECC circuit 140 . local I/O circuits 106a - n, a controller 108 coupled to each local I/O circuit 106 , a global ECC circuit 160 , and a global I/O circuit 110 . In the illustrated embodiment, memory macros 130a-n may include local memory arrays 102a-n, local ECC circuits 140a-n, and local I/Os 106a-n.

According to some embodiments, if the refresh interval is properly designed, most read operations in a memory refresh should be relatively error-free. In this case, an ECC scheme in which a simple error detection function can be performed locally is implemented, so that the local refresh data path 120 becomes shorter and latency during refresh is reduced. ECC circuitry including error correction may be shared among multiple macros 130a-n, and a longer global refresh data path 122 would be used in these relatively rare events. In this way, the area required for the local ECC circuits 140a-n having only error detection each requires a significantly smaller area.

Many methods have been developed to implement ECC, including Hamming codes, triple module redundancy, and the like. For example, Hamming codes are a class of binary linear block codes that, depending on the number of parity bits used, can detect up to two bit errors per code word, or correct one bit error without detecting uncorrected errors. to be. Several schemes have been developed, but in general parity bits are arranged within a code word so that if different wrong bits produce different error results, it is possible to identify the bit in which the error occurred. For erroneous code words, the error pattern is called an error syndrome, which identifies the erroneous bit. This syndrome decoding is a very efficient way to decode erroneous linear block codes.

As described herein, local ECC circuitry 140a - n and global ECC 160 may employ ECC encoding and decoding using ECC encoders and decoders. An ECC encoder may include any technique or algorithm that adds redundancy to information to detect or correct errors. For example, error correction codes include non-binary block codes such as Reed-Solomon [255, 239] or [255, 221] codes, Hamming codes and Bose-Chaudhuri-Hocquenghem (BCH) codes. linear block codes, such as cyclic Hamming codes, Hadamard codes such as Hadamard [16, 5] codes, Golay codes such as Golay [23, 12] codes, extended Golay [24, 12] codes, or Cyclic Golay [24, 12] Codes, Maximum Length Shift Register Codes, Reed Muller Codes, AC Codes, Gappa Codes, Binary and Non-Binary Convolutional Codes, Double K Codes, Turbo Codes, Turbo Product Codes, LDPC Codes, It can contain linking code created by wrapping one piece of code inside another, and so on. By adding more parity bits, the strength of the error correction code can be adjusted as needed. For example, the strength of a code can be measured by the minimum Hamming distance. The ECC decoder may be coupled to the ECC encoder and used to calculate the syndrome of the code word.

In some embodiments, in particular, the ECC decoder may be included in the local ECC circuits 140a - n to perform matrix multiplication on predefined parity check matrices and code words. The predefined parity check matrix may be determined according to the type of ECC used. For example, the predefined parity check matrix may be a 7x3 parity check matrix (H) of a (7, 4) Hamming code. Accordingly, the ECC decoder outputs a 3-tuple vector composed of 3 bits. The ECC decoder is for checking whether a code word to be encoded is a valid code word, based on the principle of (7, 4) Hamming code. When the 3-tuple vector generated by the ECC decoder, ie, the syndrome, is equal to (0, 0, 0), it is determined that the encoded code word is a valid code word. In this case, only the operation of determining that the code word is valid is required, and the local refresh data path 120 is used. If the 3-tuple vector generated by the ECC decoder is not equal to (0, 0, 0) in operation, the encoded code word is determined to have at least one error. In this case, a more complete ECC including error correction is needed, and the global refresh data path 122 is used.

2 is a block diagram generally illustrating another aspect of an example of an MRAM device 100 . In the illustrated embodiment, local memory array 102a includes a plurality of MRAM bit cells, such as MRAM bit cells 200, arranged in rows and columns. The MRAM bit cell 200 includes an access transistor 212 and an MTJ component 214 . The MTJ component 214 has a variable resistance depending on the orientation of the free layer and is operatively coupled between the access transistor 212 and the bit line 204 . Access transistor 212 is operatively coupled between bit line 206 and MTJ component 214 , and has a gate coupled to word line 202 . During a read or write operation, a voltage greater than the threshold voltage of access transistor 212 is applied to word line 202 , thereby “on” access transistor 212 and bit via MTJ component 214 . Allows current to flow from line 206 to bit line 204 . Sense and compare the current in the bit line, a logic high "1" corresponding to the state of the free layer within the MTJ component 214 and consequently the data ("1" or "0") being stored in the MRAM bit cell 200 . The current is detected by a sense amplifier (not shown) capable of outputting a " or a low "0". Access to any of the plurality of bit cells of the local memory array 102a is performed by accurately timing the application of voltage to the word lines and sensing the current on each bit line. The data of the bit cells in local memory array 102a may be transferred to the local ECC circuitry via bit lines 204 and 206, for example. Data in bit cells in local memory array 102a is transferred to or from circuitry external to macro 130a as shown in FIG. 1 , local I/O circuitry 106a, e.g. bit line 204, 206) is transmitted.

3 is a block diagram generally illustrating an exemplary ECC logic process 300 for MRAM error correction in accordance with one embodiment. In the illustrated embodiment, ECC logic process 300 includes local ECC logic 340 and global ECC logic 360 . In some embodiments, local ECC logic 340 is provided with a memory array or macro, and global ECC logic 360 is shared across multiple memory arrays or macros. For example, referring to FIG. 1 , the local ECC logic 340 may correspond to the local ECC circuit 140a in which the local memory array 102a is provided in the local memory macro 130a, and the global ECC logic is plural. It may correspond to the global ECC circuit 160 shared among the memory macros 130a - n.

The local ECC logic 340 includes a syndrome s1 generator 342 , a syndrome s3 generator 344 , and an error checking circuit 346 . MRAM bit cells 200 in memory arrays 102a-n store both data and parity bits for error detection and correction. In the example shown, ECC logic process 300 operates on code words read from local memory array 102a, eg, N-bit length read data read from MRAM macro 130a. In some embodiments, only partial decoding of the read data is required, since only the syndromes s1 and s3 are needed to determine whether the read data has an error. Syndromes s1, s3 may be a single numeric element, syndromes s1, s3 may each be a vector of a plurality of numeric elements, or syndromes s1, s3 may be a matrix of a plurality of numeric elements. Syndrome s1 generator 342 performs matrix multiplication on the read data using a predefined parity check matrix to arrive at syndrome s1, and similarly, syndrome s3 generator 344 pre-defined to arrive at syndrome s3 Matrix multiplication is performed on the parity check matrix. The error checking circuit 346 is configured to evaluate the syndromes s1, s3 and to determine whether the read data, eg, a code word, contains one or more errors.

If it is determined by the error checking circuitry 346 that the read data contains at least one error, then full decoding of the read data requires global ECC logic 360 . Global ECC logic 360 includes x^3 (cubic of x) calculation circuit 351, encoder (EN) calculation circuit 352, check bit generator 353, XOR (exclusive OR) calculation circuit 354, reciprocal finite field and error correction circuitry 362 such as an (inverse) computation circuit 355 and a Galois Field (GF) multiple computation circuit 356 . In some embodiments, the EN calculation circuit 352 operates on the read data and outputs a single bit that encodes whether the code word needs to be written back to the local memory array 102a after correction. For example, the EN calculation circuit 352 may be an encoder stage of a BCH cyclic error correction code. In some embodiments, the EN calculation circuit 352 allows the global ECC logic 360 to perform additional error detection in addition to correction, for example, SECDED (Single-Error Correcting (SEC) and double error). Like Double-Error Detecting (DED)), add a parity bit. In the embodiment shown in FIG. 3 , the syndromes s1 , s3 are calculated in the local ECC logic 340 and transmitted and used by the global ECC logic 360 . Specifically, x^3 computation circuit 351 operates on syndrome s1 to arrive at s1^3, and XOR computation circuit 354 operates on syndrome s3 and the resulting s1^3 from cubic computation circuit 351 to s3 and s1^3 and output a vector according to the XOR truth table. The reciprocal calculation circuit 355 operates on the syndrome s1 and outputs the reciprocal of the syndrome s1 , and the GF multiple calculation circuit 356 operates on the outputs of the reciprocal calculation circuit 355 and the XOR calculation circuit 354 . In some embodiments, the GF multiple computation circuit 356 may be a decoder stage of a BCH cyclic error correction code including error detection and error correction. In some embodiments, the GF multiple computation circuit 356 operates on the code word through multiplication and accumulation within the Galois field of all data bits, where the data bits are treated as coefficients of a polynomial. The output of the GF multiple calculation circuit 356 is input to the error correction circuit 362 together with the read data and the syndrome s1. The output of the error correction circuit 362 is an error corrected code word. Next, the check bit generator 353 operates on the corrected word, e.g., data without parity bits, and encodes the parity bits according to a predefined parity check matrix of the selected ECC type or scheme, resulting in a local code array. Form a corrected code word to be written in 102a.

FIG. 4 is a flow diagram of a method 400 for correcting an MRAM error using the ECC logic process 300 shown in FIG. 3 . Method 400 begins at step 402, where syndromes s1, s3 are calculated from read data as part of a memory refresh operation for the memory array. For example, a code word from one of a plurality of macros 130a-n comprising a local memory array 102a-n is read, and a local memory array 102a-n where read data begins during a refresh period; Syndromes s1, s3 are calculated by performing matrix multiplication on the read data using a parity check matrix predefined in the relevant local ECC circuits 140a-n. In some embodiments, the calculation of the syndromes s1 and s3 may be performed using the s1 syndrome generator 342 and the s3 syndrome generator 344 in the local ECC logic 340 as shown in FIG. 3 . In step 404 , syndromes s1 , s3 are evaluated to determine whether the code word has at least one error using, for example, error checking 346 within local ECC logic 340 . If there are no errors, the method 400 ends for that code word, and in step 402 begins for the next code word of the refresh cycle for the local memory arrays 102a-n. If at least one error exists, the method 400 provides a global associated with a plurality of local macros including the local macro from which the read data and the current read data determined to have the at least one error in which the syndrome s1, s3 is determined to have an error. Proceed to step 406 where it is input to a global ECC circuit 160 , such as ECC logic 360 . Whether or not the code word needs to be written back to the local memory array 102 after correction is determined from the read data using, for example, the EN calculation circuit 352 . For example, the EN calculation circuit 352 may be an encoder stage of a BCH cyclic error correction code. In some embodiments, the EN calculation circuit 352 allows the global ECC logic 360 to perform additional error detection in addition to correction, for example, SECDED (Single-Error Correcting (SEC) and double error). Like Double-Error Detecting (DED)), add a parity bit. In step 408 , s1^3 is calculated by the x^3 calculation circuit 351 in the global ECC logic 360 . In step 410, the XOR of the inputs s1^3, s3 is computed by, for example, an XOR calculation circuit 354 in the global ECC logic 360, and the reciprocal of s1 is computed by, for example, the global ECC logic 360 ) is calculated by the reciprocal calculation circuit 355 in In step 412, the GF multiple is computed by the GF multiple computation circuit 356 using, for example, the reciprocal s1 and the output from the XOR computation. In some embodiments, the GF multiple computation circuit 356 may be a decoder stage of a BCH cyclic error correction code including error detection and error correction. In some embodiments, the GF multiple computation circuit 356 operates on the code word through multiplication and accumulation in the Galois field of all data bits, where the data bits are treated as coefficients of a polynomial. In step 414 , a corrected code word is computed using the read data and the output of the GF multiplex and syndrome s1 calculation, for example by error correction circuitry 362 in global ECC logic 360 . In step 416 , a corrected word, eg, corrected data, is extracted from a corrected code word and check bit generator, eg, a check bit generator 353 within the global ECC logic 360 , and an ECC type selected Alternatively, the corrected data is encoded into parity bits using a pre-defined parity check matrix according to a scheme. Next, the corrected and encoded code word is written back to the local macro 130 .

5 is a block diagram generally illustrating an exemplary ECC logic process 500 for MRAM error correction in accordance with one embodiment. Compared to ECC logic process 300 of FIG. 3 , in ECC logic process 500 , check bit generator 353 is no longer included in global ECC logic 360 , but is included in local ECC logic 340 . . This difference from the ECC logic process 300 is that the operation of encoding the parity bits into corrected data and writing the resulting corrected codeword to the local memory array 102a is a local ECC associated with the local memory array 102a. Offloading to logic 340 , global ECC logic 360 encodes the parity bits and writes corrected code words for a plurality of memory macros 130a - n that share global ECC logic 360 . Take no more responsibility.

6 is a flowchart of a method 600 of correcting an MRAM error using an ECC logic process 500 . Method 600 is similar to method 400 above, but in step 616 the same operations included in step 416 are performed within the local ECC rather than the global ECC, so that the operation is as described above with respect to FIG. 5 . The difference is that it is offloaded to the local ECC logic circuit. Specifically, step 616 extracts a corrected word, eg, corrected data, from the corrected code word and converts the corrected data into parity bits using a pre-defined parity check matrix according to the selected ECC type or scheme. encoding and writing the corrected encoded code word back to a local macro associated with the local ECC logic circuitry.

7 is a block diagram generally illustrating an exemplary ECC logic process 700 for MRAM error correction in accordance with one embodiment. The ECC logic process 700 is similar to the ECC logic process 500 above, with two differences. The first difference is that the syndrome s1 generator 342 and the syndrome s3 generator 344 overlap within the global ECC logic 360 . In the global ECC logic 360, overlapping the syndrome s1 generator 342 and the syndrome s3 generator 344 may reduce the number of connections required in the overall hierarchical ECC scheme, and may simplify the layout structure. have. For example, ECC logic process 300, 500 supports all local ECC circuits 140a-n and local I/O circuits 106a-n to transmit read data and syndromes s1, s3, Requires ECC circuit 160 to support receiving syndromes s1, s3 along with read data. In contrast, ECC logic process 700 only requires local ECC circuitry 140a-n and local I/O circuitry 106a-n to support sending read data, and global ECC circuitry 160 It only requires support for receiving read data. As such, in some embodiments, the connections necessary for the transmission of syndromes s1, s3 between the local I/O circuits 106a-n and the global ECC circuitry 160 may be eliminated using the ECC logic process 700 and , this may simplify the layout structure of the MRAM device 100 .

The second difference is that the error detection circuitry 357 is included within the global ECC logic 360 . Similar to the error checking circuitry 346 , the error detection circuitry 357 is configured to determine whether the read data, e.g., a codeword, contains at least one error, although this cannot be done within the global ECC logic circuitry 360 . is done The error detection circuit 357 receives the outputs of the EN calculation circuit 351, s1, s3, and s1^3 as inputs, and outputs whether the read data contains at least one error. The error detection circuit 357 may output whether there is at least one error in the read data or at least two errors in the read data, and output whether there are at least three errors in the read data.

8 is a flow diagram of a method 800 for correcting an MRAM error using an ECC logic process 700 . Method 800 is similar to method 600 above, but with two differences. First, step 406 is replaced with step 806, wherein the syndromes s1, s3 are not input from the same operation included in step 406 of methods 400, 600, but rather from the global ECC circuit ( 160) (eg, global ECC logic 360). Second, between steps 408 and 410 , in step 809 , whether an error exists in the read data and the number of errors is determined by the global ECC circuit 160 (eg, error detection circuit 357 ). )) is calculated within

9 is a block diagram generally illustrating an exemplary ECC logic process 900 for MRAM error correction in accordance with one embodiment. The ECC logic process 900 is similar to the ECC logic process 700 above, but with four differences. First, the syndrome s1 generator 342 and the syndrome s3 generator are no longer redundant within the global ECC logic 360 . Second, the cube calculation circuit 351 , the EN calculation circuit 352 , and the error detection circuit 357 are included in the local ECC logic 340 and are no longer included in the global ECC logic 360 . Including the cube calculation circuit 351 , the EN calculation circuit 352 , and the error detection circuit 357 within the local ECC logic 340 increases the computational utility and power of the local ECC logic 340 . For an MRAM device 100 that experiences a relatively high data error rate, both the energy consumption burden of data movement and the latency of the data due to the offload of error detection and correction operations to the shared global ECC circuit 160 are dependent on local memory. The area savings benefit of eliminating the circuitry to perform these operations within macros 130a-n may be outweighed. In this case, the efficiency of the MRAM device 100 can be increased by balancing data latency, energy consumption, and area associated with error checking by increasing the operations performed locally. For example, by including the EN calculation and the syndrome s1 cube calculation, the local ECC logic 340 of the ECC logic process 900 may include error detection, e.g., via the error detection circuit 357, This makes it possible to more accurately detect the number of errors, including detecting whether an error exists within the code word and the code word and the number of errors within the word.

The third difference is that the error checking circuit 351 is omitted. A fourth difference is that the check bit generator 353 is once again included in the global ECC logic 360 rather than the local ECC logic 340 , similar to the ECC logic process 300 .

10 is a flow diagram of a method 1000 for correcting an MRAM error using an ECC logic process 900 . Method 1000 is similar to method 800 above with four differences. First, step 1003 is included after step 402, where s1^3 and EN are calculated by x^3 calculation circuit 351 and EN calculation circuit 352, respectively, within local ECC logic 340, respectively. do. Second, step 404 is replaced by step 1004, where the presence of errors in the read data and the number of errors in the read data are calculated by the error detection circuitry 357 in the local ECC logic 340, s1, Based on s3, s1^3, and EN calculations. If there are no errors, the method 1000 ends for that code word and begins at step 402 of the method 1000 for the next code word in a refresh cycle for the local memory array 102a. Third, if there is at least one error, the method 1000 proceeds to step 1006 where the read data, the syndromes s1 , s3 , s1^3 and the number of detected errors are input to the global ECC logic 360 . . Fourth, method 1000 replaces step 616 of method 800 with step 416 of method 400 . That is, in step 416 of method 1000 , a corrected word, eg, corrected data, is extracted from the corrected code word, and check bit generator 353 in global ECC logic 360 is selected ECC type Alternatively, the corrected data is encoded with parity bits using a parity check matrix defined in advance according to a scheme, and the corrected and encoded code word is written back to the local macro 130 .

11 is a block diagram generally illustrating an example ECC logic process 1100 for MRAM error correction in accordance with one embodiment. ECC logic process 1100 is similar to ECC logic process 900 above, with the difference that check bit generator 353 is no longer contained within global ECC logic 360 but within local ECC logic 340 . As discussed above with respect to ECC logic process 500 of FIG. 5 , this difference affects the operation of encoding the parity bits into corrected data and writing the resulting corrected codeword to the local memory array 102a. Offloading to the local ECC logic 340 associated with the memory array 102a , the global ECC logic 360 further encodes parity and a plurality of memory macros 130a - n sharing the global ECC logic 360 . ) and not responsible for rewriting the corrected code word for

12 is a flow diagram of a method 1200 for correcting an MRAM error using an ECC logic process 1100 . Method 1200 is similar to method 1000 above, but step 416 is replaced with step 616, extracting a corrected word, e.g., corrected data from a corrected code word, selected ECC encoding the corrected data into parity bits using a predefined parity check matrix according to type or manner, and writing the corrected encoded code words back to the local memory array 102 associated with the local ECC logic 340 The difference is that this step is performed within local ECC logic 340 such as methods 600 and 800 , rather than within global ECC logic 360 .

13 is a block diagram generally illustrating an example ECC logic process 1300 for MRAM error correction in accordance with one embodiment. The ECC logic process 1300 is similar to the ECC logic process 1100 above, except that the syndrome s1 generator 342 , the syndrome s3 generator 344 and the cube calculation circuit 351 are duplicated within the global ECC logic 360 . There is this. As described above with respect to the connection of FIG. 7 , the overlapping of the syndrome s1 generator 342 , the syndrome s3 generator 344 , and the cube calculation circuit 351 within the global ECC logic 360 is within the overall hierarchical ECC scheme. The number of connections required can be reduced and the layout can be simplified.

14 is a flow diagram of a method 1400 of correcting an MRAM error using an ECC logic process 1300 . Method 1400 is similar to method 1200 above, with the difference that step 1406 replaces step 1006 . In other words, the syndromes s1, s3, and s1^3 are calculated in the global ECC logic 360 by overlapping the quantities calculated in the local ECC logic 340 . This is instead of inputting the quantity from the local ECC logic 340 to the global ECC logic 360 , as is performed in step 1006 of the method 1200 . As such, step 1406 of method 1400 overlaps the calculations of s1, s3, and s1^3 within global ECC logic 360, as well as read data and errors detected in step 1004. and inputting the number of to the global ECC logic 360 . This is similar to the redundancy that occurs in the method 800 shown in FIG. 8 with respect to the ECC process 700 of FIG. 7 .

15 is a block diagram generally illustrating an example ECC logic process 1500 for MRAM error correction in accordance with one embodiment. ECC logic process 1500 is similar to ECC logic process 900 above, except that XOR circuit 354, reciprocal calculation circuit 355 and GF multiple calculation circuit 356 are included in local ECC logic 340, more There is a difference that the above is not included in the global ECC logic 360 . Including the XOR circuit 354 , the reciprocal calculation circuit 355 , and the GF multiple calculation circuit 356 within the local ECC logic 340 increases the computational utility and power of the local ECC logic 340 . As described above with respect to the ECC process 900 and FIG. 9 , the efficiency of the MRAM device 100 increases the area and energy consumption associated with error checking by increasing the operations performed locally as the data error rate increases. and by balancing the data latency. For example, by implementing more error checking circuitry locally within the local ECC circuits 140a-n to reduce data latency and energy consumption associated with moving data to the shared global ECC circuit 160 keep your balance For example, in ECC logic process 1500 , local ECC logic 340 performs all ECC operations locally, except for error correction and coding and writing the error corrected data back to the local macro.

16 is a flow diagram of a method 1600 for correcting an MRAM error using an ECC logic process 1500 . Method 1600 is similar to method 1000 above, with five differences. First, method 1600 replaces step 1004 of method 1000 with step 1604 . Step 1604 of method 1600 performs the same operation as step 1004 of method 1000, i.e., based on the calculation of s1, s3, s1^3 and EN, an error is detected in the read data in the local ECC logic 340. It performs a calculation of whether it exists and the number of errors. The only difference is that if there is an error in the read data, step 1604 proceeds to step 1610 of method 1600 rather than step 1006 . This is due to the additional circuitry included within the local ECC logic 340 in the ECC logic process 1500 . Second, step 1006 is not performed in method 1600 , but rather as a third difference from method 1000 , step 1610 proceeds from step 1604 of method 1600 . In step 1610, the XOR of s3 and s1^3 is computed, e.g., by XOR computation circuitry 354, together with reciprocal number s1, e.g. by reciprocal computation circuitry 355 in local ECC logic 340. is calculated by Fourth, in step 1612 , the GF multiple is computed within the local ECC logic 340 . Fifth, at step 1613 , the read data, the number of errors detected, s1 , and the GF multiple calculation result are input to the global ECC logic 360 and calculation of the corrected code word at step 414 of the method 1600 . is used for

17 is a block diagram generally illustrating an example ECC logic process 1700 for MRAM error correction in accordance with one embodiment. ECC logic process 1700 is similar to ECC logic process 1500 above, with the difference that check bit generator 353 is no longer contained within global ECC logic 360 but within local ECC logic 340 . 5 and 11, this difference in ECC logic process 1700 involves the operation of encoding the parity bits into corrected data and writing the resulting corrected codeword to the local memory array 102a. offloads the operation to the local ECC logic 340 associated with the local memory array 102a so that the global ECC logic 360 encodes parity and a plurality of memory macros 130a sharing the global ECC logic 360 . -n) no longer be responsible for writing the corrected code word.

18 is a flow diagram of a method 1800 for correcting an MRAM error using an ECC logic process 1700 . Method 1800 is similar to method 1600 above, but step 416 is replaced with step 616, extracting a corrected word, e.g., corrected data from the corrected codeword, selected ECC encoding the corrected data into parity bits using a predefined parity check matrix according to type or manner, and back to the local memory array 102 associated with the local ECC logic 340 the corrected encoded code words The difference is that the writing step is performed within local ECC logic 340 such as methods 600 , 800 , 1200 rather than within global ECC logic 360 .

19 is a flow diagram of a method 1900 for correcting MRAM errors using a hierarchical ECC logic process in accordance with some embodiments. Method 1900 begins at step 1902 in which a plurality of memory macros, eg, MRAM memory macros 130a-n, are provided, each comprising at least an array of memory cells and local ECC logic circuitry. In some embodiments, the plurality of memory macros includes local memory arrays 102a-n, each of which includes local ECC logic 140a-n, respectively. At step 1904, a global ECC logic circuit is provided that is remote from and coupled to each of the plurality of MRAM macros. In some embodiments, the global ECC logic circuit includes global ECC logic 160 . In step 1906, data from the local MRAM macro is checked as part of a refresh cycle in which a portion of the local MRAM memory, eg, read data or code words, is checked for errors within the local ECC logic circuit. If no errors are found in a particular code word, the next code word in the macro is checked as part of the refresh cycle. The method 1900 then proceeds to a step 1908, where if at least one error is found within the memory array of the local macro, the data examined and found to have the at least one error, e.g., at least one The code word with the error is sent to the global ECC logic with the output of the calculation circuit in the local ECC logic circuit. In step 1910 the data with at least one error is corrected in the global ECC logic circuit, and in step 1912 the corrected data is written back to the local macro memory array.

Accordingly, the disclosed examples provide error detection and correction for memory devices, particularly short-lived memory devices such as MRAMs that require periodic refreshes. By using a hierarchical ECC approach in which some ECC functions are provided locally in the memory macro and other ECC functions are provided globally, power reduction for the MRAM device as well as macro area reduction can be achieved with a sufficiently low error rate. Certain disclosed embodiments include a memory device, such as an MRAM memory device, wherein the memory device includes a plurality of memory macros each comprising an array of memory cells and a first ECC circuit. The first ECC circuit is configured to detect data errors in each memory macro. A second ECC circuit is remote from and communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the data error detected from the first ECC circuit of the plurality of memory macros, correct the data error, and write the corrected data to the memory array.

According to a further aspect, the ECC system includes a plurality of first ECC circuits. Each of the plurality of first ECC circuits is communicatively coupled to a respective memory array and configured to detect data errors in each memory array. A second ECC circuit is communicatively coupled to each of the plurality of first ECC circuits and is configured to receive and correct data errors detected from the first plurality of ECC circuits.

According to a further aspect, a method includes providing a plurality of memory macros each comprising an array of memory cells and a first ECC circuit. The method includes providing a second ECC circuit remote from and communicatively coupled to each of the plurality of memory macros, and checking for data errors in the memory array with the first ECC circuit. It further comprises the step of refreshing (refreshing). If a data error is identified by the first ECC circuit, the method includes forwarding the detected data error to a second ECC circuit, correcting the data error by the second ECC circuit, and storing the corrected data into memory. and writing to the array.

The foregoing outlines features of some embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages as the embodiments introduced in this disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Examples

Embodiment 1. A memory device comprising:

a plurality of memory macros, each memory comprising an array of memory cells and a first error correction code (ECC) circuit configured to detect data errors in each memory macro macro;

a second ECC circuit remote from and communicatively coupled to each of the plurality of memory macros, receiving the detected data error from a first ECC circuit of the plurality of memory macros, the data error and the second ECC circuit configured to write the corrected data to the memory array.

Embodiment 2. The memory device of embodiment 1, wherein the memory macros each comprise a magnetic random access memory (MRAM) macro.

Embodiment 3. The method according to Embodiment 2, wherein each of the MRAM macros comprises:

An array of MRAM bit cells, each MRAM bit cell comprising:

magnetic tunnel junction element;

an access transistor coupled to the magnetic tunnel junction element;

a first bit line coupled to the access transistor;

a second bit line coupled to the magnetic tunnel junction element;

an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and

and local input-output circuitry coupled to the first bit line and the second bit line of the MRAM bit cell.

Embodiment 4. The method of Embodiment 3, wherein the first ECC circuit comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line; and

and an error checking circuit coupled to an output of each of the first syndrome s1 generator and the second syndrome s3 generator.

Embodiment 5. The method according to embodiment 4, wherein the second ECC circuit comprises:

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

a syndrome s1 inversion circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator;

a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

Embodiment 6. The method according to Embodiment 3, wherein the first ECC circuit comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line;

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

and an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN computation circuit, and the syndrome s1^3 computation circuit.

Embodiment 7. The method according to Embodiment 6, wherein the second ECC circuit comprises:

a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator;

a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

Embodiment 8. The method according to embodiment 3, wherein the first ECC circuit comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line;

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit;

a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator; and

and a GF multiple computation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 reciprocal circuit.

Embodiment 9. The method of embodiment 8, wherein the second ECC circuit comprises:

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator, and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

Example 10. An ECC system comprising:

a plurality of first ECC circuits, each of the plurality of first ECC circuits configured to be communicatively coupled to a respective memory array, and configured to detect data errors within the respective memory array. 1 ECC circuit; and

a second ECC circuit, communicatively coupled to each of the plurality of first ECC circuits, and configured to receive the detected data error from the plurality of first ECC circuits and correct the data error. An ECC system comprising 2 ECC circuits.

Embodiment 11. The method according to embodiment 10, wherein each of the plurality of first ECC circuits comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line; and

an error checking circuit coupled to an output of each of the first syndrome s1 generator and the second syndrome s3 generator;

The second ECC circuit,

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator;

a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator, and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

*

Embodiment 12. The method according to Embodiment 10, wherein each of the plurality of first ECC circuits comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line;

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

an error checking circuit coupled to the output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit;

The second ECC circuit,

a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator;

a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator, and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

Embodiment 13. The method according to Embodiment 10, wherein each of the plurality of first ECC circuits comprises:

a first syndrome s1 generator coupled to the first bit line and the second bit line;

a second syndrome s3 generator coupled to the first bit line and the second bit line;

an EN calculation circuit coupled to the local input/output circuitry;

a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;

an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit;

a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;

a syndrome comparator coupled to an output of the syndrome s1^3 generator and an output of the second syndrome s3 generator; and

a GF multiple calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 reciprocal circuit;

The second ECC circuit,

an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator, and the GF multiple calculation circuit; and

and a check bit generator circuit for correcting the erroneous MRAM cell.

Example 14. A method comprising:

providing a plurality of memory macros, wherein the plurality of memory macros each include an array of memory cells and a first ECC circuit;

providing a second ECC circuit, wherein the second ECC circuit is remote from and communicatively coupled to each of the plurality of memory macros;

refreshing the memory array, the method comprising: checking the memory array for data errors in the memory array with the first ECC circuit;

if the data error is identified by the first ECC circuit, forwarding the detected data error to the second ECC circuit;

correcting the data error by the second ECC circuit; and

and writing the corrected data to the memory array.

Embodiment 15. The method of embodiment 14, wherein checking for data errors in the MRAM array with the first ECC circuit comprises:

generating a syndrome s1 based on data received from the MRAM array;

generating a syndrome s3 based on data received from the MRAM array; and

and error checking based on the syndrome s1 and the syndrome s3.

Embodiment 16. The method of embodiment 15, wherein correcting the data error with the second ECC circuit comprises:

generating an EN based on data received from the MRAM array;

generating a syndrome s1^3 based on the syndrome s1;

generating a syndrome s1 inverse based on the syndrome s1;

comparing the syndrome s1^3 with the syndrome s3;

generating a GF multiple calculation based on the reciprocal of the syndrome s1 and the comparison of the syndrome s1^3 with the syndrome s3;

generating a check bit error correction based on the EN, the syndrome s1, and the GF multiple calculation; and

and writing the check bit error correction to the MRAM array to correct the error.

Embodiment 17. The method of embodiment 14, wherein checking for data errors in the MRAM array with the first ECC circuit comprises:

generating a syndrome s1 based on data received from the MRAM array;

generating a syndrome s3 based on data received from the MRAM array;

generating an EN based on data received from the MRAM array;

generating a syndrome s1^3 based on the syndrome s1; and

and an error checking step based on the syndrome s1, the syndrome s3, the EN and the syndrome s1^3.

Embodiment 18. The method of embodiment 17, wherein correcting the data error with the second ECC circuit comprises:

generating a syndrome s1 inverse based on the syndrome s1;

comparing the syndrome s1^3 with the syndrome s3;

generating a GF multiple calculation based on the reciprocal of the syndrome s1 and the comparison of the syndrome s1^3 with the syndrome s3;

generating a check bit error correction based on the EN, the syndrome s1, and the GF multiple calculation; and

and writing the check bit error correction to the MRAM array to correct the error.

Embodiment 19. The method of embodiment 14, wherein checking for data errors in the MRAM array with the first ECC circuit comprises:

generating a syndrome s1 based on data received from the MRAM array;

generating a syndrome s3 based on data received from the MRAM array;

generating an EN based on data received from the MRAM array;

generating a syndrome s1^3 based on the syndrome s1;

an error checking step based on the syndrome s1, the syndrome s3, the EN, and the syndrome s1^3;

generating a syndrome s1 inverse based on the syndrome s1;

comparing the syndrome s1^3 with the syndrome s3; and

and generating a GF multiple calculation based on the reciprocal of the syndrome s1 and the comparison of the syndrome s1^3 with the syndrome s3.

Embodiment 20. The method according to embodiment 19, wherein correcting the data error with the second ECC circuit comprises:

generating a check bit error correction based on the EN, the syndrome s1, and the GF multiple calculation; and

and writing the check bit error correction to the MRAM array to correct the error.

Claims (6)

A memory device comprising:
a plurality of memory macros, each comprising a memory array of memory cells and a first error correction code (ECC) circuit configured to detect data errors in each memory macro memory macro;
a second ECC circuit remote from and communicatively coupled to each of the plurality of memory macros, receiving the detected data error from a first ECC circuit of the plurality of memory macros; the second ECC circuit is configured to correct the data error received from the ECC circuit and write the corrected data to the memory array;
the memory macros each include a magnetic random access memory (MRAM) macro,
Each of the MRAM macros,
An array of MRAM bit cells, each MRAM bit cell comprising:
magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element; and
an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and
local input-output circuitry coupled to a first bit line and a second bit line of the MRAM bit cell
further comprising,
The first ECC circuit,
a first syndrome s1 generator coupled to the first bit line and the second bit line;
a second syndrome s3 generator coupled to the first bit line and the second bit line;
an EN calculation circuit coupled to the local input/output circuitry;
a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator; and
an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit
A memory device comprising: According to claim 1, wherein the second ECC circuit,
a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;
a syndrome comparator coupled to an output of the syndrome s1^3 calculation circuit and an output of the second syndrome s3 generator;
a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;
an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator and the GF multiple calculation circuit; and
and a check bit generator circuit to correct the erroneous MRAM bit cell. A memory device comprising:
a plurality of memory macros, each comprising a memory array of memory cells and a first error correction code (ECC) circuit configured to detect data errors in each memory macro memory macro;
a second ECC circuit remote from and communicatively coupled to each of the plurality of memory macros, receiving the detected data error from a first ECC circuit of the plurality of memory macros; and correcting the data error received from the ECC circuit and writing the corrected data to the memory array.
including,
each of the memory macros comprises a magnetic random access memory (MRAM) macro;
Each of the MRAM macros,
An array of MRAM bit cells, each MRAM bit cell comprising:
magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element;
an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and
local input-output circuitry coupled to a first bit line and a second bit line of the MRAM bit cell
include more
The first ECC circuit,
a first syndrome s1 generator coupled to the first bit line and the second bit line;
a second syndrome s3 generator coupled to the first bit line and the second bit line; and
an error checking circuit coupled to an output of each of the first syndrome s1 generator and the second syndrome s3 generator
including,
The second ECC circuit,
an EN calculation circuit coupled to the local input/output circuitry;
a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;
a syndrome s1 inversion circuit coupled to an output of the first syndrome s1 generator;
a syndrome comparator coupled to an output of the syndrome s1^3 calculation circuit and an output of the second syndrome s3 generator;
a GF multiple calculation circuit coupled to an output of the syndrome comparator and an output of the syndrome s1 reciprocal circuit;
an error correction circuit coupled to the local input/output circuitry, the syndrome s1 generator and the GF multiple calculation circuit; and
Check bit generator circuit to correct the MRAM bit cell in error
A memory device comprising: A memory device comprising:
a plurality of memory macros, each comprising a memory array of memory cells and a first error correction code (ECC) circuit configured to detect data errors in each memory macro memory macro;
a second ECC circuit remote from and communicatively coupled to each of the plurality of memory macros, receiving the detected data error from a first ECC circuit of the plurality of memory macros; and correcting the data error received from the ECC circuit and writing the corrected data to the memory array.
including,
the memory macros each include a magnetic random access memory (MRAM) macro,
Each of the MRAM macros,
An array of MRAM bit cells, each MRAM bit cell comprising:
magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element; and
an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and
local input-output circuitry coupled to a first bit line and a second bit line of the MRAM bit cell
further comprising,
The first ECC circuit,
a first syndrome s1 generator coupled to the first bit line and the second bit line;
a second syndrome s3 generator coupled to the first bit line and the second bit line;
an EN calculation circuit coupled to the local input/output circuitry;
a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator;
an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit;
a syndrome s1 reciprocal circuit coupled to an output of the first syndrome s1 generator;
a syndrome comparator coupled to an output of the syndrome s1^3 calculation circuit and an output of the second syndrome s3 generator; and
GF multiple calculation circuit coupled to the output of the syndrome comparator and the output of the syndrome s1 reciprocal circuit
A memory device comprising: In the ECC system,
a plurality of first ECC circuits, each of the plurality of first ECC circuits configured to be communicatively coupled to a respective memory array, and configured to detect data errors within the respective memory array. 1 ECC circuit; and
a second ECC circuit, communicatively coupled to each of the plurality of first ECC circuits, to receive the detected data error from the plurality of first ECC circuits, and to receive the data received from the plurality of first ECC circuits and the second ECC circuit configured to correct an error;
Each of the memory arrays,
An array of MRAM bit cells, each MRAM bit cell comprising:
magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element; and
an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and
local input/output circuitry coupled to a first bit line and a second bit line of the MRAM bit cell
further comprising,
The first ECC circuit,
a first syndrome s1 generator coupled to the first bit line and the second bit line;
a second syndrome s3 generator coupled to the first bit line and the second bit line;
an EN calculation circuit coupled to the local input/output circuitry;
a syndrome s1^3 calculation circuit coupled to an output of the first syndrome s1 generator; and
an error checking circuit coupled to an output of each of the first syndrome s1 generator, the second syndrome s3 generator, the EN calculation circuit, and the syndrome s1^3 calculation circuit
Including, ECC system. In the method,
providing a plurality of memory macros, wherein the plurality of memory macros each include a memory array of memory cells and a first ECC circuit;
providing a second ECC circuit, wherein the second ECC circuit is remote from and communicatively coupled to each of the plurality of memory macros;
refreshing the memory array, the method comprising: checking the memory array for data errors in the memory array with the first ECC circuit;
if a data error is identified by the first ECC circuit, forwarding the identified data error to the second ECC circuit;
correcting the data error received from the first ECC circuit by the second ECC circuit; and
writing the corrected data to the memory array;
the memory macros each include a magnetic random access memory (MRAM) macro,
Each of the MRAM macros,
An array of MRAM bit cells, each MRAM bit cell comprising:
magnetic tunnel junction element;
an access transistor coupled to the magnetic tunnel junction element;
a first bit line coupled to the access transistor;
a second bit line coupled to the magnetic tunnel junction element; and
an array of MRAM bit cells comprising a word line coupled to the gate of the access transistor; and
local input/output circuitry coupled to a first bit line and a second bit line of the MRAM bit cell
further comprising,
Checking for data errors in the memory array with the first ECC circuit comprises:
generating a syndrome s1 based on data received from the first bit line and the second bit line;
generating a syndrome s3 based on data received from the first bit line and the second bit line;
generating an EN based on data received from the local input/output circuit unit;
generating a syndrome s1^3 based on the syndrome s1; and
checking an error based on the syndrome s1, the syndrome s3, the EN, and the syndrome s1^3
A method comprising

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