KR20200058129A - Semiconductor package comprising organic interposer - Google Patents

Abstract

The present disclosure relates to a semiconductor package including an organic interposer, including: a semiconductor chip having an active surface on which a connection pad is disposed; a connection structure disposed on the active surface of the semiconductor chip and including an insulation layer and a redistribution layer electrically connected to the connection pad; and an under bump metallurgy (UBM) layer disposed on the connection structure and electrically connected to the redistribution layer of the connection structure; and an electric connection metal disposed on the UBM layer, wherein the UBM layer includes a UBM pad disposed on the insulation layer of the connection structure and having a T-shape, a surface treatment layer disposed on a lower surface of the UBM pad to expose a side surface of the UBM pad and including at least one plating layer, and a UBM via passing through at least a part of the insulation layer of the connection structure to electrically connect the redistribution layer of the connection structure to the UBM pad.

Description

Semiconductor package including organic interposer {SEMICONDUCTOR PACKAGE COMPRISING ORGANIC INTERPOSER}

The present disclosure relates to a semiconductor package comprising an organic interposer.

The interposer market is growing due to the high specification of sets and the adoption of HBM (High Bandwidth Memory). Currently, silicon is mainly used as an interposer material, but glass or organic methods have been developed for large area and low cost. The part that connects the interposer to the main board of the set is called the UBM (Under Bump Metallurgy) layer, and the reliability of the connection part is greatly affected by the structure of the UBM layer, so it is necessary to optimize it.

In particular, various surface treatments have been performed on the UBM layer to improve bonding reliability. Such surface treatment mainly uses electroless plating. In this case, the surface treatment layer is disposed on the side as well as the top surface of the pad, and various defects may occur after bonding with the solder. In addition, since the UBM layer is formed to have a relatively large thickness compared to the redistribution layer, when forming a connection structure including the redistribution layer on the UBM layer, it is difficult to implement a microcircuit due to undulation.

One of several objects of the present disclosure is to provide a semiconductor package including an organic interposer having a structure capable of preventing defects in the surface treatment layer and the UBM layer while simplifying the process.

One of the various solutions proposed through the present disclosure is that the surface treatment layer is formed only on the lower surface of the UBM pad, and when the UBM layer is formed, a part of the UBM pad is impregnated into the insulating layer so that the UBM pad has a T-shape. Is to do.

For example, a semiconductor package including an organic interposer according to an example proposed in the present disclosure, a semiconductor chip having an active surface on which a connection pad is disposed, disposed on an active surface of the semiconductor chip, and electrically connected to the connection pad A connection structure including a redistribution layer and an insulating layer connected to each other, and an UBM (Under Bump Metallurgy) layer disposed on the connection structure and electrically connected to the redistribution layer of the connection structure, and the UBM layer An electrical connection metal, the UBM layer is disposed on the insulating layer of the connection structure and has a T-shaped UBM pad, and is disposed on the lower surface of the UBM pad to expose the side surface of the UBM pad and at least one It includes a surface treatment layer including a plating layer, and UBM vias penetrating at least a portion of the insulating layer of the connection structure and electrically connecting the redistribution layer of the connection structure and the UBM pad.

As one of various effects of the present disclosure, a semiconductor package including an organic interposer having a structure capable of preventing defects in the surface treatment layer and the UBM layer while simplifying the process can be provided.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically illustrating a case in which a 3D BGA package is mounted on a main board of an electronic device.
4 is a cross-sectional view schematically illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.
5 is a cross-sectional view schematically illustrating a case in which a 2.5D organic interposer package is mounted on a main board.
6 is a cross-sectional view schematically showing an example of a semiconductor package including an organic interposer.
7A and 7B are enlarged views schematically showing another example of a semiconductor package including an organic interposer.
8A to 8E schematically show an example of a process for forming a semiconductor package including the organic interposer of FIG. 6.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shape and size of elements in the drawings may be exaggerated or reduced for a more clear description.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates the main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. They are also combined with other components described below to form various signal lines 1090.

The chip-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, CPU), graphics processor (eg, GPU), digital signal processor, encryption processor, microprocessor, microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included. It goes without saying that these parts 1020 may be combined with each other.

As network related parts 1030, Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols specified thereafter, including, but not limited to, many other wireless or wired Any of the standards or protocols can be included. In addition, it is needless to say that the network-related parts 1030 may be combined with each other along with the chip-related parts 1020.

Other parts 1040 include high frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-Firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. , But is not limited thereto, and other passive components used for various other purposes may be included. In addition, of course, other components 1040 may be combined with each other along with the chip-related component 1020 and / or the network-related component 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other parts include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), and a compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (e.g., hard disk drive) (not shown), compact disk (CD) (not shown), and DVD (digital versatile disk) (not shown), and the like, but is not limited to this, in addition to other types of electronic devices 1000 may be used for various purposes, including, of course, may be included.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, automotive, or the like. However, the present invention is not limited thereto, and of course, it may be any other electronic devices that process data.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the semiconductor package is applied to various electronic devices as described above for various purposes. For example, the motherboard 1110 is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically and / or electrically connected to the mainboard 1010, such as the camera 1130, are housed in the body 1101. Some of the parts 1120 may be chip-related parts, and some of them may be an interposer package 1121. The electronic device is not necessarily limited to the smart phone 1100, and, of course, may be other electronic devices as described above.

Semiconductor package containing organic interposer

In general, a semiconductor chip has a large number of fine electrical circuits integrated, but it cannot serve as a semiconductor finished product by itself, and there is a possibility that it is damaged by an external physical or chemical impact. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices or the like in a package state.

The reason for the need for semiconductor packaging is that from the viewpoint of electrical connection, there is a difference in the circuit width of the semiconductor chip and the main board of the electronic device. Specifically, in the case of a semiconductor chip, the size of the connection pad and the spacing between the connection pads are very fine, whereas in the case of a main board used in electronic devices, the size of the component mounting pad and the spacing of the component mounting pad are much larger than the scale of the semiconductor chip . Therefore, it is difficult to mount the semiconductor chip directly on such a main board, and a packaging technology capable of buffering the difference in circuit width between each other is required.

Hereinafter, a semiconductor package including an organic interposer manufactured by such a packaging technology will be described in more detail with reference to the drawings.

3 is a cross-sectional view schematically illustrating a case in which a 3D BGA package is mounted on a main board of an electronic device.

Among semiconductor chips, application specific integrated circuits (ASICs) such as graphics processing units (GPUs) are very expensive, so it is very important to perform packaging with high yield. For this purpose, a ball grid array (BGA) substrate 2210 or the like capable of redistributing thousands to hundreds of thousands of connection pads is first prepared before mounting of the semiconductor chip, and expensive of GPU 2220 or the like is prepared. The same semiconductor chip is subsequently mounted and packaged on a BGA substrate 2210 by surface mounting technology (SMT), and then finally mounted on the main board 2110.

Meanwhile, in the case of the GPU 2220, it is necessary to minimize a signal path with a memory such as a high bandwidth memory (HBM), and for this purpose, a semiconductor chip such as the HBM 2240 is interposer 2230. After mounting on the packaging, it is used to stack it in a package on package (POP: Package on Package) form on a package on which the GPU 2220 is mounted. However, in this case, there is a problem that the thickness of the device is too thick, and there is a limit to minimize the signal path.

4 is a cross-sectional view schematically illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.

As a method for solving the above-described problem, a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 on a silicon interposer 2250 are arranged side-by-side. It may be considered to manufacture a semiconductor package 2310 including a silicon interposer with a 2.5D interposer technology for packaging after mounting. In this case, the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads can be redistributed through the interposer 2250, and these can be electrically connected with a minimum path. In addition, when the semiconductor package 2310 including the silicon interposer is mounted on the BGA substrate 2210 and redistributed again, it can be finally mounted on the main board 2110. However, in the case of the silicon interposer 2250, not only is formation of a through silicon via (TSV) very difficult, but also the manufacturing cost is considerable, which is disadvantageous for large area and low cost.

5 is a cross-sectional view schematically illustrating a case in which a 2.5D organic interposer package is mounted on a main board.

As a method for solving the above-described problem, it may be considered to use the organic interposer 2260 instead of the silicon interposer 2250. For example, the organic interposer is a 2.5D interposer technology in which a first semiconductor chip such as GPU 2220 and a second semiconductor chip such as HBM 2240 are surface-mounted and packaged side by side on the organic interposer 2260. It is conceivable to manufacture the containing semiconductor package 2320. In this case, the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of connection pads can be redistributed through the interposer 2260, and these can be electrically connected with a minimum path. In addition, when the semiconductor package 2320 including such an organic interposer is mounted on the BGA substrate 2210 and redistributed again, it can be finally mounted on the main board 2110. In addition, it is advantageous for large area and low cost.

Meanwhile, in the case of the semiconductor package 2320 including such an organic interposer, the chips 2220 and 2240 are mounted on the interposer 2260 and then manufactured by performing a package process to mold or seal the chips. This is because it cannot be connected to the BGA substrate 2210 and the like because it is not handled unless a molding process is performed, and thus rigidity is maintained through molding. However, when the molding process is performed, warpage occurs due to mismatch of the coefficient of thermal expansion (CTE) between the interposer 2260 and the sealing material of the chips 2220, 2240, deterioration of underfill resin fillability, semiconductor Problems such as cracking between the chip and the sealing material may occur.

6 is a cross-sectional view schematically showing an example of a semiconductor package including an organic interposer.

Referring to FIG. 6, a semiconductor package 100A including an organic interposer according to an example includes semiconductor chips 111, 112, and 113 having an active surface on which connection pads 111P, 112P, and 113P are disposed, respectively. The encapsulant 160 that seals at least a portion of the (111, 112, 113), is disposed on the active surface of the semiconductor chip (111, 112, 113) and is electrically connected to each connection pad (111P, 112P, 113P) Connection structure 120 including redistribution layer 122, UBM layer 140 disposed on connection structure 120 and electrically connected to redistribution layer 122 of connection structure 120, and UBM layer 140 And an electrical connection metal 150 connected to the. The UBM layer 140 is disposed on the connection structure 120 and has a T-shaped UBM pad 142, a surface treatment layer 145 disposed only on the lower surface of the UBM pad 142, and a connection structure 120 It includes a UBM via 143 that penetrates at least a portion of the insulating layer 121 and electrically connects the redistribution layer 122 of the connection structure 120 and the UBM pad 142. The UBM pad 142 includes a T-shaped first layer 142a forming a lower portion and a second layer 142b forming an upper portion. The first layer 142a is located at the center of the second layer 142b, and the width of the first layer 142a is smaller than the width of the second layer 142b.

A conventional interposer forms a redistribution layer on an insulating layer, attaches a die on the redistribution layer, and performs a package process to mold it, separates the package from the carrier, and forms a via on the lower surface of the package in contact with the carrier, The UBM layer was formed through processes such as exposure and plating. This conventional method forms the last UBM layer, and is generally referred to as a UBM layer last construction method. In this last method of UBM layer, since it is difficult to move the process due to the bending problem in the package alone, it is necessary to use a separate carrier and there is a burden to establish a dedicated line for the UBM layer process. On the other hand, in the case of the UBM layer first method of forming the UBM layer first, no additional carrier is required, and a dedicated line for forming the UBM layer can be omitted, and the risk of foreign substances after the packaging process can be eliminated. However, since the UBM pad has a relatively thick thickness, when forming a redistribution layer on the UBM pad, there is a problem that defects due to undulation occur.

However, in the case of the semiconductor package 100A according to an example, the first region 142a, which is a part of the UBM pad 142, is manufactured to be impregnated in the insulating member while manufacturing by applying the UBM layer first method, as can be seen in the process described later. do. Therefore, the occurrence of undulation due to the thickness of the UBM pad 142 can be minimized, so that a fine pattern can be formed when the redistribution layer 122 of the connection structure 120 is formed, and occurrence of defects can be minimized. . In addition, since the UBM pad 142 has a T-shape, adhesion to the electrical connection metal 150 may be improved due to the step of the UBM pad 142.

In addition, the surface treatment layer 145 is disposed only on the lower surface of the UBM pad 142, so that at least the side surfaces can be exposed. According to an embodiment, the surface treatment layer 145 may be disposed only on a part of the lower surface of the UBM pad 142. The surface treatment layer 145 may include at least one plating layer that includes a different material from the UBM pad 142, and includes, for example, first and second plating layers 145a and 145b. For example, the first plating layer 145a may be a gold (Au) plating layer, and the second plating layer 145b may be made of a different material from the first plating layer 145a, for example, a nickel (Ni) plating layer. have. The second plating layer 145b may prevent the formation of an intermetallic compound between the first plating layer 145a and the UBM pad 142.

On the other hand, in the case of the semiconductor package 100A according to an example, the width of the upper surface of the UBM via 143 in contact with the redistribution layer 122 of the connection structure 120 is greater than the width of the lower surface in contact with the UBM pad 142. Here, the width is determined based on the cross-sectional view. When applying the last method of the UBM layer as in the prior art, the width of the upper surface of the UBM via is generally smaller than the width of the lower surface. On the other hand, in the case of the semiconductor package 100A according to an example, since the UBM layer first method is applied, the UBM via 143 may be formed in a so-called inverted trapezoid shape in which the width of the upper surface is wider than the width of the lower surface. In addition, as the redistribution layer 122 and the via 123 of the connection structure 120 form the UBM pad 142 and the UBM via 143, the UBM via 143 may be a filled-via. have.

Hereinafter, each configuration included in the semiconductor package 100A according to an example will be described in more detail.

The semiconductor chips 111, 112, and 113 may include, for example, a central processor (eg, CPU), graphics processor (eg, GPU), field programmable gate array (FPGA), digital signal processor, encryption processor, microprocessor, microcomputer It may be a processor chip such as a controller, or an analog-to-digital converter, a logic chip such as an application-specific IC (ASIC), or volatile memory (eg, DRAM), non-volatile memory (eg, ROM, flash memory), It may be a memory chip such as HBM (High Bandwidth Memory). Also, they may be arranged in combination with each other. As a non-limiting example, the first semiconductor chip 111 and the third semiconductor chip 113 may be memory chips such as HBM, and the second semiconductor chip 112 may be a processor chip such as an AP, but are not limited thereto. no. The semiconductor chips 111, 112, and 113 may be electrically connected to each other through the connection structure 120.

The semiconductor chips 111, 112, and 113 may be integrated circuits (ICs) in which hundreds to millions of devices are integrated in one chip, respectively. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like may be used as a base material constituting each body. Various circuits may be formed on each body. Each of the connection pads 111P, 112P, 113P of the semiconductor chips 111, 112, 113 is for electrically connecting each semiconductor chip 111, 112, 113 with other components, and aluminum ( Al) can be used without particular limitation. A passivation film exposing the connection pads 111P, 112P, and 113P may be formed on each body, and the passivation film may be an oxide film or a nitride film, or may be a double layer of the oxide film and the nitride film. An insulating film or the like may be further disposed at other necessary positions. If necessary, a redistribution layer may be further formed on the active surfaces of the semiconductor chips 111, 112, and 113, and bumps 111B, 112B, 113B, and the like are connected to the connection pads 111P, 112P, 113P. You may have The bumps 111B, 112B, and 113B may be made of metal or solder. The semiconductor chips 111, 112, and 113 may be connected to the exposed pad layer 122c on the top of the connection structure 120 through the connection pads 111P, 112P, 113 and / or bumps 111B, 112B, 113B. In addition, connection members 115 such as solder and micro bumps may be used for connection. Each of the semiconductor chips 111, 112, and 113 may be fixed on the connection structure 120 with an underfill resin 170.

The connection structure 120 redistributes the connection pads 111P, 112P, and 113P of each of the semiconductor chips 111, 112, and 113. Through the connection structure 120, connection pads 111P, 112P, 113P of each of dozens of hundreds of semiconductor chips 111, 112, and 113 having various functions may be redistributed, and through the electrical connection metal 150 Depending on the function, it may be physically and / or electrically connected to the outside. The connection structure 120 electrically penetrates the insulating layer 121, the redistribution layer 122 formed on or within the insulating layer 121, and the redistribution layer 122 formed through different layers through the insulating layer 121. And a connecting via 123. The number of layers of the connection structure 120 may be greater than or less than that shown in the drawings. The connection structure 120 of this type may be used as an organic interposer in a 2.5D form.

The connection structure 120 is buried in the second insulating layer 121b and the second insulating layer 121b on the first insulating layer 121a in contact with the UBM layer 140 and the first redistribution layer in contact with the UBM via 143 The first redistribution layer 122a and the second redistribution layer 122b pass through at least a portion of the second redistribution layer 122b on the first redistribution layer 122a and the second insulating layer 121b. And a first via 123a that is electrically connected. The connection structure 120 may be composed of a multilayer of an insulating layer, a redistribution layer, and a via of this type. In addition, the connection structure 120 is the third insulating layer 121c in contact with the sealing material 160 and / or the underfill resin 170, and the third redistribution layer 122c disposed on the third insulating layer 121c. It includes.

As the material of the insulating layer 121, an insulating material may be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build-up Film) may be used. Alternatively, a photosensitive insulating material such as PID (Photo Imeagable Dielectric) resin may be used. That is, the insulating layers 121 may be photosensitive insulating layers, respectively. When the insulating layer 121 has a photosensitive property, the insulating layer 121 may be formed thinner, and the fine pitch of the via 123 may be more easily achieved. When the insulating layer 121 is a multilayer, these materials may be identical to each other, or may be different from each other as necessary. When the insulating layers 121 are multi-layered, they may be integrated according to a process, and thus the boundaries may be unclear by themselves.

The redistribution layer 122 may substantially serve to redistribute the connection pads 111P, 112P, and 113P, and may include copper (Cu), aluminum (Al), silver (Ag), and tin (Sn). ), Conductive materials such as gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layer 122 may perform various functions according to the design design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, and a signal (Signal: S) pattern may be included. Here, the signal S pattern includes various signals except for the ground (GND) pattern and the power (PWR) pattern, for example, a data signal. In addition, via pads, connection terminal pads, and the like may be included. A surface treatment layer P may be formed on the surface of the third redistribution layer 122c, which serves as a pad for mounting the semiconductor chips 111, 112, and 113 among the redistribution layers 122. The surface treatment layer P is not particularly limited as long as it is known in the art, for example, electrolytic gold plating, electroless gold plating, OSP or electroless tin plating, electroless silver plating, electroless nickel plating / replacement gold plating, It may be formed by DIG plating, HASL, etc., but is not limited thereto.

The via 123 electrically connects the redistribution layer 122 formed on different layers, and the like, thereby forming an electrical path in the package 100A. The forming material of the via 123 includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Conductive materials, such as these alloys, can be used. The via 123 may be completely filled with a conductive material, but is not limited thereto. The cross-sectional shape of the via 123 may be an approximately inverted trapezoidal shape based on the drawing.

The UBM layer 140 improves connection reliability of the electrical connection metal 150, and as a result, improves board-level reliability of the package 100A. The UBM layer 140 is disposed on the lower surface of the first insulating layer 121a at the lower portion of the connection structure 120 and includes UBM pads 142 and first insulation including first and second layers 142a and 142b. UBM vias 143 buried in the layer 121a to electrically connect the redistribution layer 122 of the connection structure 120 and the UBM pad 142, and the surface treatment layer 145 on the lower surface of the UBM pad 142 It includes. The UBM layer 140 may be made of copper (Cu), for example.

In the UBM pad 142, the first layer 142a has a width narrower than the width of the second layer 142b, and the thickness T2 of the first layer 142a is the thickness T1 of the second layer 142b. It may be larger, but is not limited thereto. The UBM pad 142 includes a plated seed layer 142S that is used as a seed layer when forming the UBM pad 142, and the plated seed layer 142S includes lower surfaces of the first and second layers 142a, 142b, and It may have a shape extending along the side of the first layer 142a. Since the remaining regions of the plating seed layer 142S and the upper UBM pad 142 are formed through different processes, a boundary between them may be identified.

The surface treatment layer 145 is disposed between the first surface treatment layer 145a and the first plating layer 145a and the UBM pad 142 disposed under the first layer 142a of the UBM pad 142. A second plating layer 145b may be included. However, the number of layers constituting the surface treatment layer 145 is not limited thereto. The material for forming the surface treatment layer 145 includes copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti) Alternatively, conductive materials such as alloys of these may be used.

The electrical connection metal 150 is disposed on the lower surface of the connection structure 120 so as to cover the entire surface of the lower surface and side surfaces of the UBM pad 142 and the lower surface of the surface treatment layer 145, so that the semiconductor package 100A is external Connect physically and / or electrically. For example, the semiconductor package 100A may be mounted on the main board of the electronic device through the electrical connection metal 150. Therefore, the electrical connection metal 150 may be larger in size and diameter than the connection member 115. In particular, the electrical connection metal 150 may cover the side surfaces of the first layer 142a of the UBM pad 142 and the bottom and side surfaces of the second layer 142b. The electrical connection metal 150 may be formed of a conductive material, for example, solder, but this is only an example and the material is not particularly limited thereto. The electrical connection metal 150 may be a land, a ball, or a pin. The electrical connection metal 150 may be formed of multiple layers or single layers. When formed in a multi-layer, it may include a copper pillar and a solder, and when formed in a single layer, it may include a tin-silver solder or copper, but this is only an example and is not limited thereto. .

The number, spacing, arrangement type, etc. of the electrical connection metal 150 are not particularly limited, and can be sufficiently modified according to design matters to a person skilled in the art. For example, the number of the electrical connection metals 150 may be several tens to thousands, depending on the number of the connection pads 111P, 112P, and 113P, and may have more or less numbers. Some of the electrical connection metal 150 may be disposed in the fan-out area. The fan-out area means an area outside the area where the semiconductor chips 111, 112, and 113 are disposed. That is, the semiconductor package 100A according to an example may be a fan-out semiconductor package. The fan-out package is more reliable than the fan-in package, and multiple I / O terminals can be implemented, and 3D interconnection is easy. In addition, compared to BGA (Ball Grid Array) package, LGA (Land Grid Array) package, the thickness of the package can be manufactured thinner, and the price is excellent.

The encapsulant 160 may protect the semiconductor chips 111, 112, and 113. The encapsulation form is not particularly limited, and may be any form that encloses at least a portion of the semiconductor chips 111, 112, and 113. The material of the encapsulant 160 is not particularly limited. For example, an insulating material may be used, wherein the insulating material is a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build- up Film). However, the present invention is not limited thereto, and prepreg including glass fiber may also be used. Alternatively, a known EMC (Epoxy Molding Compound) may be used.

The underfill resin 170 may fix the semiconductor chips 111, 112, and 113 on the connection structure 120. For the underfill resin 170, a known material including epoxy or the like can be applied. If necessary, the underfill resin 170 may be omitted. On the other hand, although not shown in the drawings, if necessary, passive components may be packaged by being arranged side by side with the semiconductor chips 111, 112, and 113 on the connection structure 120.

7A and 7B are enlarged views schematically showing another example of a semiconductor package including an organic interposer. 7A and 7B show areas corresponding to the enlarged view of FIG. 6.

Referring to FIG. 7A, at the bottom of the connection structure 120, the first insulating layer 121a may cover at least a portion of the side surface of the second layer 142b of the UBM pad 142. That is, at least a portion of the second layer 142b of the UBM pad 142 may have a shape embedded in the first insulating layer 121a of the connection structure 120. According to embodiments, the second layer 142b of the UBM pad 142 may be entirely embedded in the first insulating layer 121a of the connection structure 120. Also, the electrical connection metal 150 may expose some of the side surfaces of the UBM pad 142, for example, the side surfaces of the second layer 142b. The electrical connection metal 150 may cover the side surface of the first layer 142a of the UBM pad 142, the lower surface of the second layer 142b, and the lower surface of the surface treatment layer 145. Descriptions of other structures are omitted as they are substantially the same as those described in the semiconductor package 100A according to the above-described example.

Referring to FIG. 7B, at the bottom of the connection structure 120, as in FIG. 7A, the first insulating layer 121a may cover at least a portion of the side surface of the second layer 142b of the UBM pad 142. . In addition, the electrical connection metal 150 may expose some of the side surfaces of the UBM pad 142, for example, the entire side surface of the second layer 142b and a portion of the side surface of the first region 142a. However, according to embodiments, the electrical connection metal 150 may not expose the side surface of the first region 142a. Accordingly, the electrical connection metal 150 may cover at least a portion of the side surface of the first layer 142a of the UBM pad 142 and may cover the lower surface of the surface treatment layer 145. In particular, since the surface treatment layer 145 of the UBM layer 140 does not extend on the side of the UBM pad 142, the electrical connection metal 150 is also not wetted along the side of the UBM pad 142. The consumption amount of the electrical connection metal 150 can be minimized. In addition, it is possible to prevent a defect such as an electrical short circuit from occurring between adjacent electrical connection metals 150, and thus it is possible to implement a fine ball pitch structure. Descriptions of other structures are omitted as they are substantially the same as those described in the semiconductor package 100A according to the above-described example.

8A to 8E schematically show an example of a process for forming a semiconductor package including the organic interposer of FIG. 6.

8A, first, a carrier 210 is prepared. The carrier 210 may include a core layer 211 and metal layers 212 and 213 formed on the core layer 211. The core layer 211 may be, for example, a prepreg including an insulating resin, an inorganic filler, and glass fibers. The metal films 212 and 213 may include metals such as copper (Cu) and titanium (Ti). The metal films 212 and 213 may be surface-treated to facilitate separation. Alternatively, a release layer may be provided therebetween. The carrier 210 may be a conventional detach core. Next, the lower insulating layer 222 is formed on the carrier 210, and the lower plating seed layer 232 is patterned on the lower insulating layer 222 to form it. The lower insulating layer 222 may be formed using a photosensitive insulating material such as PID (Photo Imeagable Dielectric) resin. The lower plating seed layer 232 may be formed by a sputtering process, a process of forming a mask layer through an exposure and development process, and an etching process, for example, a copper (Cu) layer. Next, the surface treatment layer 145 including the first and second plating layers 145a and 145b is formed using the lower plating seed layer 232 as a plating seed layer. The surface treatment layer 145 may be formed by an electrolytic plating process. In this case, defects such as smearing around the pattern, which may occur when forming by electroless plating, can be prevented. Next, an upper insulating layer 224 exposing the surface treatment layer 145 is formed on the lower insulating layer 222, and a plated seed layer 142S is formed. The lower insulating layer 224 is formed by patterning the PID resin, and the plating seed layer 142S is formed through a sputtering process.

Referring to FIG. 8B, a photoresist layer 240 is formed on a portion of the lower insulating layer 224 and the plating seed layer 142S, and the UBM pad 142 is formed. The UBM pad 142 may be formed on the surface treatment layer 145 and may be formed on the plated seed layer 142S. The UBM pad 142 is formed to have a T-shape due to the step difference between the upper insulating layer 224 and the photoresist layer 240. Next, the photoresist layer 240 is removed. Next, the first insulating layer 121a is formed, and the first insulating layer 121a is patterned to form the UBM via 143 and the first redistribution layer 122a connected to the UBM pad 142. The UBM via 143 and the first redistribution layer 122a may be formed by forming a pattern using a dry film or the like, and then filling it with a plating method. As a result, the UBM layer 140 is formed.

Referring to FIG. 8C, structures other than the first redistribution layer 122a are further formed on the first insulating layer 121a and the UBM layer 140 to form the connection structure 120, and the connection structure 120 ), A surface treatment layer P is formed on the third redistribution layer 122c. The connection structure 120 and the UBM layer 140 may be continuously formed in the same line. The insulating layer 121 may be formed by laminating or applying PID or the like. The redistribution layer 122 and the via 123 may be formed by forming a pattern using a dry film or the like, and then filling it with a plating method. As a plating method, subtractive, additive, SAP (Semi-Additive Process), MSAP (Modified Semi-Additive Process), etc. may be used, but are not limited thereto. Next, if necessary, a quad route inspection, an electrical inspection of the redistribution layer 122, and the like are performed. Next, the semiconductor chips 111, 112, and 113 are mounted on the upper portion of the connection structure 120. A connection member 115 such as a micro bump may be used for mounting, and then the semiconductor chips 111, 112, and 113 may be fixed with the underfill resin 170.

Referring to FIG. 8D, a sealing material 160 for sealing the semiconductor chips 111, 112, and 113 is formed, and the carrier 210 is separated from the connection structure 120 and the semiconductor chips 111, 112, 113. . The encapsulant 160 may be formed by laminating a film form or applying a liquid form to a coating and curing method. Separation of the carrier 210 may be performed by separation of the release layer 212. Accordingly, the lowermost insulating layer 222 is exposed. Next, a descum etching process is performed to remove a portion of the first insulating layer 121a of the lower insulating layer 222, the upper insulating layer 224, and the connection structure 120. Accordingly, the UBM pad 142 is exposed to the lower portion of the connection structure 120. On the other hand, if necessary, the sealing material 160 may be ground. The upper surfaces of the semiconductor chips 111, 112, and 113 may be located at the same level by grinding. That is, the thicknesses of the semiconductor chips 111, 112, and 113 may be substantially the same. However, the grinding process may be performed or omitted after the formation of the electrical connection metal 150.

Referring to FIG. 8E, the attachment and reflow process of the electrical connection metal 150 is performed. The semiconductor package 100A according to the above-described example may be manufactured through a series of processes.

In the present disclosure, the lower side, the lower side, the lower side, etc. were used to mean the direction toward the mounting surface of the fan-out semiconductor package based on the cross section of the drawing for convenience, and the upper side, upper side, and upper side were used in opposite directions. However, this defines the direction for convenience of explanation, and it goes without saying that the scope of the claims is not particularly limited by the description of the direction.

The term "connected" in the present disclosure is a concept that includes not only directly connected but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept including both physically connected and non-connected cases. In addition, expressions such as first and second are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be referred to as a second component, and similarly, the second component may be referred to as a first component without departing from the scope of rights.

The expression “an example” used in the present disclosure does not imply the same embodiment, but is provided to explain different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, although the matter described in a particular example is not described in another example, it may be understood as a description related to another example, unless there is a description contrary to or contradicting the matter in another example.

The terms used in the present disclosure are only used to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless the context clearly indicates otherwise.

1000: electronic device 1010: main board
1020: Chip-related parts 1030: Network-related parts
1040: other parts 1050: camera
1060: Antenna 1070: Display
1080: Battery 1090: Signal line
1100: smartphone 1101: smartphone body
1110: Smartphone mainboard 1111: Mainboard insulation layer
1112: motherboard wiring 1120: parts
1130: smartphone camera 100A: semiconductor package
111, 112, 113: semiconductor chip 111P, 112P, 113P: connection pad
111B, 112B, 113B: bump 115: connecting member
120: connection structure 121, 121a, 121b, 121c: insulating layer
122, 122a, 122b, 122c: redistribution layer 123, 123a: via
140: UBM layer 142: UBM pad
143: UBM via 145: surface treatment layer
150: electrical connection metal 160: sealing material
170: underfill resin

Claims (10)

A semiconductor chip having an active surface on which a connection pad is disposed;
A connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer and an insulation layer electrically connected to the connection pad; And
An UBM (under bump metallurgy) layer disposed on the connection structure and electrically connected to the redistribution layer of the connection structure; And
It includes an electrical connection metal disposed on the UBM layer,
The UBM layer is disposed on an insulating layer of the connection structure, a UBM pad having a T-shape, and disposed on a lower surface of the UBM pad to expose a side surface of the UBM pad, and a surface treatment layer including at least one plating layer , And UBM vias penetrating at least a portion of the insulating layer of the connection structure and electrically connecting the redistribution layer of the connection structure and the UBM pad.
A semiconductor package comprising an organic interposer.
According to claim 1,
The UBM pad includes a first layer under the insulating layer of the connection structure and a second layer disposed between the first layer and the UBM via and having a width greater than the width of the first layer,
A semiconductor package comprising an organic interposer.
According to claim 2,
The UBM pad further includes a plating seed layer disposed along the bottom surface of the first and second layers and side surfaces of the first layer,
A semiconductor package comprising an organic interposer.
According to claim 2,
The first layer of the UBM pad has a thicker thickness than the second layer,
A semiconductor package comprising an organic interposer.
According to claim 1,
The electrical connection metal covers the entire bottom and side surfaces of the UBM pad,
A semiconductor package comprising an organic interposer.
According to claim 1,
The electrical connection metal covers a part of the side surface of the UBM pad and a lower surface of the surface treatment layer,
A semiconductor package comprising an organic interposer.
According to claim 1,
The UBM pad is partially embedded in the insulating layer of the connection structure,
A semiconductor package comprising an organic interposer.
According to claim 1,
The surface treatment layer includes a first plating layer containing gold (Au), and a second plating layer including nickel (Ni) disposed between the UBM pad and the first plating layer,
A semiconductor package comprising an organic interposer.
According to claim 1,
The semiconductor chip includes a processor chip and a memory chip,
The processor chip and the memory chip are electrically connected through the connection structure,
A semiconductor package comprising an organic interposer.
A semiconductor chip having an active surface on which a connection pad is disposed;
A connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer and an insulation layer electrically connected to the connection pad; And
A UBM layer disposed on the connection structure and electrically connected to the redistribution layer of the connection structure; And
It includes an electrical connection metal disposed on the UBM layer,
The UBM layer is disposed on the insulating layer of the connection structure, a UBM pad having a T-shape, and disposed on a lower surface of the UBM pad to expose a side surface of the UBM pad, and a surface treatment layer including at least one plating layer , And UBM vias penetrating at least a portion of the insulating layer of the connection structure and electrically connecting the redistribution layer of the connection structure and the UBM pad,
The surface treatment layer includes a different material from the UBM pad,
A semiconductor package comprising an organic interposer.

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