KR20190088734A - Memory interface and memory controller having the same, and memory system having the same - Google Patents

Abstract

The present invention relates to a memory interface, a memory controller including the same, and a memory system including the same. The memory interface comprises: a command queue control unit which determines the order of execution of normal commands and a suspend command; a command time control unit which receives the normal commands from the command queue control unit, provides additional operating time to the normal commands, respectively and outputs information on commands and time; a command time table which matches the command and time information with each of the normal commands, stores the same, and outputs a completion signal; and an input/output interface which receives the normal commands or the suspend command from the command queue control unit, and transmits the normal commands or the suspend command to a memory device through a channel. Therefore, the memory interface can prevent continuous delays of execution of normal commands due to the suspend command.

Description

[0001] The present invention relates to a memory interface, a memory controller including the same, and a memory system including the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface, a memory controller including the memory interface, and a memory system including the memory interface. More particularly, the present invention relates to a memory interface for managing a normal command and a suspend command, Controller and a memory system including the same.

The memory system may include a memory device and a memory controller.

The memory device may store data or output the stored data. For example, the memory device may consist of a volatile memory device in which the stored data is destroyed when the power supply is interrupted, or a nonvolatile memory device in which the stored data is retained even if the power supply is interrupted.

The memory controller can control data communication between the host and the memory device.

A host can use an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI And can communicate with the memory device. The interface protocols between the host and the memory system are not limited to the above examples and various interfaces such as USB (Universal Serial Bus), MMC (Multi-Media Card), ESDI (Enhanced Small Disk Interface) May be included.

The embodiment of the present invention sets an operation time to a normal command so that if the suspend command is to be executed later, A memory controller including the memory interface, and a memory system including the memory controller.

A memory interface according to an embodiment of the present invention includes a command queue control unit for determining execution orders of normal commands and suspend commands; A command time control unit receiving the normal commands from the command queue control unit and outputting commands and time information by giving the normal commands an additional operation time; A command time table for matching and storing the command and time information with the normal commands and outputting a termination signal; And an input / output interface for receiving the normal commands or the suspend command from the command queue control unit and transmitting the normal commands or the suspend command to the memory device via a channel.

A memory controller according to an embodiment of the present invention includes a central processing unit for generating a normal command or a suspend command in response to a request from a host; And a memory interface for transferring the normal command or the suspend command to a memory device, wherein the memory interface provides the normal command to the memory device after giving the normal command an additional operating time when the normal command is received And when the suspend command is received, further executes the normal command for the additional operation time, and then transmits the suspend command to the memory device.

A memory system according to an embodiment of the present invention includes: a memory device in which data is stored; And a memory controller for generating a normal command or a suspend command in accordance with a request from the host and transmitting the normal command or the suspend command to the memory device through a channel, wherein, when the normal command is generated, After sending the normal command to the memory device after giving an additional operation time to the normal command and, when the suspend command is generated, transferring the suspend command to the memory device after delaying the suspend command by the additional operation time .

When the suspend command is to be executed, the present invention can prevent the execution of the normal command from being delayed by the suspend command by executing the suspend command after additionally executing the already executed normal command for a predetermined operation time .

1 is a diagram for explaining a memory system according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the memory controller of FIG. 1 in detail.
3 is a diagram for explaining a memory interface according to an embodiment of the present invention.
FIG. 4 is a diagram for explaining the command queue control unit of FIG. 3 in detail.
FIG. 5 is a diagram for specifically explaining the command time control unit of FIG. 3; FIG.
Figs. 6 and 7 are diagrams for explaining embodiments of the command time table of Fig.
8 is a diagram for explaining a method of executing a normal command according to an embodiment of the present invention.
9 is a diagram for explaining a method of executing a suspend command according to an embodiment of the present invention.
FIG. 10 is a diagram for explaining another embodiment of a memory system including the memory controller and the memory device shown in FIG. 2. FIG.
11 is a diagram for explaining another embodiment of a memory system including the memory controller and the memory device shown in Fig.
12 is a diagram for explaining another embodiment of the memory system including the memory controller and the memory device shown in FIG.
13 is a diagram for explaining another embodiment of the memory system including the memory controller and the memory device shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a diagram for explaining a memory system according to an embodiment of the present invention.

1, a memory system 1000 includes a memory device 1100 for storing data, a memory controller 1100 for controlling the memory device 1100 under the control of a host 2000, A memory controller 1200, and the like.

The host 2000 may be connected to the memory 2000 using an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA) And can communicate with the system 1000. In addition, the interface protocols between the host 2000 and the memory system 1000 are not limited to the above-described examples. For example, USB (Universal Serial Bus), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI) Drive Electronics) may be further included.

The memory controller 1200 controls the overall operation of the memory system 1000 and can control the exchange of data between the host 2000 and the memory device 1100. For example, the memory controller 1200 may convert received information so that a command CMD, an address, and data may be communicated between the host 2000 and the memory device 1100, The converted information can be stored and output. For example, the memory controller 1200 may control the memory device 1100 to perform a program, read, or erase operation. According to an embodiment, the memory device 1100 may be a DDR SDRAM, a Low Power Double Data Rate (SDRAM) SDRAM, a GDDR (Graphics Double Data Rate) SDRAM, a LPDDR (Low Power DDR) A Rambus Dynamic Random Access Memory (RDRAM) or a FLASH memory.

The memory controller 1200 can sequentially execute the normally executed normal command according to the command queue. In addition, the memory controller 1200 may use the suspend command to control the memory device 1100 to perform certain operations prior to the normal command. The memory controller 1200 according to the present embodiment can give an additional operation time to each of the normal commands and control the command so that the operation corresponding to the normal commands is further performed during the additional operation time when executing the suspend command.

FIG. 2 is a diagram for explaining the memory controller of FIG. 1 in detail.

2, the memory controller 1200 includes a buffer memory 1210, a central processing unit (CPU) 1220, and a buffer memory 1210 to control communication between the host 2000 and the memory device 1100. [ An internal memory 1230, a host interface 1240, an error correction circuit (ECC) 1250, and a memory interface 1260. The internal memory 1230 may be a memory, The buffer memory 1210, the central processing unit 1220, the internal memory 1230, the host interface 1240, the error correction circuit 1250 and the memory interface 1260 can communicate with each other via a bus 1270 And the memory interface 1260 may communicate with the memory device 1100 via a channel 1280.

The buffer memory 1210 may temporarily store data transmitted and received between the memory controller 1200 and the memory device 1100. For example, during program operation, the data to be programmed may be temporarily stored in the buffer memory 1210 before being transmitted to the memory device 1100, where the stored data is stored in the memory device 1100, Can be reused. Further, at the time of the read operation, the data read from the memory device 1100 can be temporarily stored in the buffer memory 1210. For example, when the read data of the predetermined capacity is temporarily stored in the buffer memory 1210 during the read operation, the read data may be output to the host 2000 through the host interface 1240.

The central processing unit 1220 may perform various operations for controlling the memory device 1100 or may perform firmware. The central processing unit 1220 also generates a normal command in response to normal requests received from the host 2000 or generates a suspend command in response to a suspend request, Can be generated.

The internal memory 1230 may be used as a storage device capable of storing various system information necessary for the operation of the memory controller 1200. For example, the internal memory 1230 may be implemented as an SRAM. The internal memory 1230 may include a table in which various system information necessary for operation of the memory system 1000 is stored.

The host interface 1240 may be configured to communicate with an external host 2000 connected to the memory system 1000 under the control of the central processing unit 1220. [ For example, the host interface 1240 may receive a write command, data, and a logical address corresponding to the write command from the host 2000. [ The host interface 1240 can also receive a read command and a logical address corresponding to the read command from the host 2000. [

The error correction circuit 1250 can detect or correct an error included in the data read from the memory device 1100. [ For example, the error correction circuit 1250 may perform an error correction encoding (ECC encoding) operation based on data to be written to the memory device 1100 via the memory interface 1260. The data on which the error correction encoding operation has been performed can be transferred to the memory device 1100 through the memory interface 1260. [ The error correction circuit 1250 may also perform error correction decoding (ECC decoding) on data received from the memory device 1100 via the memory interface 1260. The error correction circuit 1250 can perform an error correction operation based on a Bose-Choduria-Okenzem code (BCH code) or a low density parity check code (LDPC code).

The memory interface 1260 may be configured to communicate with the memory device 1100 under the control of the central processing unit 1220. In this embodiment, the memory interface 1260 may queue commands, e.g., normal commands, received from the central processing unit 1220. In addition, the memory interface 1260 may set an additional operation time for each of the normal commands. The additional operation time may be set to ensure the execution time of the normal command for a predetermined time even if the suspend command is received.

3 is a diagram for explaining a memory interface according to an embodiment of the present invention.

3, the memory interface 1260 includes a CMD Queue Controller 61, a CMD Time Controller 62, a CMD Time Table 63, and an I / O Interface 64).

The command queue control unit 61 can receive a normal command or a suspend command via the bus 1270. [ The command queue control unit 61 sequentially receives a plurality of normal commands and queues the normal commands according to the execution order. The command queue control unit 61 can sequentially output the queued normal commands to the command time control unit 62. [ Further, when the suspend command is received, the command queue control section 61 can immediately output the suspend command to the command time table 63 irrespective of the queuing order of the normal commands.

The command time control section 62 can give an additional operation time to each of the normal commands received from the command queue control section 61 and transmit information including the normal commands and the additional operation time to the command time table 63 . Hereinafter, the information will be referred to as 'command and time information'.

The command time table 63 can receive command and time information from the command time control unit 62 and store the additional operation time matched to the normal command, respectively. The command time table 63 may store the command and time information for the normal command and then output the end signal to the command queue control unit 61. [ The command time table 63 can also output a termination signal to the command queue control unit 61 after an additional operation time has elapsed according to the command and time information stored in the table upon receiving the suspend command from the command queue control unit 61 have.

When the end signal is input to the command queue control unit 61, the command queue control unit 61 can transmit the normal command or the suspend command corresponding to the end signal to the input / output interface 64. [ For example, the command queue control section 61 can sequentially output the normal command to the input / output interface 64 or output the suspend command to the input / output interface 64 whenever the end signal is received.

The additional operation time stored in the command time table 63 and the corresponding normal command may be deleted when the operation on the normal command in the memory device 1100 is completed.

Upon receiving the normal command or the suspend command from the command queue control unit 61, the input / output interface 64 can output a normal command or a suspend command via the channel 1280. [

The memory device receiving the normal command or the suspend command through the channel 1280 can execute the corresponding command.

The configuration of the memory interface 1260 will be described in more detail as follows.

FIG. 4 is a diagram for explaining the command queue control unit of FIG. 3 in detail.

Referring to FIG. 4, the command queue control unit 61 may manage a queue of normal commands (1N_CMD through aN_CMD; a is a positive integer) received via a bus (1270 in FIG. 3). For example, the first through the a-th normal commands 1N_CMD through aN_CMD received via the bus 1270 may be sequentially output in order (T41).

When the first to the a-th normal commands 1N_CMD to aN_CMD are sequentially output, when the suspend command S_CMD having a high degree of importance is received, the command queue control unit 61 outputs the suspend command (S_CMD) can be preferentially output (T42). For example, the normal command received through the bus 1270 is output to the command time control section (62 of FIG. 3). When the end signal is received, the same northern command output to the command time control section 62 is input / 3, < / RTI > 64). When the suspend command S_CMD is received via the bus 1270, the command queue control unit 61 outputs the suspend command S_CMD to the command time table (63 in FIG. 3) instead of the command time control unit 62 . The command queue control unit 61 can output the suspend command S_CMD to the input / output interface 64 when the end signal is received after the suspend command S_CMD is output to the command time table 63. [

FIG. 5 is a diagram for specifically explaining the command time control unit of FIG. 3; FIG.

5, when the first to the a-th normal commands 1N_CMD to aN_CMD are received from the command queue control unit 61 (FIG. 3), the command time control unit 62 outputs the first to the a-th normal commands 1N_CMD (1Min_T to aMin_T) can be given to each of the sub-fields a1 to aN_CMD. The additional operation time (1Min_T to aMin_T) means a time at which the currently executed normal command is additionally executed when the suspend command is received.

For example, the command time control unit 62 gives the first to the a-th additional operation times (1Min_T to aMin_T) to the first to the a-th normal commands 1N_CMD to aN_CMD respectively, and the additional operation time 1Min_T to aMin_T (1N_CMD + 1Min_T to aN_CMD + aMin_CMD) to which the command and time information (1N_CMD + 1Min_T to aN_CMD + aMin_CMD) That is, the additional operation time given to each of the normal commands 1N_CMD to aN_CMD is set such that when the suspend command S_CMD is received when the normal command is being executed in the memory device, the executing normal command is not immediately stopped, Can be used to further execute.

The additional operation time (1Min_T to aMin_T) may be set differently according to the memory system 1000. For example, the additional operation time (1Min_T to aMin_T) may be set to the same time in each of the first to the a-th normal commands (1N_CMD to aN_CMD), or may be set to different times. For example, the additional operation time (1Min_T to aMin_T) may be set according to the characteristics of the first to the a-th normal commands (1N_CMD to aN_CMD), respectively. For example, the additional operation time (1Min_T to aMin_T) may be set differently depending on the importance of the first to the a-th normal commands (1N_CMD to aN_CMD). For example, the additional operation time (1Min_T to aMin_T) may be set to some normal commands according to the first to the a-th normal commands (1N_CMD to aN_CMD) and not to the rest of the normal commands. The characteristics or importance of the above-mentioned first to the a-th normal commands 1N_CMD to aN_CMD may vary depending on the memory system 1000.

Figs. 6 and 7 are diagrams for explaining embodiments of the command time table 63 of Fig. FIG. 6 is a diagram for explaining a command time table 63a according to an embodiment, and FIG. 7 is a diagram for explaining a command time table 63b according to another embodiment.

Referring to FIG. 6, the command time table 63a may include an information table 31a and an end signal output unit (E_SG Generator) 32.

Data in which the command (CMD) information and time (Time) information are matched with each other can be stored in the information table 31a. For example, in the information table 31a, data in which the first normal command 1N_CMD and the first additional operation time 1Min_T match each other can be stored, and the second normal command 2N_CMD and the second additional operation time (2Min_T) are matched with each other, and data in which the a-th normal command (aN_CMD) and the a-th additional operation time (aMin_T) match each other can be stored.

The end signal output unit 32 may output an end signal indicating that information is stored in the table when the information input to the command time table 63a is stored in the information table 31a.

Referring to FIG. 7, the command time table 63b may include an information table 31b and an end signal output unit (E_SG Generator) 32. The command time table 63b according to the embodiment of FIG. 7 is different from the information stored in the information table 31a of FIG. 6, and the remaining configuration is similar to the command time table 63a of FIG.

Data in which die DIE information, command CMD information, and time information match each other may be stored in the command time table 63b of FIG. 2) may be connected to the memory interface (1260 of FIG. 2) if, for example, the memory device (1200 of FIG. 2) And a plurality of memory devices 1100 may be connected to each of the channels 1280. [ If each memory device 1100 is a die DIE, then the command CMD running on each die DIE may vary.

Therefore, in the memory system 1000 having such a structure, the information of die DIE can be stored in the command time table 63b. For example, in the information table 31b, data in which the first die 1DIE, the first normal command 1N_CMD, and the first additional operation time 1Min_T match each other can be stored. That is, when the command CMD being executed in the first die 1DIE is the first normal command 1N_CMD, the first normal operation 1N_CMD may be given a first additional operation time 1Min_T and stored. In this case, when the suspend command for the first die 1DIE is received, the first normal command 1N_CMD does not immediately terminate, but can be terminated after being further executed for the first additional operation time 1Min_T. In this manner, when the command CMD being executed in the a-th die aDIE is the a-th normal command aN_CMD, the a-th additional command aN_CMD can be given and added to the a-th additional operation time aN_CMD .

The end signal output unit 32 may output an end signal for informing that information is stored in the table when the information input to the command time table 63b is stored in the information table 31b.

8 is a diagram for explaining a method of executing a normal command according to an embodiment of the present invention.

8, when the first normal command 1N_CMD is input to the memory interface 1260 via the bus 1270, the command queue control unit 61 can temporarily store the first normal command 1N_CMD therein have. Then, the command queue control section 61 can transmit the first normal command 1N_CMD to the command time control section 62. [

The command time control section 62 gives the first additional operation time 1Min_T to the first normal command 1N_CMD and outputs the first command and the time information 1N_CMD + 1Min_T for the first normal command 1N_CMD .

The first command and the time information (1N_CMD + 1Min_T) output from the command time control unit 62 can be input to the command time table 63. [ When the first command and the time information 1N_CMD + 1Min_T are stored in the command time table 63, the command time table 63 can output the end signal E_SG to the command queue control unit 61. [

The command queue control unit 61 can transmit the temporarily stored first normal command aN_CMD to the input / output interface 64 when the end signal E_SG is received.

The input / output interface 64 can transmit the first normal command aN_CMD received from the command queue control unit 61 to the memory device (1100 in Fig. 2) via the channel 1280. [

The memory device 1100 may execute the first normal command 1N_CMD when the first normal command 1N_CMD is received via the channel 1280. [

If the suspend command occurs while the memory device 1100 executes the first normal command 1N_CMD, the surge-send command can be executed in the following order.

9 is a diagram for explaining a method of executing a suspend command according to an embodiment of the present invention.

9, when the suspend command S_CMD is input to the memory interface 1260 via the bus 1270, the command queue control unit 61 may temporarily store the suspend command S_CMD therein. Subsequently, the command queue control unit 61 can transmit the suspend command S_CMD to the command time table 63. [

When the suspend command S_CMD is input to the command time table 63, the command time table 63 is a table in which the memory device 1100 searches for the currently executed normal command, determines whether there is an additional operation time matched to the found normal command information Can be determined.

If there is no information on the additional operation time, the command time table 63 can immediately output the end signal E_SG. If there is information on the additional operation time, the command time table 63 can output the end signal E_SG after a delay time corresponding to the additional operation time. For example, when the memory apparatus 1100 is executing the first normal command 1N_CMD and the first additional operation time 1Min_T is matched with the first normal command 1N_CMD, It is possible to output the end signal E_SG after one additional operation time (1Min_T) has elapsed.

Accordingly, even if the suspend command S_CMD occurs, the memory device 1100 can perform the corresponding operation for the first additional operation time 1Min_T without immediately terminating the operation of the currently executed first normal command 1N_CMD have.

When the command time table 63 outputs the end signal E_SG, the output end signal E_SG can be input to the command queue control unit 61. [

The command queue control unit 61 can transmit the temporarily stored suspend command S_CMD to the input / output interface 64 when the end signal E_SG is input.

Output interface 64 can transmit the suspend command S_CMD received from the command queue control unit 61 to the memory device 1100 through the channel 1280. [

According to the embodiment described above, since the additional time is given to the normal command, even if the suspend command is generated, the minimum time in which the normal command can be additionally executed is guaranteed, thereby preventing the normal command from being delayed infinitely.

FIG. 10 is a diagram for explaining another embodiment of a memory system including the memory controller and the memory device shown in FIG. 2. FIG.

10, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device . The memory system 30000 can include a memory device 1100 and a memory controller 1200 that can control the operation of the memory device 1100. The memory controller 1200 may control the data access operation of the memory device 1100 such as a program operation, an erase operation, or a read operation according to the control of the processor 3100 .

The data programmed into the memory device 1100 may be output through a display (Display) 3200 under the control of the memory controller 1200.

The radio transceiver 3300 can transmit and receive radio signals through the antenna ANT. For example, the wireless transceiver 3300 may change the wireless signal received via the antenna ANT to a signal that can be processed by the processor 3100. Thus, the processor 3100 can process the signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 1200 or display 3200. Memory controller 1200 may send a signal processed by processor 3100 to memory device 1100. In addition, the wireless transceiver 3300 may convert the signal output from the processor 3100 into a wireless signal, and output the modified wireless signal to an external device through the antenna ANT. An input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100 and includes a touch pad, A pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 is connected to the display 3200 so that data output from the memory controller 1200, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output via the display 3200. [ Can be controlled.

According to an embodiment, a memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as part of the processor 3100 and may also be implemented as a separate chip from the processor 3100.

11 is a diagram for explaining another embodiment of a memory system including the memory controller and the memory device shown in Fig.

11, the memory system 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant ), A portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 can include a memory device 1100 and a memory controller 1200 that can control the data processing operations of the memory device 1100.

A processor 4100 may output data stored in the memory device 1100 through a display 4300 according to data input through an input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200. [ The memory controller 1200 capable of controlling the operation of the memory device 1100 according to an embodiment may be implemented as part of the processor 4100 or in a separate chip from the processor 4100. [

12 is a diagram for explaining another embodiment of the memory system including the memory controller and the memory device shown in FIG.

Referring to Fig. 12, the memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with a digital camera.

The memory system 50000 includes a memory controller 1200 that is capable of controlling the data processing operations of the memory device 1100 and the memory device 1100, such as program operations, erase operations, or read operations.

The image sensor 5200 of the memory system 50000 can convert the optical image into digital signals and the converted digital signals can be transmitted to the processor 5100 or the memory controller 1200. Depending on the control of the processor 5100, the converted digital signals may be output via a display 5300 or stored in the memory device 1100 through a memory controller 1200. The data stored in the memory device 1100 may also be output via the display 5300 under the control of the processor 5100 or the memory controller 1200. [

The memory controller 1200 capable of controlling the operation of the memory device 1100 according to an embodiment may be implemented as a part of the processor 5100 or in a chip separate from the processor 5100. [

13 is a diagram for explaining another embodiment of the memory system including the memory controller and the memory device shown in Fig.

Referring to FIG. 13, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a memory controller 1200, and a card interface (Card Interface) 7100.

The memory controller 1200 may control the exchange of data between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be an SD (secure digital) card interface or a multi-media card (MMC) interface, but is not limited thereto.

The card interface 7100 can interface data exchange between the host 60000 and the memory controller 1200 according to the protocol of the host (HOST) 60000. According to the embodiment, the card interface 7100 can support USB (Universal Serial Bus) protocol and IC (InterChip) -USB protocol. Here, the card interface 7100 may mean hardware that can support the protocol used by the host 60000, software installed on the hardware, or a signal transmission method.

When the memory system 70000 is connected to the host interface 6200 of the host 60000 such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set- The interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of a microprocessor (μP) 6100.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

2000: Host 1000: Memory System
1100: memory device 1200: memory controller
1210: buffer memory 1220: central processing unit
1230: internal memory 1240: host interface
1250: error correction circuit 1260: memory interface
61: Command queue control unit 62: Command time control unit
63: Command time table 64: I / O interface

Claims (20)

A command queue control unit for determining an execution order of normal commands and suspend commands;
A command time control unit receiving the normal commands from the command queue control unit and outputting commands and time information by giving the normal commands an additional operation time;
A command time table for matching and storing the command and time information with the normal commands and outputting a termination signal; And
And an input / output interface for receiving the normal commands or the suspend command from the command queue control unit and transmitting the normal commands or the suspend command to a memory device via a channel.
The method according to claim 1,
The command queue control unit,
When the normal commands are received, the normal commands are temporarily stored,
Sequentially transmits the normal commands to the command time control unit,
And sequentially transmits the normal commands to the input / output interface in response to the termination signal.
The method according to claim 1,
The command queue control unit,
Sequentially outputs the normal commands to the command time control unit,
And sequentially transmits the normal commands to the input / output interface each time the termination signal is received.
The method according to claim 1,
Wherein the command queue control view comprises:
Wherein when the suspend command is received, the suspend command is preferentially output irrespective of an output order of the normal commands.
The method according to claim 1,
The command queue control unit,
And sequentially transmits the normal commands to the command time control unit when the normal commands are received,
And transmits the suspend command to the command time table when the suspend command is received.
The method according to claim 1,
The command time control unit,
And wherein the memory interface gives the additional operation time in accordance with the nature or importance of the normal commands.
The method according to claim 6,
The command time control unit,
All of the additional operation times are equally given to the normal commands,
The additional operation time is given to a part of the normal commands and the additional operation time is not given to the remaining normal commands.
8. The method of claim 7,
The command time control unit,
And does not give or give the additional operating time according to the nature and importance of the normal commands.
The method according to claim 1,
The command time table includes:
An information table in which the command and the time information in which the additional operation time is respectively matched are stored in the normal commands; And
And outputs the termination signal whenever the command and the time information are stored in the information table.
The method according to claim 1,
The command time table includes:
And when the suspend command is received, outputs the end signal after the additional operation time matched to the normal command.
A central processing unit for generating a normal command or a suspend command in response to a request from a host; And
And a memory interface for transferring the normal command or the suspend command to a memory device,
The memory interface comprising:
After the normal command is received, an additional operation time is given to the normal command, and then the normal command is transmitted to the memory device,
And when the suspend command is received, further executing the normal command for the additional operation time, and then sending the suspend command to the memory device.
12. The method of claim 11,
The memory interface comprising:
A command queue control unit for controlling an output order of the normal command or the suspend command;
A command time control unit for giving the additional operation time according to the normal command;
A command time table for storing information in which the normal command and the additional operation time are matched and for delaying the suspend command for the additional operation time when the suspend command is received; And
And an input / output interface for transmitting the normal command or the suspend command received from the command queue control unit to the memory device.
13. The method of claim 12,
The command queue control unit,
Wherein when the normal command is received, the normal command is temporarily stored, and then the normal command is transmitted to the command time control unit,
Temporarily stores the suspend command when the suspend command is received, and then transmits the suspend command to the command time table.
13. The method of claim 12,
The command time control unit,
And adds said additional operation time in accordance with the nature or importance of said normal command.
13. The method of claim 12,
The command time control unit,
Wherein said additional operation time is not given or given in accordance with the nature or importance of said normal command.
13. The method of claim 12,
The command time table includes:
An information table in which the command and the time information are stored in the normal command, respectively; And
And outputs the end signal each time the command and time information are stored in the information table.
13. The method of claim 12,
The command time table includes:
And when the suspend command is received, delays the suspend command for the additional operation time matched to the normal command, and outputs the termination signal after the additional operation time.
A memory device in which data is stored; And
And a memory controller for generating a normal command or a suspend command in accordance with a request from the host and transmitting the normal command or the suspend command to the memory device via a channel,
The memory controller includes:
Wherein when the normal command is generated, after giving an additional operation time to the normal command, the normal command is transmitted to the memory device,
And when the suspend command is generated, delays the suspend command by the additional operating time and then sends the suspend command to the memory device.
19. The method of claim 18,
The memory controller includes:
And adds the additional operation time according to the nature or importance of the normal command.
19. The method of claim 18,
The memory controller includes:
When the suspend command is generated while the normal command is being executed in the memory device,
Delaying the output of the suspend command so that the normal command is further executed during the additional operation time in the memory device,
And to send the suspend command to the memory device after the additional operating time.

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