KR20190056951A - Storage device performing peer-to-peer communication with external device without intervention of host - Google Patents

Abstract

The present invention provides a storage device including a field programmable gate array (FPGA) board and a storage controller. The FPGA board is connected to a first port of the storage device. A first interface circuit of the storage controller is connected to the FPGA board and a second interface circuit of the storage controller is connected to a second port of the storage device. At least one of the first port and the second port is connected to another storage device outside the storage device. When the first port is connected to another storage device, the FPGA board provides a path for transferring data in a peer-to-peer manner between the storage controller and another storage device without intervention of a host.

Description

TECHNICAL FIELD [0001] The present invention relates to a storage device that performs peer-to-peer communication with an external device without intervention of a host.

The present disclosure relates to electronic devices, and more particularly to configurations and operations of storage devices that store and output data.

Various types of electronic devices have been used in recent years. The electronic device performs its own functions according to the operations of the electronic circuits included therein. The electronic device can perform its own function while operating alone. In some cases, the electronic device can perform its own functions while communicating with other electronic devices.

Storage devices are an example of a variety of electronic devices. The storage device is capable of storing and outputting data according to the operations of the components included therein and thus can provide storage services to the user. The storage device can manage data on its own, or can manage data while communicating with other electronic devices.

As diverse information circulates and the volume of data increases dramatically, the capacity of storage devices is also increasing to manage large amounts of data. Moreover, in order to store a larger amount of data, a plurality of storage devices can be employed together to manage data of a single electronic system. A plurality of storage devices communicate with each other and can store and output data, and can provide capacity for storing a larger amount of data.

However, if the amount of data managed in a plurality of storage devices becomes excessive and the performance of each storage device increases, the load on managing storage devices and data may increase. In particular, if the host system is dedicated to managing storage devices and data, the workload of the host system can be increased.

The present disclosure can provide a storage device configured to perform peer-to-peer communication with another storage device without the intervention of a host.

In some embodiments, the storage device may include a Field Programmable Gate Array (FPGA) board and a storage controller. The FPGA board can be connected to the first port of the storage device. The first interface circuit of the storage controller may be coupled to the FPGA board and the second interface circuit of the storage controller may be coupled to the second port of the storage device. At least one port of the first port and the second port may be connected to another storage device outside the storage device. When the first port is connected to another storage device, the FPGA board can provide a path for transferring data in a peer-to-peer manner between the storage controller and another storage device without the intervention of the host.

In some embodiments, the storage device may comprise a storage controller and a memory device. The first interface circuit of the storage controller may be coupled to a first port of the storage device and the second interface circuit of the storage controller may be coupled to a second port of the storage device. The memory device can store or output data according to the control of the storage controller. The first interface circuit may operate in an operating mode selected from a plurality of operating modes based on whether the first port is connected to another device external to the storage device and the type of another device connected to the first port. When the first port is connected to another storage device external to the storage device, the storage controller can exchange data in a peer-to-peer manner with another storage device through the first port without the intervention of the host.

In some embodiments, the storage device may comprise a storage controller and arithmetic logic circuitry. The storage controller may be located between a first port of the storage device and a second port of the storage device. The arithmetic logic circuit may perform processing operations based on data received from the storage controller or the second port to produce the processed data. When the first port is connected to another storage device outside the storage device, the storage device can output the processed data to the other storage device via the first port without the intervention of the host.

In some embodiments, the storage device may comprise a storage controller and a memory device. The storage controller may be located between a first port of the storage device and a second port of the storage device. The memory device can store or output data according to the control of the storage controller. When the first port is connected to another storage device outside the storage device, the storage device stores third data generated based on at least one of the first data stored in the memory device and the second data received via the second port Can be output to the other storage device via the first port without involvement of the host.

In some embodiments, the storage system may include a first storage device and a second storage device. The first storage device may include a first port and a second port, and the second storage device may include a third port. The second port can be connected to the third port and the first storage device can communicate with the second storage device via the second port and the third port without the intervention of the host. The first storage device may output the third data via the second port based on at least one of the first data received through the first port and the second data stored in the first storage device. The second storage device may generate the fifth data based on at least one of the third data received via the third port and the fourth data stored in the second storage device. The operation result corresponding to the request of the host can be provided to the host based on the fifth data.

According to embodiments of the present disclosure, a plurality of storage devices can perform peer-to-peer communication without the intervention of the host. Thus, even if the amount of data increases and the performance of each storage device increases, the load on the host for managing storage devices and data can be significantly reduced. This can reduce the design and management costs of the entire electronic system.

1 is a block diagram illustrating an exemplary configuration of an electronic system according to some embodiments.
2 is a conceptual diagram illustrating an exemplary implementation associated with the storage device of FIG.
Figures 3 and 4 are block diagrams illustrating exemplary configurations associated with the electronic system of Figure 1;
5 is a block diagram illustrating an exemplary configuration associated with the storage devices of FIG.
FIGS. 6 through 10 are block diagrams illustrating exemplary operations associated with the storage devices of FIG.
Figures 11 and 12 are block diagrams illustrating exemplary configurations associated with the storage devices of Figure 5.
Figures 13 and 14 are block diagrams illustrating exemplary configurations associated with the storage device of Figure 1;
15 is a block diagram illustrating an exemplary configuration associated with the storage devices of FIG.
Figs. 16 and 17 are flowcharts illustrating exemplary operations of the variable interface circuit of Fig.
18 is a block diagram illustrating an exemplary configuration associated with the storage devices of FIG.
19 is a conceptual diagram illustrating an exemplary implementation associated with the electronic system of FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

1 is a block diagram illustrating an exemplary configuration of an electronic system 1000 in accordance with some embodiments.

The electronic system 1000 may include a main processor 1101, a working memory 1200, a storage system 1300, a communication block 1400, a user interface 1500, and a bus 1600. By way of example, electronic system 1000 may be a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a video game console, a workstation, one or more servers, an electric vehicle, Or the like.

The main processor 1101 can control the overall operations of the electronic system 1000. By way of example, main processor 1101 may be implemented as a general purpose processor, a dedicated processor, or an application processor, including one or more processor cores.

The working memory 1200 may store data used in the operation of the electronic system 1000. By way of example, the working memory 1200 may temporarily store data to be processed or to be processed by the main processor 1101. [ For example, the working memory 1200 may be a volatile memory such as SRAM (Static Random Access Memory), DRAM (Dynamic RAM), SDRAM (Synchronous RAM), and / ), ReRAM (Resistive RAM), FRAM (Ferro-electric RAM), and the like.

The storage system 1300 may include one or more storage devices. By way of example, the storage system 1300 may include storage devices 1300a, 1300b, and 1300c. Although FIG. 1 illustrates three storage devices 1300a, 1300b, and 1300c, the number of storage devices included in the storage system 1300 may vary or be varied to suit the requirements of the electronic system 1000 Can be modified.

Each storage device 1300a, 1300b, and 1300c can store data regardless of power supply. By way of example, each storage device 1300a, 1300b, 1300c may include a non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, By way of example, each storage device 1300a, 1300b, 1300c may include a storage medium such as a solid state drive (SSD), card storage, embedded storage, and the like.

Communication block 1400 may support at least one of various wireless / wired communication protocols for communicating with an external device / system of electronic system 1000. The user interface 1500 may include various input / output interfaces to mediate communication between the user and the electronic system 1000. [

The bus 1600 may provide a communication path between the components of the electronic system 1000. The components of the electronic system 1000 may exchange data according to the bus format of the bus 1600. For example, the bus format may be a USB (Universal Serial Bus), a Small Computer System Interface (SCSI), a Peripheral Component Interconnect Express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached SCSI (SAS), a Nonvolatile Memory Express , UFS (Universal Flash Storage), DDR (Double Data Rate), and LPDDR (Low Power DDR).

In the following, embodiments related to the exemplary configurations and storage devices 1300a, 1300b, and 1300c related to the PCIe protocol will be described. However, the embodiments of the present disclosure may be variously modified or modified so as to be employed in connection with other interface protocols other than the PCIe protocol. Furthermore, embodiments of the present disclosure may be employed in any electronic device (e.g., working memory 1200) capable of storing and outputting data, as well as storage devices 1300a, 1300b, and 1300c. The following description is provided to enable a better understanding, and is not intended to limit the invention.

FIG. 2 is a conceptual diagram illustrating an exemplary implementation associated with the storage device 1300a of FIG.

In some embodiments, the storage device 1300a may include a printed circuit board (PCB) 1307a. The storage device 1300a may include one or more chips or packages mounted or mounted on the PCB 1307a. As an example, memory devices 1310a and storage controller 1330a may be mounted or mounted on PCB 1307a.

The storage controller 1330a can control and manage the overall operations of the storage device 1300a. To this end, the storage controller 1330a may include hardware circuitry (e.g., analog circuitry, logic circuitry, etc.) configured to perform the intended operations. Additionally or alternatively, the storage controller 1330a may include one or more processor cores configured to execute a set of instructions of the program code for performing the intended operations.

Memory devices 1310a may comprise one or more types of memories. The memory devices 1310a may store or output data under the control of the storage controller 1330a. By way of example, memory devices 1310a may communicate with storage controller 1330a via conductive patterns printed on PCB 1307a.

In some embodiments, the storage device 1300a may be configured to communicate with other devices external to the storage device 1300a via a dual-port. By way of example, the dual-port of the storage device 1300a may include a first port and a second port, and the storage device 1300a may receive data from another device via the first port and the second port, As shown in FIG. By way of example, if storage device 1300a is an SSD, storage device 1300a may be referred to as a dual-port SSD.

By way of example, storage device 1300a may include connectors 1390a, 1395a corresponding to a dual-port. The connectors 1390a, 1395a may include pins or patterns 1391a, 1396a embodied in a conductive material. By way of example, each of the connectors 1390a, 1395a may be connected to another device, either directly or indirectly (e.g., via leads, cables, etc.). In this case, the storage device 1300a can exchange data with other devices via pins or patterns 1391a, 1396a.

By way of example, connector 1390a and fins or patterns 1391a may correspond to a first port, and connector 1395a and fins or patterns 1396a may correspond to a second port. By way of example, the storage controller 1330a may be connected to the pins or patterns 1391a, 1396a via conductive patterns printed on the PCB 1307a. Accordingly, the storage controller 1330a can output or receive data via the first port and the second port.

The first port and the second port may provide independent communication. By way of example, outputting or receiving data via the first port may be independent of outputting or receiving data via the second port.

(E.g., the number of memory devices 1310a, the placement of memory devices 1310a and storage controller 1330a, the location and shape of connectors 1390a, 1395a, pins or patterns The positions and shapes of the light emitting elements 1391a and 1396a, and the like) may be variously modified or modified so as to be different from those shown in Fig. The exemplary implementation of FIG. 2 is provided to enable a better understanding, and is not intended to limit the present invention. The storage devices 1300b and 1300c may be configured to be the same as or similar to the storage device 1300a.

3 is a block diagram illustrating an exemplary configuration associated with the electronic system 1000 of FIG.

By way of example, electronic system 1000 may include configuration 1000a. The configuration 1000a may include a main processor 1101, a root complex 1003, a switch 1005, a working memory 1200, and storage devices 1300a and 1300b.

The root complex 1003 may manage data flow among the components of the electronic system 1000. By way of example, the root complex 1003 may control the data path, schedule data delivery, or resolve communication conflicts. By way of example, the main processor 1101, the working memory 1200, and the storage devices 1300a and 1300b can be connected to the root complex 1003, communicate with each other via the root complex 1003, have.

In some cases, switch 1005 may be further connected to root complex 1003 and storage devices 1300a and 1300b may be connected to root complex 1003 via switch 1005. By way of example, switch 1005 may include a PCIe switch or other type of switch. The switch 1005 can control the data path between the root complex 1003 and the storage devices 1300a and 1300b. The root complex 1003 and the switch 1005 may be implemented as hardware circuits for data control and data transfer.

In some instances, storage device 1300a may be coupled to switch 1005 via a dual-port. The first port of the storage device 1300a may provide a data path P11 between the storage device 1300a and the switch 1005 and the second port of the storage device 1300a may provide the data path P11 between the storage device 1300a And a switch 1005. The switch 1005 may be connected to the switch 1005 via a data path P12. Similarly, storage device 1300b may also be coupled to switch 1005 via a dual-port. Although not shown in FIG. 3, the storage device 1300c may also be coupled to the switch 1005 via a dual-port.

The main processor 1101 can communicate with the storage devices 1300a and 1300b via the root complex 1003 and the switch 1005. [ In this disclosure, an object capable of accessing components of electronic system 1000, such as storage devices 1300a, 1300b, may be referred to as a " host ". The main processor 1101 may be an example of objects that can operate as a host, but the present invention is not limited thereto.

Reliability can be improved if each storage device 1300a, 1300b communicates with the main processor 1101 via a dual-port. For example, even if one port of the storage device 1300a fails or is disabled, another port can support communication.

In the example of FIG. 3, the storage devices 1300a and 1300b can communicate with each other in a peer-to-peer manner via the switch 1005. [ In this case, a host (e.g., main processor 1101) may intervene in communication between storage devices 1300a and 1300b.

By way of example, when data is transferred from storage device 1300a via switch 1005 to storage device 1300b, main processor 1101 controls the data path to storage device 1300b and maps the memory address . ≪ / RTI > To this end, the main processor 1101 may intervene in processing data exchanged between the storage devices 1300a, 1300b.

On the other hand, when the capacity of each of the storage devices 1300a and 1300b is large, the amount of data exchanged between the storage devices 1300a and 1300b may be large. In addition, the performance of each of the storage devices 1300a and 1300b may be high to manage a large amount of data. In this case, as the host intervenes in processing the data exchanged between the storage devices 1300a and 1300b, the workload of the host may become worse.

4 is a block diagram illustrating an exemplary configuration associated with the electronic system 1000 of FIG.

By way of example, electronic system 1000 may include configuration 1000b. The configuration 1000b may include a main processor 1101, a root complex 1003, a switch 1005, a working memory 1200, and storage devices 1300a and 1300b.

In the configuration 1000b according to some embodiments, neither the first port nor the second port of the storage device 1300a may be connected to the switch 1005. [ Instead, the first port of the storage device 1300a may be coupled to the storage device 1300b, and the second port of the storage device 1300a may be coupled to the switch 1005. [

By way of example, a second port of the storage device 1300a may provide a data path P21 between the storage device 1300a and the switch 1005, and a first port of the storage device 1300a may be a storage device 1300a, and 1300b. Storage device 1300a may communicate with main processor 1101 via data path P21, switch 1005, and root complex 1003.

Similarly, one port of the dual-port of storage device 1300b may be coupled to storage device 1300a. Storage device 1300a may communicate with storage device 1300b in a peer-to-peer manner via data path P22. Although not shown in FIG. 4, the storage device 1300c may also be connected to the storage device 1300a or 1300b via one port of a dual-port for peer-to-peer communication.

The other port of the dual-port of the storage device 1300b may or may not be connected to the switch 1005. If the storage device 1300b is not connected to the switch 1005, the storage device 1300b can communicate with the main processor 1101 via the storage device 1300a. When the storage device 1300b is connected to the switch 1005, the storage device 1300b can communicate with the main processor 1101 via the switch 1005. [

In configuration 1000b, switch 1005 may not be required for communication between storage devices 1300a and 1300b. Data exchanged between the storage devices 1300a and 1300b may be processed by the storage device 1300a and / or the storage device 1300b. The host (e.g., main processor 1101) may not intervene (or at least intervene) in processing data exchanged between storage devices 1300a, 1300b.

Some or all of the data manipulation performed on the host in configuration 1000a may be performed by storage devices 1300a and 1300b in configuration 1000b. Thus, in configuration 1000b, even if the amount of data exchanged between storage devices 1300a, 1300b increases and the performance of storage devices 1300a, 1300b increases, the workload of the host can be significantly reduced have. This can reduce the design and management costs of the entire electronic system 1000.

4 shows that the storage device 1300a is connected to the switch 1005. Fig. In some embodiments, storage device 1300a may be coupled to root complex 1003 without switch 1005. [ The electronic system 1000 can be variously modified or modified to be different from the configuration 1000b.

FIG. 5 is a block diagram illustrating an exemplary configuration associated with the storage devices 1300a, 1300b, and 1300c of FIG.

In some embodiments, the storage devices 1300a, 1300b, and 1300c may include storage devices 1301a, 1301b, and 1301c, respectively. Similar to those described with reference to Fig. 4, the storage devices 1301a, 1301b, 1301c may be interconnected without a root complex 1003 or switch 1005 to communicate in a peer-to-peer manner. To this end, each of the storage devices 1301a, 1301b, and 1301c may be implemented as a dual-port structure.

FIG. 5 shows that the storage devices 1301a and 1301c are directly connected to the main processor 1101. FIG. However, in some embodiments, a root complex 1003 and / or a switch 1005 may be provided between the storage devices 1301a and 1301c and the main processor 1101. [ In this disclosure, the connection to the main processor 1101 may include direct and indirect connections.

Storage device 1301a may include one or more memory devices 1310a, a storage controller 1331a, and a peer-to-peer manager 1350a. The storage controller 1331a may correspond to the storage controller 1330a. The storage controller 1331a can control and manage the overall operations of the storage device 1301a. The memory device 1310a can store or output data under the control of the storage controller 1331a.

The storage controller 1331a may include interface circuits 1335a and 1336a. Each of the interface circuits 1335a and 1336a includes a physical layer configured to transmit / receive and process data, signals, and / or packets to cause the storage controller 1331a to communicate with components external to the storage controller 1331a, / ≪ / RTI > logic layer. Each of the interface circuits 1335a, 1336a may include hardware circuitry configured to handle communications between the storage controller 1331a and the external components.

By way of example, interface circuit 1335a may be coupled to a second port of storage device 1301a. A second port of the storage device 1301a may provide a data path P21a between the storage controller 1331a and the main processor 1101. [ Storage device 1301a may communicate with main processor 1101 via interface circuitry 1335a, data path P21a, and a second port.

By way of example, interface circuitry 1336a may be coupled to peer-to-peer manager 1350a. A data path P23a may be provided between the interface circuit 1336a and the peer-to-peer manager 1350a. Storage controller 1331a may communicate with peer-to-peer manager 1350a via interface circuit 1336a and data path P23a.

The peer-to-peer manager 1350a may be coupled to a first port of the storage device 1301a. The peer-to-peer manager 1350a may be located between the first port and the storage controller 1331a. The storage controller 1331a may be located between a first port of the storage device 1301a and a second port of the storage device 1301a.

The storage device 1301a may be connected to another device (e.g., storage device 1301b) outside the storage device 1301a via the first port. A first port of the storage device 1301a may provide a data path P22a between the peer-to-peer manager 1350a and the storage device 1301b. Storage device 1301a may communicate with storage device 1301b via data path P22a and a first port.

Peer-to-peer manager 1350a may include internal switch 1351a and arithmetic logic circuit 1352a. Internal switch 1351a and arithmetic logic circuitry 1352a may communicate with each other via a bus within peer-to-peer manager 1350a. Depending on the operations of the internal switch 1351a and the arithmetic logic circuit 1352a, the peer-to-peer manager 1350a may exchange data in a peer-to-peer manner between the storage controller 1331a and the storage device 1301b (E. G., Data paths P22a and P23a) for transmission.

The internal switch 1351a can manage the data output from the storage device 1301a through the first port and the flow of data received by the storage device 1301a through the first port. Thus, the peer-to-peer manager 1350a can output data to the storage device 1301b via the first port or to the storage device 1301b via the first port based on the data exchanged with the storage controller 1331a As shown in FIG.

The internal switch 1351a may be implemented as a hardware circuit for managing the data flow. Here, the term " switch " is used, but the implementation of internal switch 1351a can be variously modified or modified. By way of example, internal switch 1351a may be implemented in the form of an internal root complex to control the data path (similar to root complex 1003), to schedule data transfers, or to resolve communication conflicts. Alternatively, internal switch 1351a may be implemented in the form of an internal root complex combined with a switch (similar to root complex 1003 and switch 1005).

However, the internal switch 1351a can manage only the data flow between the storage controller 13331a and the first port. Thus, the internal switch 1351a can be implemented to have a smaller size than the size of the root complex 1003 and / or the switch 1005 (e.g., circuit size, circuit area, circuit scale, etc.).

The arithmetic logic circuitry 1352a may perform processing operations based on data received at the peer-to-peer manager 1350a. By way of example, a processing operation may include operations to monitor information (e.g., amount of data, data path, address, etc.) associated with the received data, Redundant Array of Independent Disks (RAID) operations based on the received data, Based Regular Expression Search operation, and the like. However, the present invention is not limited to this example.

By way of example, arithmetic logic circuit 1352a may perform processing operations based on data received from storage controller 1331a and may generate processed data to be output via the first port by processing the received data have. By way of example, arithmetic logic circuitry 1352a may perform processing operations based on data received over the first port and may process the received data to generate processed data to be provided to storage controller 1331a have.

To this end, arithmetic logic circuitry 1352a may be implemented with hardware circuitry configured to perform processing operations. In some embodiments, the peer-to-peer manager 1350a may include a form of an FPGA (Field Programmable Gate Array) board or ASICs (Application Specific Integrated Circuits) separate from the storage controller 1331a in the set of storage devices 1301a . ≪ / RTI > As an example, the arithmetic logic circuit 1352a may be implemented as a reconfigurable logic circuit based on the configuration of the FPGA board.

Thus, rather than simply managing the data flow, the peer-to-peer manager 1350a may process or transform the received data itself to output processed or transformed data. The output data may be provided to the storage controller 1331a or may be provided to the storage device 1301b via the first port. To this end, the peer-to-peer manager 1350a may include a storage controller 1331a and two downstream ports connected to the first port.

The processing operation of the arithmetic logic circuit 1352a may be performed by the main processor 1101. [ However, in embodiments, to alleviate the workload of main processor 1101, storage device 1301a may perform arithmetic operations using arithmetic logic circuitry 1352a instead. Examples related to the machining operation will be described with reference to Figs. 6 to 9. Fig.

Storage device 1301b may include one or more memory devices 1310b, a storage controller 1331b, and a peer-to-peer manager 1350b. Storage controller 1331b may include interface circuits 1335b and 1336b. Peer-to-peer manager 1350b may include internal switch 1351b and arithmetic logic circuit 1352b.

The peer-to-peer manager 1350b may be coupled to the storage device 1301c via a first port of the storage device 1301b and a data path P24a. The interface circuit 1335b may be connected to the storage device 1301a via the second port of the storage device 1301b and the data path P22a. Interface circuit 1336b may be coupled to peer-to-peer manager 1350b via data path P25a.

A storage device 1301b, a memory device 1310b, a storage controller 1331b, interface circuits 1335b and 1336b, a peer-to-peer manager 1350b, an internal switch 1351b and an arithmetic logic circuit 1352b. A peer-to-peer manager 1350a, an internal switch 1351a, and an arithmetic logic circuit 1352a, a storage device 1301a, a memory device 1310a, a storage controller 1331a, interface circuits 1335a and 1335b, ), Respectively, as shown in FIG. For brevity, redundant descriptions will be omitted below.

Storage device 1301c may include one or more memory devices 1310c, a storage controller 1331c, and a peer-to-peer manager 1350c. The storage controller 1331c may include interface circuits 1335c and 1336c. Peer-to-peer manager 1350c may include internal switch 1351c and arithmetic logic circuit 1352c.

The peer-to-peer manager 1350c may be connected to the main processor 1101 via a first port of the storage device 1301c and a data path P27a. The interface circuit 1335c may be connected to the storage device 1301b through the second port of the storage device 1301c and the data path P24a. Interface circuit 1336c may be coupled to peer-to-peer manager 1350c via data path P26a.

A storage device 1301c, a memory device 1310c, a storage controller 1331c, interface circuits 1335c and 1336c, a peer-to-peer manager 1350c, an internal switch 1351c and an arithmetic logic circuit 1352c. A peer-to-peer manager 1350a, an internal switch 1351a, and an arithmetic logic circuit 1352a, a storage device 1301a, a memory device 1310a, a storage controller 1331a, interface circuits 1335a and 1335b, ), Respectively, as shown in FIG. For brevity, redundant descriptions will be omitted below.

At each storage device 1301a, 1301b, 1301c, at least one port of the first port and the second port may be connected to another storage device. Meanwhile, a port other than the first port and the second port that are not connected to another storage device may be connected to the host (e.g., the main processor 1101).

For example, in the storage device 1301b, if both the first port and the second port are connected to another storage device, the storage device 1301b may not be connected to the host. In this case, the storage apparatus 1301b may not directly communicate with the main processor 1101. [ Instead, the storage device 1301b may communicate with the main processor 1101 via the storage device 1301a or 1301c.

Some ports of the storage devices 1301a, 1301b, and 1301c may not be connected to the main processor 1101. [ However, when the data paths P21a and P27a to the main processor 1101 are provided, the reliability can be improved. By way of example, data path P21a may provide communication with main processor 1101, even if data path P27a is faulty or inactive.

FIGS. 6-9 are block diagrams illustrating exemplary operations associated with the storage devices 1301a, 1301b, and 1301c of FIG.

The exemplary operations of FIGS. 6-9 illustrate that a host (e.g., main processor 1101) may perform a RAID operation (e.g., parity) with respect to data D1, D2, D3 stored in storage devices 1301a, 1301b, Operation) on the request. The arithmetic logic circuits 1352a, 1352b, and 1352c may perform a RAID operation as a machining operation.

Referring to FIG. 6, the storage controller 1331a may receive a request (REQ) from the main processor 1101 through the second port of the storage device 1301a and the interface circuit 1335a. The request REQ may be directed to the storage device 1301a and other storage devices (e.g., storage devices 1301b and 1301c). As an example, the request REQ may request to calculate the parity corresponding to data D1, D2, D3.

Referring to FIG. 7, in response to a request (REQ), the storage controller 1331a may perform the requested operation on the storage device 1301a. By way of example, the storage controller 1331a may control the memory device 1310a such that the memory device 1310a outputs the data D1.

Further, in response to the request (REQ), the storage controller 1331a may exchange data associated with the requested operation for the other storage device via the interface circuit 1336a with the peer-to-peer manager 1350a . As an example, the storage controller 1331a may provide the data D1 to the peer-to-peer manager 1350a.

The arithmetic logic circuit 1352a may perform processing operations based on at least one of the data stored in the memory device 1310a and the data received via the second port of the storage device 1301a. By way of example, arithmetic logic circuitry 1352a may perform arithmetic operations (e.g., parity arithmetic) based on data D1.

The arithmetic logic circuit 1352a may process the data D1 to produce processed data D1 '. The data D1 'may be used for operations to be performed in the storage device 1301b. The parity operation is still performed on only one data D1, and the data D1 'may be the same as the data D1.

The internal switch 1351a can manage the flow of data D1 and D1 '. The internal switch 1351a can receive the data D1 from the storage controller 1331a and output the data D1 'to the first port of the storage device 1301a. Thus, the peer-to-peer manager 1350a can output the data D1 'to the storage device 1301b without involvement of the host.

The storage device 1301a can communicate with the storage device 1301b through the first port of the storage device 1301a and the second port of the storage device 1301b without the intervention of the host. The storage controller 1331b may receive the data D1 'from the storage device 1301a via the second port of the storage device 1301b and the interface circuit 1335b.

Referring to Figure 8, the storage controller 1331b may perform the requested operation on the storage device 1301b. By way of example, storage controller 1331b may control memory device 1310b such that memory device 1310b outputs data D2. To this end, for example, the storage controller 1331b may receive information regarding the data D2 and the request REQ from the storage device 1301a together with the data D1 '. The storage controller 1331b may provide the data D1 ', D2 via the interface circuit 1336b to the peer-to-peer manager 1350b.

The arithmetic logic circuitry 1352b may perform processing operations based on at least one of the data stored in the memory device 1310b and the data received via the second port of the storage device 1301b. By way of example, the arithmetic logic circuit 1352b may perform a parity operation based on the data D1 ', D2. The arithmetic logic circuit 1352b may process the data D1 ', D2 to produce processed data D2'.

The parity operation performed by arithmetic logic circuit 1352a may include a first portion of the overall operation requested by main processor 1101 (e.g., a partial operation on data D1). As the storage device 1301a outputs the data D1 'to the storage device 1301b, the arithmetic logic circuit 1352b generates a second portion of the overall operation requested by the main processor 1101 ', D2), for example. Here, the operation of the second part may not overlap with the operation of the first part.

As the arithmetic logic circuit 1352b performs the parity operation, the data D2 'may be generated so as to be different from the data D1' and the data D2, respectively. The data D2 'may be used for operations to be performed in the storage device 1301c.

The internal switch 1351b can manage the flow of data D1 ', D2, and D2'. The internal switch 1351b can receive the data D1 'and D2 from the storage controller 1331b and output the data D2' to the first port of the storage device 1301b. The peer-to-peer manager 1350b can output the data D2 'to the storage device 1301c without involvement of the host.

The storage device 1301b can communicate with the storage device 1301c through the first port of the storage device 1301b and the second port of the storage device 1301c without the intervention of the host. The storage controller 1331c can receive the data D2 'from the storage device 1301b via the second port of the storage device 1301c and the interface circuit 1335c.

9, the storage controller 1331c may control the memory device 1310c such that the memory device 1310c outputs the data D3. The storage controller 1331c may provide the data D2 ', D3 to the peer-to-peer manager 1350c via the interface circuit 1336c.

The arithmetic logic circuit 1352c may perform a parity operation based on the data D2 'and D3. The arithmetic logic circuit 1352c can generate parity (P) as the processed data. The parity P may be an operation result corresponding to the request (REQ) of the main processor 1101.

The entire operation requested by the main processor 1101 to obtain the parity P may be performed on the storage devices 1301a, 1301b, and 1301c in a distributed manner. The main processor 1101 may not intervene in the parity operation, and thus the workload of the main processor 1101 may be reduced. Each of the arithmetic logic circuits 1352a, 1352b, 1352c may partially perform the entire operation. As the partial operations are successively performed, the entire operation can be completed and the parity P can be obtained.

The internal switch 1351c can receive the data D2 'and D3 from the storage controller 1331b and output the parity P to the first port of the storage device 1301c. The storage apparatus 1301c can output the parity P through the first port of the storage apparatus 1301c. Accordingly, the parity P may be provided to the main processor 1101. [

10 is a block diagram illustrating exemplary operations associated with the storage devices 1301a, 1301b, and 1301c of FIG.

In some cases, the data path P27a of FIG. 5 may not be connected. By way of example, data path P27a may be faulty or inactive. For example, in order to simplify the circuit configuration, the data path P27a may not be provided.

In this case, the storage apparatus 1301c can transmit the parity P to the storage apparatus 1301b through the second port of the storage apparatus 1301c and the first port of the storage apparatus 1301b. In this manner, the parity P may be provided to the main processor 1101 through the storage devices 1301b and 1301a. The storage apparatus 1301a can output the parity P to the main processor 1101 through the second port of the storage apparatus 1301a.

In the example of FIG. 10, the direction of the path for transferring the parity P to the main processor 1101 may be opposite to the direction of the path for transferring data in the examples of FIGS. The interface circuits 1335a, 1336a, 1335b, 1336b, 1335c and 1336c and the peer-to-peer managers 1350a, 1350b and 1350c may support bi-directional communication.

Exemplary operations have been described with reference to Figures 6-10. However, these descriptions are provided to enable a better understanding, and are not intended to limit the present invention. Operations of the storage devices 1301a, 1301b, 1301c may be variously modified or modified to provide peer-to-peer communication and processing operations between the storage devices 1301a, 1301b, 1301c. Further, it will be appreciated that embodiments of the present disclosure may be applied to various processing operations other than parity operations.

Figures 11 and 12 are block diagrams illustrating exemplary configurations associated with the storage devices 1301a, 1301b, and 1301c of Figure 5.

Referring to FIG. 11, the main processor 1101 can communicate with the storage devices 1301a, 1301b, and 1301c through data paths P21b and P27b. Storage devices 1301a, 1301b, and 1301c may communicate with each other in a peer-to-peer manner via data paths P22b through P26b. The data paths P21b to P27b may correspond to the data paths P21a to P27a, respectively.

Unlike the exemplary operations of FIGS. 6-10, in the example of FIG. 11, a storage device 1301c may receive a request from the main processor 1101. FIG. The peer-to-peer manager 1350c may perform processing operations in response to a request from the main processor 1101, and thus may provide the processed data to the storage controller 1331c.

In this manner, the peer-to-peer managers 1350c, 1350b, 1350a can perform the entire operations requested by the main processor 1101 in a distributed manner, and thus generate the operation results. The operation result may be output to the main processor 1101 through the storage controller 1331a of the storage device 1301a.

In some embodiments, arithmetic logic circuitry may not be provided between the main processor 1101 and the storage controller 1331a. In some cases, additional processing may be required for the data output from the storage controller 1331a. As an example, additional parity operations may be required for the processed data provided from the peer-to-peer manager 1350a and the data stored in the memory device 1310a of the storage device 1301a, and the storage controller 1331a, May provide the processed data and the stored data to the main processor 1101.

In this example, the main processor 1101 may perform additional parity operations. Although the main processor 1101 partially intervenes in the machining operations, the peer-to-peer managers 1350c, 1350b, 1350a may perform most of the overall operation. Furthermore, the main processor 1101 may not intervene in communication between the storage devices 1301a, 1301b, and 1301c. Therefore, the intervention of the main processor 1101 can be minimized.

Referring to FIG. 12, in some cases, the data path P21b of FIG. 11 may not be connected. By way of example, data path P21b may be faulty or inactive. For example, in order to simplify the circuit configuration, the data path P21b may not be provided. In this case, the operation result of the peer-to-peer manager 1350a may be provided to the main processor 1101 through the storage devices 1301b and 1301c. In the example of FIG. 12, the direction of the path for transferring the operation result to the main processor 1101 may be opposite to the direction of the path for transferring data in the example of FIG.

Each of the interface circuits 1335a, 1336a, 1335b, 1336b, 1335c and 1336c is connected to the main processor 1101 or the peer-to-peer managers 1350a, 1350b, and 1350c, respectively. Accordingly, the interface circuits 1335a, 1336a, 1335b, 1336b, 1335c, and 1336c may operate to operate the respective storage devices 1301a, 1301b, and 1301c as endpoint devices.

13 and 14 are block diagrams illustrating exemplary configurations associated with the storage device 1300a of FIG.

Referring to FIG. 13, in some embodiments, the storage device 1300a may include a storage device 1302a. Storage device 1302a may include one or more memory devices 1310a, a storage controller 1332a, and arithmetic logic circuitry 1355a. The storage controller 1332a may include an interface circuit 1337a and a variable interface circuit 1338a.

The storage controller 1332a, the interface circuit 1337a and the arithmetic logic circuit 1355a may correspond to the storage controller 1331a, the interface circuit 1335a, and the arithmetic logic circuit 1352a, respectively. The storage controller 1332a can control and manage the overall operations of the storage device 1302a. The interface circuit 1337a can support communication with an A device (e.g., a host, another storage device, etc.) outside the storage device 1302a through a second port of the storage device 1302a.

The arithmetic logic circuit 1355a may perform processing operations to generate processed data. The arithmetic logic circuit 1355a may exchange data with a B device (e.g., a host, another storage device, etc.) external to the storage device 1302a via a first port of the storage device 1302a. The arithmetic logic circuit 1355a may be connected to a variable interface circuit 1338a.

The internal switch 1351a and the arithmetic logic circuit 1352a described with reference to Figs. 5 to 12 may be implemented on one component (e.g., one FPGA board, one chip, etc.). However, in some embodiments, internal switch 1351a and arithmetic logic circuit 1352a may be implemented as separate components (e.g., separate chips, separate circuits, etc.). When the internal switch 1351a is disconnected from the arithmetic logic circuit 1352a, in some embodiments, the internal switch 1351a may be implemented within the storage controller 1331a.

By way of example, the variable interface circuit 1338a of the storage controller 1332a can include the configurations of the internal switch 1351a and perform the operations of the internal switch 1351a. The variable interface circuit 1338a may operate in an operation mode selected from a plurality of operation modes. The operational mode may be selected based on whether the first port of the storage device 1302a is connected to the B device and the type of the connected B device.

By way of example, the operational mode of the variable interface circuit 1338a may include a termination mode of operation associated with the operation of the terminating device (e.g., to support the storage device 1302a such that the storage device 1302a operates as a terminating device) . By way of example, the operational mode of the variable interface circuit 1338a may include a switch operation mode (e.g., to support communication with the B device) associated with communication with the B device.

To this end, the variable interface circuit 1338a may comprise a physical and / or logical layer of hardware circuitry configured to transmit / receive and process data, signals and / or packets. Further, variable interface circuit 1338a may include hardware circuitry of the root complex and / or switch to manage the exchange of data with the B device. Variable interface circuit 1338a may operate differently depending on the selected operating mode.

14, in some embodiments, the storage device 1300a may include a storage device 1303a. Storage device 1303a may include one or more memory devices 1310a and a storage controller 1333a. The storage controller 1333a may include an interface circuit 1337a, a variable interface circuit 1338a, and an internal arithmetic logic circuit 1339a. The storage controller 1333a may correspond to the storage controller 1331a and may control and manage the overall operations of the storage device 1303a.

The interface circuit 1337a may be connected to the second port of the storage device 1303a and may support communication with the A device through the second port. The variable interface circuit 1338a may be connected to the first port of the storage device 1303a and may support communication with the B device via the first port. Variable interface circuit 1338a may operate in an operating mode that is selected based on whether the first port of storage device 1303a is connected to the B device and the type of connected B device.

In some embodiments, arithmetic logic circuit 1352a or 1355a may also be implemented within storage controller 1331a. By way of example, the internal arithmetic logic circuit 1339a of the storage controller 1333a may include the arrangements of arithmetic logic circuit 1352a or 1355a and may perform operations of arithmetic logic circuit 1352a or 1355a.

The interface circuit 1337a, the variable interface circuit 1338a, and the internal arithmetic logic circuit 1339a can communicate with each other via a bus inside the storage controller 1333a. By way of example, the embedded arithmetic logic circuit 1339a may be implemented in the form of an embedded FPGA or embedded ASICs. By way of example, the embedded arithmetic logic circuit 1339a may be implemented as a reconfigurable logic circuit.

The internal arithmetic logic circuit 1339a can perform the arithmetic operation. The internal arithmetic logic circuit 1339a may process the data received via the first port of the storage device 1303a to generate the processed data to be output via the second port of the storage device 1303a. The internal arithmetic logic circuit 1339a may process the data received via the second port of the storage device 1303a to generate processed data to be output via the first port of the storage device 1303a.

15 is a block diagram illustrating an exemplary configuration associated with the storage devices 1300a, 1300b, and 1300c of FIG.

In some embodiments, the storage devices 1300a, 1300b, and 1300c may include storage devices 1303a, 1303b, and 1303c, respectively. Each of the storage devices 1303a, 1303b, and 1303c may be implemented as a dual-port architecture and may communicate with each other in a peer-to-peer manner without the intervention of a host (e.g., main processor 1101).

Storage device 1303b may include one or more memory devices 1310b and a storage controller 1333b. The storage controller 1333b may include an interface circuit 1337b, a variable interface circuit 1338b, and an internal arithmetic logic circuit 1339b. The storage controller 1333b, the interface circuit 1337b, the variable interface circuit 1338b and the internal arithmetic logic circuit 1339b are connected to the storage controller 1333a, the interface circuit 1337a, the variable interface circuit 1338a, And logic circuit 1339a, respectively.

The storage device 1303c may include one or more memory devices 1310c and a storage controller 1333c. The storage controller 1333c may include an interface circuit 1337c, a variable interface circuit 1338c, and an internal arithmetic logic circuit 1339c. The storage controller 1333c, the interface circuit 1337c, the variable interface circuit 1338c and the internal arithmetic logic circuit 1339c are connected to the storage controller 1333a, the interface circuit 1337a, the variable interface circuit 1338a, And logic circuit 1339a, respectively. For brevity, redundant descriptions will be omitted below.

The interface circuit 1337a may be connected to the second port of the storage device 1303a. A second port of the storage device 1303a may provide a data path P21c between the storage controller 1333a and the main processor 1101. [ Accordingly, the storage device 1303a can communicate with the main processor 1101 via the data path P21c and exchange data.

The internal arithmetic logic circuit 1339a performs processing operations based on at least one of the data stored in the memory device 1310a and the data received via the second port (or first port) of the storage device 1303a . The internal arithmetic logic circuit 1339a can perform processing operations to generate processed data. The processed data may be output to another device (e.g., main processor 1101, storage device 1303b, etc.) via a first port (or a second port) of the storage device 1303a.

The variable interface circuit 1338a may be connected to the first port of the storage device 1303a. The interface circuit 1337b may be connected to the second port of the storage device 1303b. The first port of the storage device 1303a and the second port of the storage device 1303b may provide a data path P22c between the storage controllers 1333a and 1333b. Accordingly, the storage apparatus 1303a can communicate and exchange data with the storage apparatus 1303b in a peer-to-peer manner without the intervention of the main processor 1101. [

The internal arithmetic logic circuit 1339b performs processing operations based on at least one of the data stored in the memory device 1310b and the data received via the second port (or first port) of the storage device 1303b . The internal arithmetic logic circuit 1339b can perform processing operations to generate processed data. The processed data may be output to another device (e.g., storage device 1303a or 1303c, etc.) through a first port (or a second port) of the storage device 1303b.

Similarly, a first port of the storage device 1303b and a second port of the storage device 1303c may provide a data path P24c between the storage controllers 1333b and 1333c. The storage device 1303b communicates in a peer-to-peer manner with the storage device 1303c via the variable interface circuit 1338b, the data path P24c, and the interface circuit 1337c without the intervention of the main processor 1101 Data can be exchanged.

The first port of the storage device 1303c may provide a data path P27c between the storage controller 1333c and the main processor 1101. [ The storage device 1303c can communicate with and exchange data with the main processor 1101 via the variable interface circuit 1337c and the data path P27c. The internal arithmetic logic circuit 1339c can generate processed data based on at least one of the data received via the first and second ports of the storage device 1303c and the data stored in the memory device 1310c have.

By way of example, the storage controller 1333a may receive requests directed to the storage devices 1303a, 1303b, and 1303c via interface circuitry 1337a. The storage controller 1333a may perform the requested operation on the storage device 1303a. The storage controller 1333a may output or receive data associated with the requested operation for the storage devices 1303b and 1303c via the variable interface circuit 1338a.

The built-in arithmetic logic circuits 1339a, 1339b, and 1339c may perform the entire operations requested by the main processor 1101 in a distributed manner. Accordingly, the storage controller 1333c can output the data of the operation result corresponding to the request of the main processor 1101 to the main processor 1101 through the variable interface circuit 1338c. In some cases, the storage controller 1333c may receive data or requests from the main processor 1101 via the variable interface circuit 1338c.

The storage devices 1303a, 1303b, and 1303c may be configured and operated similarly to those described with reference to FIGS. In some cases, the data path P21c or P27c may not be provided, and the storage controllers 1333a, 1333b, and 1333c may support bi-directional communication. Although FIG. 15 shows a configuration associated with storage device 1303a of FIG. 14, storage device 1302a of FIG. 13 may also be employed in a manner similar to that described with reference to FIGS. 5-12 and 15 This will be well understood.

Each of the interface circuits 1337a, 1337b, and 1337c may be connected to the main processor 1101 or a downstream port. The interface circuits 1337a, 1337b, and 1337c may operate in a termination mode of operation. The variable interface circuit 1338c may be coupled to the main processor 1101 and thus may operate in the termination mode of operation. As the variable interface circuit 1338c operates in the termination mode of operation, the first port of the storage device 1303c can be understood as a downstream port.

The variable interface circuits 1338a and 1338b may be connected to the storage devices 1303b and 1303c, respectively. Each of the variable interface circuits 1338a and 1338b may operate in a switch operation mode to support communication with an external storage device. In switch operating mode, variable interface circuits 1338a, 1338b can provide the functionality of a root complex and / or switch to manage data exchange. As the variable interface circuits 1338a and 1338b operate in the switch operation mode, the first port of each of the storage devices 1303a and 1303b can be understood as an upstream port.

FIG. 15 shows that each of the storage devices 1303a, 1303b, and 1303c includes one variable interface circuit. In some embodiments, each of the storage devices 1303a, 1303b, 1303c may include two variable interface circuits. For example, the interface circuit 1337a of the storage device 1303a may also be implemented as a variable interface circuit. In this case, the interface circuit 1337a can also support communication with the external storage device as well as with the main processor 1101, so that flexibility in connection of the storage device 1303a can be improved.

16 is a flow chart illustrating an exemplary operation of the variable interface circuit of FIG.

As power is supplied to the storage device and the storage device is turned on, the storage device can initialize the configuration (S110). By way of example, a storage device may recognize and configure the status of components, connection status to external devices, settings, and the like during a boot operation.

Thereafter, the storage device can establish a linkup state with the connected external device (S120). The link-up state can be provided for recognizing the partner device and configuring an environment for communicating with the partner device. In order to set up the link-up state, the storage device can provide the information of the storage device (e.g., device type, communication performance, configuration of the transmission / reception circuit, etc.) to the external device, can do.

According to the link-up state, the storage device can acquire information of a connected external device (S130). For example, the storage device 1303a can recognize that the external device connected through the variable interface circuit 1338a is another storage device 1303b, and the storage device 1303c is connected through the variable interface circuit 1338c It can recognize that the external device is the main processor 1101. In some embodiments, the storage device may recognize the type of external device via additional pins (e.g., General Purpose Input / Output (GPIO) pins), regardless of the link up state.

The storage device can select the operation mode of the interface circuit based on the information of the connected external device (S140). For example, the storage controller 1333a may operate the variable interface circuit 1338a in a switch mode of operation in response to a connection to another storage device 1303b, and the storage controller 1333c may be coupled to the main processor 1101 The variable interface circuit 1338c can be operated in the termination operation mode in response.

17 is a flowchart illustrating an exemplary operation of the variable interface circuit of Fig.

By way of example, the variable interface circuit may first attempt to operate in a switch operating mode. In the attempted switch operation mode, the variable interface circuit may transmit a test signal (S210). The test signal may be configured to be suitable for identifying whether the external device is connected to a variable interface circuit and the type of external device. As another example, the variable interface circuit may first attempt to operate in the termination mode of operation and transmit a test signal.

The variable interface circuit or the storage controller may determine whether a response corresponding to the test signal is received (S220). If no response is received (No in S220), this indicates that the variable interface circuit is not connected to the external device. In this case, the variable interface circuit may be operated in the terminal operation mode or turned off to reduce power consumption (S240). Turn-off may mean a state in which the intended function or operation is not performed without power being supplied.

If a response is received (S220: Yes), this indicates that the variable interface circuit is connected to the external device. By way of example, the response from a terminating device (e.g., a storage device) may be implemented to differ from the response from the host (e.g., main processor 1101). In this case, the variable interface circuit or the storage controller may determine the type of external device corresponding to the response (e.g., determine whether the response is related to the end device or the host) (S230).

If the response is related to the terminal equipment (Yes in S230), the variable interface circuit can operate in the switch operation mode (S250). By way of example, variable interface circuit 1338a may provide operation of a root complex and / or switch in a switch mode of operation based on a response from storage device 1303b.

When the response is related to the host (No in S230), the variable interface circuit can operate in the termination operation mode (S260). By way of example, the variable interface circuit 1338c can support communication of an end device in an end operation mode based on a response from the main processor 1101. [

FIG. 18 is a block diagram illustrating an exemplary configuration associated with the storage devices 1300a, 1300b, and 1300c of FIG.

In some embodiments, the storage devices 1300a, 1300b, and 1300c may include storage devices 1304a, 1301b, 1301c, 1304d, and 1304e. Similar to the exemplary configuration of FIG. 5, the storage devices 1304a, 1301b, and 1301c may be connected to one another to communicate in a peer-to-peer manner.

As an example, peer-to-peer manager 1357a may include three downstream ports. Two of the three downstream ports may be connected to the storage controllers 1331a and 1331b, respectively. The other of the three downstream ports may be connected to the storage controller 1331d of the storage device 1304d.

Similar to the connection between the storage devices 1304a, 1301b, 1301c, the storage devices 1304a, 1304d, 1304e can be connected to one another and communicate in a peer-to-peer manner. The peer-to-peer manager 1350d may be connected to the storage controllers 1331d and 1331e via two downstream ports. The peer-to-peer manager 1350e may be coupled to the storage controller 1331e and the main processor 1101 via two downstream ports.

The peer-to-peer managers 1357a, 1350b, 1350c, 1350d, and 1350e can manage the data flow and can distribute and perform the entire operations requested by the main processor 1101. [ It will be appreciated that the connection between storage devices may vary or be modified depending on the number of downstream ports included in each peer-to-peer manager. Such changes or modifications may be similarly applied to the exemplary configurations described with reference to Figs.

19 is a conceptual diagram illustrating an exemplary implementation associated with the electronic system 1000 of FIG.

By way of example, the electronic system 1000 may be implemented as a server 1000c. The storage devices 1300a, 1300b, and 1300c may be implemented as a dual-port structure and may be connected to or mounted to the server 1000c.

The connector 1390a of the storage apparatus 1300a can be connected to the backplane 1007 through the cable P21d and the connector 1007a. Figure 19 shows the connection through cable P21d, but in some embodiments connector 1390a may be directly connected to connector 1007a.

The connector 1395a of the storage apparatus 1300a can be connected to the connector 1390b of the storage apparatus 1300b via the cable P22d. The connector 1395b of the storage apparatus 1300b can be connected to the connector 1390c of the storage apparatus 1300c via the cable P24d. The connector 1395c of the storage apparatus 1300c may be connected to the backplane 1007 through the cable P27d and the connector 1007c and may not be connected to the backplane 1007 in some cases.

In this manner, the storage devices 1300a, 1300b, and 1300c can communicate with each other in a peer-to-peer manner. The peer-to-peer connection between the storage devices 1300a, 1300b, and 1300c can be completely disconnected from the backplane 1007. Thus, the main processor 1101 may not intervene in communication between the storage devices 1300a, 1300b, and 1300c.

The main processor 1101 may be connected to the backplane 1007 via conductive lines L21 and thus may communicate with the storage device 1300a. The main processor 1101 can communicate with the storage device 1300c via the conductive lines L27 and in some cases the conductive lines L27 may not be provided.

The foregoing description is intended to provide exemplary configurations and operations for implementing the invention. The technical spirit of the present invention will include implementations not only described above, but also implementations that can be obtained by simply modifying or modifying the above embodiments. In addition, the technical spirit of the present invention will also include implementations that can be achieved by easily modifying or modifying the embodiments described above.

1000: Electronic system

Claims (20)

In a storage device,
An FPGA (Field Programmable Gate Array) board connected to the first port of the storage device; And
A storage controller including a first interface circuit coupled to the FPGA board and a second interface circuit coupled to a second port of the storage device,
Wherein at least one port of the first port and the second port is configured to be connected to another storage device outside the storage device,
When the first port is connected to the other storage device, the FPGA board transmits data in a peer-to-peer manner between the storage controller and the other storage device without intervention of a host A storage device configured to provide a path for the storage device. The method according to claim 1,
The storage device includes a dual-port solid-state drive (SSD) configured to receive or output data through the first port and the second port,
Wherein the FPGA board is implemented separately from the storage controller within the set of dual-port SSDs. The method according to claim 1,
Wherein the port of the first port and the port of the second port that are not connected to the other storage device are connected to the host. The method according to claim 1,
When the first port is connected to the other storage device,
Receive a request directed to the storage device and the other storage device via the second port and the second interface circuit,
And in response to the request, perform a requested operation on the storage device and exchange data associated with the requested operation for the other storage device via the first interface circuit with the FPGA board. 5. The method of claim 4,
The FPGA board is further configured to output data to the other storage device via the first port or receive data from the other storage device via the first port based on the data exchanged with the storage controller Storage device. The method according to claim 1,
Wherein the FPGA board comprises an internal root complex circuit configured to manage data flow between the storage controller and the first port. The method according to claim 1,
The FPGA board is configured to process data received from the storage controller to generate data to be output through the first port or to process data received through the first port to generate data to be provided to the storage controller A storage device comprising an arithmetic logic circuit. In a storage device,
A storage controller including a first interface circuit coupled to a first port of the storage device and a second interface circuit coupled to a second port of the storage device; And
And a memory device configured to store or output data under the control of the storage controller,
The first interface circuit operates in an operation mode selected from a plurality of operation modes based on whether the first port is connected to another device outside the storage device and the type of the other device connected to the first port Respectively,
The storage controller is configured to exchange data in a peer-to-peer manner with the other storage device via the first port without intervention of a host, when the first port is connected to another storage device external to the storage device Storage device. 9. The method of claim 8,
Wherein the plurality of operation modes comprises a first mode of operation associated with operation of an endpoint device and a second mode of operation associated with communication with the other storage device. 10. The method of claim 9,
Wherein the first interface circuit operates in the second mode of operation when the first port is connected to the other storage device and the storage controller is connected to the other storage device via the first interface circuit and the first port And to output data or receive data from the other storage device via the first port and the first interface circuit. 10. The method of claim 9,
Wherein the first interface circuit operates in the first mode of operation when the first port is coupled to the host and the storage controller outputs data to the host via the first interface circuit and the first port, And receive data from the host through the first port and the first interface circuit. 10. The method of claim 9,
Wherein the first interface circuit operates in the first operation mode or is turned off when the first port is not connected to another device outside the storage device. 9. The method of claim 8,
When the first port is connected to the other storage device,
Receive a request directed to the storage device and the other storage device via the second port and the second interface circuit,
In response to the request, perform a requested operation on the storage device and output or receive data associated with the requested operation on the other storage device via the first interface circuit and the first port Storage device. 9. The method of claim 8,
The storage controller may process data received through the first port to generate data to be output through the second port or to process data received through the second port to output data to be output through the first port Wherein the storage device further comprises an embedded FPGA configured to create the storage device. In a storage device,
A storage controller between a first port of the storage device and a second port of the storage device; And
And an arithmetic logic circuit configured to perform a processing operation based on data received from the storage controller or the second port to generate processed data,
Wherein the storage device is configured to output the processed data to the another storage device via the first port without intervention of a host when the first port is connected to another storage device outside the storage device. 16. The method of claim 15,
Wherein the processing operation performed by the arithmetic logic circuit includes a first portion of the overall operation requested by the host,
Wherein the storage device is further configured to output the processed data to the other storage device such that the other storage device performs a second portion of the overall operation based on the processed data,
Wherein the second portion does not overlap with the first portion. 16. The method of claim 15,
Wherein the processing operation comprises: an operation to monitor information associated with the received data; a Redundant Array of Independent Disks (RAID) -based operation based on the received data; and a regex search operation based on the received data Lt; / RTI > In a storage device,
A storage controller between a first port of the storage device and a second port of the storage device; And
And a memory device configured to store or output data under the control of the storage controller,
Wherein when the first port is connected to another storage device outside the storage device, the storage device is configured to store, based on at least one of the first data stored in the memory device and the second data received via the second port And to output the generated third data to the other storage device via the first port without involvement of a host. A first storage device including a first port and a second port; And
And a second storage device including a third port,
Wherein the second port is coupled to the third port and the first storage device is configured to communicate with the second storage device via the second port and the third port without the intervention of a host,
Wherein the first storage device is further configured to output third data via the second port based on at least one of the first data received via the first port and the second data stored in the first storage device And,
The second storage device is configured to generate fifth data based on at least one of the third data received via the third port and the fourth data stored in the second storage device,
And the result of the operation corresponding to the request of the host is provided to the host based on the fifth data. 20. The method of claim 19,
Wherein all operations requested by the host to obtain the operation result are performed in a distributed manner on the first storage device and the second storage device.

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