KR20190031869A - Scan Driver and Light Emitting Display Device Having the same - Google Patents

Abstract

The present invention provides a scan driver capable of implementing a narrow bezel of an electroluminescent display device. The scan driver comprises: a first output buffer unit outputting a first light emission control signal since the first output buffer unit is turned on based on a potential of a Q node; and a second output buffer unit composed of a double buffer. The double buffer includes two transistors. The two transistors are individually connected to gate electrodes of nodes different from each other, and the two transistors output the same second light emission control signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a scan driver and a light emitting display device,

The present invention relates to a scan driver and an electroluminescent display device including the scan driver.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. As a result, various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a quantum dot display device are increasingly used.

The display apparatus includes a display panel including a plurality of sub pixels, a driver for driving the display panel, and a power supply unit for supplying power to the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data voltage to the display panel.

In the electroluminescent display device, when a scan signal, a data voltage, or the like is supplied to the subpixels, the light emitting diodes of the selected subpixel emit light to display an image. Light emitting diodes are implemented on organic basis or on inorganic basis.

The scan driver for outputting a scan signal may include not only an integrated circuit but also a thin film transistor process and a built-in display panel formed on a display panel in a gate in panel (GIP) form.

Accordingly, the scan driver in the form of a gate-in panel may be advantageous in realizing a Narrow Bezel on a display panel. However, in order to improve the driving characteristics of the transistors of the scan driver, the size of the transistors must be increased. Accordingly, the inventors of the present invention have recognized that there arises a problem that it is difficult to realize a narrow bezel.

Accordingly, the inventors of the present invention have been able to realize a narrow bezel and have conducted various experiments to improve the driving characteristics of the display device. The inventors of the present invention have invented a new scan driver and an electroluminescent display device capable of improving driving capability of a transistor and maintaining a stable output characteristic through various experiments and realizing a narrow bezel implementation.

The present invention provides a scan driver capable of improving the driving capability of a transistor and maintaining a stable output characteristic and implementing a narrow bezel, and an electroluminescent display device including the same.

The present invention includes a first output buffer unit that is turned on based on a potential of a Q node to output a first emission control signal, and a second output buffer unit that is formed of a double buffer, and the double buffer includes two transistors And the two transistors provide a scan driver in which gate electrodes are connected to different nodes and output the same second emission control signal.

The QB2 node controller controls the QB2 node based on the potential of the Q node. The QB2 node controller controls the QB2 node based on the potential of the QB2 node. The QB2 node controls the QB2 node based on the start signal transmitted through the start signal line. A first output buffer unit that is turned on based on the potential of the Q node to output a first emission control signal and a second emission buffer unit that is turned on based on the potentials of the other nodes to output a second emission control signal And a second output buffer portion having at least two transistors.

According to another aspect of the present invention, there is provided a display device including a display panel for displaying an image, a scan driver including scan signal generating circuits for outputting scan signals to the display panel, and emission signal generating circuits for outputting emission signals to the display panel, (M is a positive integer) emission signal generation circuit of the generation circuits includes a first output buffer unit that is turned on based on the potential of the Q node and outputs a first emission control signal, and a second output buffer unit that is formed of a double buffer 2 output buffers, the double buffer includes two transistors, and the two transistors are connected to gate electrodes at different nodes and output the same second emission control signal.

According to another aspect of the present invention, there is provided a display device including a display panel for displaying an image, a scan driver including scan signal generating circuits for outputting scan signals to the display panel, and emission signal generating circuits for outputting emission signals to the display panel, A m-th (m is a positive integer) emission signal generating circuit of the generating circuits includes a Q-node controller for controlling a Q-node based on a start signal transmitted through a start signal line, a QB2 node based on a potential of the Q- A QB1 node control unit for controlling the QB1 node based on the potential of the QB2 node, a first output buffer unit for turning on the Q node and outputting the first emission control signal based on the potential of the Q node, And at least two transistors are turned on based on the potentials of the different nodes to output a second emission control signal, ≪ / RTI >

The details of other embodiments are included in the detailed description and drawings.

The present invention includes a scan driver capable of improving driving capability of a transistor and maintaining stable output characteristics, thereby realizing a narrow bezel of an electroluminescent display device including a scan driver.

In addition, since the present invention realizes a scan driver including an output buffer implemented as a double buffer, even if a threshold voltage of a transistor operating as an output buffer shifts, The driving reliability of the driving unit can be improved.

Further, the scan driver of the present invention includes a shift register-based emission signal generation circuit, so that a signal delay due to a load of a clock signal line can be eliminated.

1 is a block diagram of an organic light emitting display according to an embodiment of the present invention;
Figure 2 is a block diagram of the subpixel shown in Figure 1;
FIG. 3 is an exemplary layout of the scan driver shown in FIG. 1. FIG.
4 is a block diagram of a scan driver arranged on one side of a display panel according to an embodiment of the present invention;
FIG. 5 is a block diagram of the light emitting signal generating circuits of FIG. 4;
6 is a block diagram showing a configuration of an mth light emitting signal generation circuit according to an experimental example;
7 is a circuit configuration diagram showing an mth light emission signal generation circuit according to an experimental example;
Figs. 8 and 9 are circuit diagrams and driving waveform diagrams for explaining operational characteristics related to the inverter circuit portion of Fig. 7; Fig.
10 is a block diagram showing a configuration of an mth light emitting signal generation circuit according to the embodiment of the present invention;
11 is a circuit configuration diagram showing the output buffer unit of Fig.
12 is a circuit configuration diagram showing the mth light emitting signal generation circuit according to the embodiment of the present invention in detail.
13 is a drive waveform diagram of an mth light emission signal generation circuit according to the embodiment of the present invention;
Figs. 14 and 15 are circuit diagrams and driving waveform diagrams for explaining operation characteristics related to the QB2 node controller of Fig. 12; Fig.
16 is a voltage waveform diagram measured from the QB1 node and the QB2 node of the mth light emitting signal generation circuit according to the embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The electroluminescent display device described below may be implemented as a television, a video player, a personal computer (PC), a home theater, a smart phone, a virtual reality device (VR), or the like. The electroluminescent display device described below will be described with reference to an organic electroluminescent display device implemented based on an organic light emitting diode. However, the electroluminescent display device described below is not limited to this, and may be implemented based on an inorganic light emitting diode.

In addition, the organic light emitting display device described below is implemented based on one or more of a P-type transistor or an N-type transistor. In the case of the P-type transistor and the N-type transistor, since the positions of the source electrode and the drain electrode may be different depending on the type except the gate electrode, they are referred to as a first electrode and a second electrode.

FIG. 1 is a block diagram of an organic light emitting display according to an embodiment of the present invention, and FIG. 2 is a block diagram of the subpixel shown in FIG. 1. Referring to FIG.

1, an organic light emitting display includes an image processing unit 110, a timing control unit 120, a data driving unit 140, a scan driving unit 130, a display panel 150, and a power supply unit 180 .

The image processing unit 110 outputs driving signals for driving various devices in addition to image data supplied from the outside. The driving signal output from the image processing unit 110 may include a data enable signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal.

The timing control unit 120 receives a driving signal and the like from the image processing unit 110 in addition to the video data. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140, .

The data driver 140 outputs the data voltage in response to the data timing control signal DDC supplied from the timing controller 120. [ The data driver 140 samples and latches the digital data signal DATA supplied from the timing controller 120, and converts the data signal into an analog data voltage based on the gamma reference voltage. The data driver 140 outputs a data voltage through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC (Integrated Circuit).

The scan driver 130 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 outputs scan signals and the like through the scan lines GL1 to GLm. The scan driver 130 may include a display panel built in a display panel 150 in the form of a gate in panel (GIP) together with a thin film transistor process.

The power supply unit 180 outputs the first voltage, the second voltage, and the like. The first voltage and the second voltage output from the power supply unit 180 are supplied to the display panel 150. The first voltage is supplied to the display panel 150 through the first power line EVDD and the second voltage is supplied to the display panel 150 through the second power line EVSS. The voltage output from the power supply unit 180 may be used in the data driver 140 or the scan driver 130.

The display panel 150 displays an image corresponding to the data voltage and the scan signal supplied from the data driver 140 and the scan driver 130 and the power supplied from the power supplier 180. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels SP may include red subpixels, green subpixels, and blue subpixels, or may include white subpixels, red subpixels, green subpixels, and blue subpixels. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one subpixel SP is connected to the scan line GL1, the data line DL1, the first power line EVDD, and the second power line EVSS. The number of transistors and capacitors as well as the driving method of the sub-pixel SP are determined according to the configuration of the pixel circuit.

The subpixel SP includes an organic light emitting diode, a switching transistor, a driving transistor, a light emitting control transistor, a capacitor, and the like. The switching transistor serves to transfer the data voltage to the capacitor in response to the scan signal. The capacitor serves to transfer the data voltage to the gate electrode of the driving transistor. The driving transistor generates a driving current capable of driving the organic light emitting diode in accordance with the data voltage transferred from the capacitor. The emission control transistor controls the emission time of the organic light emitting diode in response to the emission control signal.

The number of transistors and capacitors to compensate for transistor deterioration such as 3T1C, 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, And can be variously implemented. In FIG. 2, only one scan line GL1 is shown for the sake of explanation, and it may be composed of I (I is an integer of 2 or more) depending on the number of transistors included in the subpixel and compensation scheme.

FIG. 3 is a diagram illustrating the arrangement of the scan driver shown in FIG. 1, FIG. 4 is a block diagram of a scan driver disposed on one side of the display panel, and FIG. 5 is a block diagram of the emission signal generating circuits of FIG.

3, the display panel 150 includes a display area AA for displaying an image based on sub-pixels SP, a non-display area for displaying a signal line, a driving circuit, (NA).

The scan driver 130 is formed in a non-display area NA of the display panel 150 in a gate in panel manner. The scan driver 130 may be disposed on each of left and right sides of the display panel 150, or may be disposed on only one side of the display panel 150.

4, the scan driver 130 includes scan signal generating circuits SRD1 to SRD [m] for outputting scan signals and emission signal generating circuits EMD1 to EMD [m ]). The scan signal generating circuits SRD1 to SRD [m] are connected to the first to m-th scan lines SCAN1 to SCAN [m]. The emission signal generating circuits EMD1 to EMD [m] are connected to the first to mth emission signal lines EM1 to EM [m].

The scan signal generating circuits SRD1 to SRD [m] and the emission signal generating circuits EMD1 to EMD [m] are composed of a plurality of stages for outputting signals corresponding to the scan lines of the display panel. The first scan signal generation circuit SRD1 and the first emission signal generation circuit EMD1 may be defined as a first stage. The first stage SRD1 or EMD1 outputs a first scan signal for driving the first horizontal line of the display panel 150 and a first emission control signal. The second scan signal generation circuit SRD2 and the second emission signal generation circuit EMD2 may be defined as a second stage. The second stage SRD2 or EMD2 outputs a second scan signal for driving the second horizontal line of the display panel 150 and a second emission control signal.

5, the first to mth emission signal generating circuits EMD1 to EMD [m] are connected to the first clock signal CLKa, the second clock signal CLKb, and the start signals VST and Start Pulse And the like, respectively. The first to mth emission signal generating circuits EMD1 to EMD [m] output the first to mth emission signals through the first to mth emission signal lines EM1 to EM [m], respectively.

The first to mth emission signal generating circuits EMD1 to EMD [m] have a structure in which signals at the previous stage are connected to each stage so as to be used at the subsequent stage. The first emission signal generation circuit EMD1 receives the start signal VST through the start signal terminal VP. The remaining second light emission signal generating circuits EMD2 to EMD [m] generate first to m-1 carry signals CRY1 to CRY1 generated from the light emission signal generating circuit of their previous stage, CRY [m-1]) through the start signal terminal VP.

Therefore, the first emission signal generation circuit EMD1 starts operation based on the start signal VST applied to the start signal terminal VP, whereas the second emission signal generation circuit EMD2 starts the operation based on the start signal VST applied to the start signal terminal VP. And starts the operation based on the first carry signal CRY1 outputted from the first carry signal EMD1. Since the carry signal can use a signal generated from the light emission signal generation circuit located at the front end or the front end in consideration of the input / output timing of the signal, a signal generated from the light emission signal generation circuit of K (K is an integer of one or more) Can be defined.

As described above, the scan driver (or the built-in scan driver) in the form of a gate-in-panel has many advantages over the scan driver provided in the form of an integrated circuit. However, in addition to the narrow bezel on the display panel, And to maintain stable output characteristics.

Hereinafter, circuits for implementing the scan driver will be described. Hereinafter, an example in which the emission signal generation circuit is implemented based on a P-type transistor will be described as an example, but the present invention is not limited thereto.

FIG. 6 is a block diagram showing the configuration of the mth light emitting signal generating circuit according to the experimental example, FIG. 7 is a circuit configuration diagram showing the mth light emitting signal generating circuit according to the experimental example, and FIG. 8 and FIG. Circuit configurations and drive waveforms for explaining operation characteristics related to the inverter circuit portion.

6, the mth light emitting signal generation circuit according to the experimental example includes a Q node control unit 133, a bootstrap inverter circuit unit 135, a QB1 node control unit 137, a first output buffer unit T6, A second output buffer unit T7, and the like. The main configuration of the mth emission signal generation circuit according to the experimental example will be briefly described below.

The Q node controller 133 controls the Q node Q based on the start signal transmitted through the start signal line EVST. The bootstrap inverter circuit section 135 controls the QB2 node QB2 based on the potential of the Q node (Q). The QB1 node controller 137 controls the QB1 node QB1 based on the potential of the QB2 node QB2. The first output buffer unit T6 is turned on based on the potential of the Q node Q and outputs a logic low light emission control signal through an output terminal EMO of the light emission signal generation circuit. The second output buffer unit T7 is turned on based on the potential of the QB1 node QB1 and outputs a logic high light emission control signal through the output terminal EMO of the light emitting signal generating circuit.

6 and 7, the mth light emitting signal generating circuit according to the experimental example includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, A sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor CQ, 2 capacitors CQP and a third capacitor CQB.

The bootstrap inverter circuit section 135 includes a fourth transistor T4, an eighth transistor T8, a tenth transistor T10 and a second capacitor CQP. The bootstrap inverter circuit section 135 inverts and outputs the input signal or potential based on the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the second capacitor CQP. The rest except for the elements included in the bootstrap inverter circuit section 135 are connected to the Q node control section 133, the QB1 node control section 137, the first output buffer section T6, the second output buffer section T7, .

8 and 9, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the second capacitor CQP included in the bootstrap inverter circuit portion 135 of FIG. ), The following explanation is supplemented.

The fourth transistor T4 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the low potential voltage line VEL, and a second electrode connected to the QP node QP. The fourth transistor T4 is turned on in response to the second clock signal Eclk2 transmitted through the second clock signal line ECLK2. When the fourth transistor T4 is turned on, the low potential voltage Vel transmitted through the low potential voltage line VEL is applied to the QP node QP.

The tenth transistor T10 has a gate electrode connected to the Q node Q, a first electrode connected to the second clock signal line ECLK2, and a second electrode connected to the QP node QP. The tenth transistor T10 is turned on in response to the potential q of the Q node Q of the logic low. When the tenth transistor T10 is turned on, the second clock signal Eclk2, which is transmitted through the second clock signal line ECLK2, is applied to the QP node QP.

The eighth transistor T8 has a gate electrode connected to the QP node QP, a first electrode connected to the first clock signal line ECLK1, and a second electrode connected to the QB2 node QB2. The eighth transistor T8 is turned on in response to the potential Qp of the QP node QP of the logic low. When the eighth transistor T8 is turned on, the first clock signal Eclk1 transmitted through the first clock signal line ECLK1 is applied to the QB2 node QB2.

The second capacitor CQP is connected at one end to the QP node QP and at the other end to the QB2 node QB2. The second capacitor CQP serves as a bootstrap capacitor for bootstrapping the potential of one of the two terminals of the second capacitor CQP.

The bootstrap inverter circuit portion of the experimental example receives the potential (q) of the Q node (Q) as an input. Therefore, the operation and output characteristics when the potential q of the Q node Q is logic low and logic high are different, which will be described below.

The tenth transistor T10 is maintained in a turned-on state during a period in which a potential of a logic low is formed in the Q node (Q). During this period, the fourth transistor T4 is turned on and off by the second clock signal Eclk2, which changes from logic high to logic low.

As the turn-on and turn-off operations of the fourth transistor T4 are repeated in the turn-on state of the tenth transistor T10, the QP node QP is turned on at a logic high and a logic low in the same manner as the second clock signal Eclk2 . On the other hand, the potential of the logic high is always maintained by the turn-on / turn-off operation of the eighth transistor T8 in the QB2 node QB2.

The tenth transistor T10 is maintained in the turned-off state during a period in which the potential of the logic high is formed in the Q node (Q). During this period, the fourth transistor T4 is turned on and off by the second clock signal Eclk2, which changes from logic high to logic low.

As the turn-on and turn-off operations of the fourth transistor T4 are repeated in the state that the tenth transistor T10 is turned off, the level of the low potential voltage Vel is maintained in the QP node QP, CQP, the voltage may be lower than the low potential voltage through the fourth transistor T4. In the QB2 node QB2, the potential changes to a logic high and a logic low in the same manner as the first clock signal Eclk1 by the turn-on operation of the eighth transistor T8. In this case, since the QB2 node QB2 is subjected to the low potential voltage bootstrapping effect by the second capacitor CQP, the voltage of the QP node QP becomes lower. Thus, the first clock signal Eclk1 may be transmitted to the QB2 node QB2 through the eighth transistor T8.

Thus, the experimental example reverses the potential (q) of the Q node (Q) like an inverter circuit to form a potential to be applied to the QB2 node (QB2). And causes the potential Qb2 of the QB2 node QB2 to be transferred to the QB1 node QB1 through the ninth transistor T9 turned on. The circuit is implemented so that the logic high output of the second output buffer unit T7 is made based on the potential formed in the QB1 node QB1.

FIG. 10 is a block diagram showing the configuration of the mth light emitting signal generating circuit according to the embodiment, FIG. 11 is a circuit configuration diagram showing the output buffer unit of FIG. 10, and FIG. Fig. 13 is a driving waveform diagram of the m-th light emitting signal generating circuit according to the embodiment. Fig. 14 and Fig. 15 are circuit diagrams for explaining the operating characteristics related to the QB2 node controller in Fig. 12, 16 is a voltage waveform diagram measured from the node QB1 and the node QB2 of the mth light emitting signal generation circuit according to the embodiment.

10, the mth light emitting signal generation circuit according to the embodiment includes a Q node control unit 133, a QB2 node control unit 134, a QB1 node control unit 137, a first output buffer unit T6, 2 output buffer units T7a and T7b, and the like. The main configuration of the mth light emitting signal generating circuit according to the embodiment will be briefly described as follows.

The Q node controller 133 controls the Q node Q based on the start signal transmitted through the start signal line EVST. The QB2 node control unit 134 controls the QB2 node QB2 based on the potential of the (m-1) th QB2 node QB2 [m-1]. The QB1 node controller 137 controls the QB1 node QB1 based on the potential of the QB2 node QB2. The (m-1) th QB2 node (QB2 [m-1]) is the QB2 node of the (m-1) th emission signal generating circuit located at the previous stage of the mth light emitting signal generating circuit.

The first output buffer unit T6 is turned on based on the potential of the Q node Q and outputs a logic low light emission control signal (first light emission control signal) through the output terminal EMO of the mth light emission signal generation circuit . The second output buffer units T7a and T7b are turned on based on the potentials of the different nodes and output a logic high light emission control signal (second light emission control signal) through the output terminal EMO of the mth light emission signal generation circuit .

The second output buffer units T7a and T7b are composed of a pair of transistors T7a and T7b. The gate electrodes of the pair of transistors T7a and T7b are connected to different nodes, but the first electrode has a parallel connection structure in which the first electrodes are connected to each other and the second electrode is connected to the second electrodes. The two transistors T7a and T7b constituting a pair may be defined as a double buffer because they output the same signal although they are turned on corresponding to the potentials of the different nodes.

11, the second output buffer units T7a and T7b according to the embodiment include a pair of the second-1 output buffer units T7a and the second-2 output buffer units T7a and T7b connected to different nodes T7b. The 2-1 output buffer unit T7a operates in response to the potential of the QB1 node QB1. The 2-2 output buffer unit T7b operates in correspondence with the potential of the QB2 node QB2. A description related to the effect that a pair of the second-1 output buffer unit T7a and the second-2 output buffer unit T7b are connected to different nodes will be described below.

12 and 13, the mth light emitting signal generating circuit according to the embodiment includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, A seventh transistor T7a, a seventh transistor T7b, an eighth transistor T8, a ninth transistor T9, a tenth transistor T9, a sixth transistor T6, T10, a first capacitor CQ, a second capacitor CQP, and a third capacitor CQB.

The first transistor T1 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the start signal line EVST, and a second electrode connected to the Q node Q. The first transistor T1 is turned on based on the second clock signal Eclk2 transmitted through the second clock signal line ECLK2. When the first transistor (T1) is turned on, a start signal is applied to the Q node (Q). At this time, the Q node Q is charged by the start signal.

The second transistor T2 has a gate electrode connected to the Q node Q, a first electrode connected to the first clock signal line ECLK1, and a second electrode connected to one end of the first capacitor CQ. The second transistor T2 is turned on based on the potential q of the Q node Q. When the second transistor T2 is turned on, the first clock signal Eclk1 is applied to one end of the first capacitor CQ. In this case, the first capacitor CQ is charged with the voltage for keeping the Q node Q in a specific state.

The third transistor T3 has a gate electrode connected to the QB2 node QB2, a first electrode connected to the Q node Q, and a second electrode connected to the high potential voltage line VEH. The third transistor T3 is turned on based on the potential Qb2 of the QB2 node QB2. When the third transistor T3 is turned on, a high potential voltage is applied to the Q node Q. In this case, the Q node Q is discharged by the high potential voltage.

The fourth transistor T4 has a gate electrode connected to the second clock signal line ECLK2 and a first electrode connected to the m-1 QB2 node QB2 [m-1] and a second electrode connected to the QP node QP. Electrodes are connected. The fourth transistor T4 is turned on based on the second clock signal Eclk2 transmitted through the second clock signal line ECLK2. When the fourth transistor T4 is turned on, the potential Qb2 [m-1] of the m-1 QB2 node QB2 [m-1] is applied to the QP node QP. The (m-1) th QB2 node (QB2 [m-1]) is the QB2 node of the (m-1) th emission signal generating circuit located at the previous stage of the mth light emitting signal generating circuit.

The fifth transistor T5 has a gate electrode connected to the Q node Q, a first electrode connected to the QB2 node QB2, and a second electrode connected to the high potential voltage line VEH. The fifth transistor T5 is turned on based on the potential q of the Q node Q. When the fifth transistor T5 is turned on, a high potential voltage is applied to the QB2 node QB2. At this time, the QB2 node QB2 is discharged by the high potential voltage.

The sixth transistor T6 has a gate electrode connected to the Q node Q, a first electrode connected to the low potential voltage line VEL, and a second electrode connected to the output terminal EMO of the mth light emitting signal generating circuit . The sixth transistor T6 is turned on based on the potential q of the Q node Q. When the sixth transistor T6 is turned on, a low potential voltage is applied to the output terminal EMO of the mth light emission signal generating circuit. At this time, the mth emission signal generating circuit outputs a logic low emission control signal through its output terminal EMO.

The seventh transistor T7a has a gate electrode connected to the QB1 node QB1 and a first electrode connected to the output terminal EMO of the mth light emitting signal generating circuit and a second electrode connected to the high voltage line VEH . The seventh transistor T7a is turned on based on the potential of the QB1 node QB1. When the seventh transistor T7a is turned on, a high potential voltage is applied to the output terminal EMO of the mth light emission signal generating circuit. In this case, the mth emission signal generation circuit outputs a logic high emission control signal through the output stage EMO.

The seventh transistor T7b has a gate electrode connected to the QB2 node QB2 and a first electrode connected to the output terminal EMO of the mth light emitting signal generating circuit and a second electrode connected to the high potential voltage line VEH . The seventh to eighth transistor T7b is turned on based on the potential of the QB2 node QB2. When the seventh transistor T7b is turned on, a high potential voltage is applied to the output terminal EMO of the mth light emission signal generating circuit. At this time, the mth emission signal generating circuit outputs a logic high emission control signal through its output terminal EMO.

The eighth transistor T8 has a gate electrode connected to the QP node QP, a first electrode connected to the first clock signal line ECLK1, and a second electrode connected to the QB2 node QB2. The eighth transistor T8 is turned on based on the potential Qb2 [m-1] of the m-1 QB2 node QB2 [m-1] transferred through the fourth transistor T4. When the eighth transistor T8 is turned on, the first clock signal Eclk1 is applied to the QB2 node QB2.

The ninth transistor T9 has a gate electrode connected to the first clock signal line ECLK1, a first electrode connected to the QB2 node QB2, and a second electrode connected to the QB1 node QB1. The ninth transistor T9 is turned on based on the first clock signal Eclk1 transmitted through the first clock signal line ECLK1. When the ninth transistor T9 is turned on, the QB2 node QB2 and the QB1 node QB1 are rendered conductive. In this case, the QB1 node QB1 is affected by the potential Qb2 formed at the QB2 node QB2.

The tenth transistor T10 has a gate electrode connected to the Q node Q, a first electrode connected to the QB1 node QB1, and a second electrode connected to the high potential voltage line VEH. The tenth transistor T10 is turned on based on the potential of the Q node Q. When the tenth transistor T10 is turned on, a high potential voltage is applied to the QB1 node QB1. In this case, the QB1 node QB1 is discharged by the high potential voltage.

The first capacitor CQ has one end connected to the second electrode of the second transistor T2 and the other end connected to the first electrode of the Q node Q and the third transistor T3. The first capacitor CQ serves to maintain the potential of the Q node Q at a logic high level after the emission control signal of the logic low is outputted.

The second capacitor CQP is connected at one end to the QP node QP and at the other end to the QB2 node QB2. The second capacitor CQP keeps the potential of the logic low of the first clock signal Eclk1 low based on the potential Qb2 [m-1] of the m-1 QB2 node QB2 [m-1] It plays a role.

The third capacitor CQB is connected at one end to the QB1 node QB1 and at the other end to the high voltage line VEH. The third capacitor CQB serves to keep the potential of the QB1 node QB1 at a logic high level after the emission control signal of the logic high is outputted.

The Q node controller Q Control includes a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor CQ. The QB1 node control unit QB1 Control includes a fifth transistor T5, a tenth transistor T10 and a third capacitor CQB. The QB2 node control unit QB2 Control includes a fourth transistor T4, an eighth transistor T8, and a second capacitor CQP. The first output buffer unit T6 includes a sixth transistor T6. The second output buffer units T7a and T7b include a seventh transistor T7a and a seventh transistor T7b.

Hereinafter, with reference to FIG. 14 to FIG. 16, supplements the description related to the fourth transistor T4, the eighth transistor T8, and the second capacitor CQP included in the QB2 node control unit 134 of FIG. 12 As follows.

The QB2 node controller 134 of the embodiment receives as input the potential Qb2 [m-1] of the (m-1) th QB2 node QB2 [m-1]. Therefore, the operation and output characteristics when the potential Qb2 [m-1] of the (m-1) th QB2 node QB2 [m-1] are logic high and logic low are different from each other .

The fourth transistor T4 during the period in which the logic high potential Qb2 [m-1] is formed in the m-1 QB2 node QB2 [m-1] The turn-on and turn-off operations are repeated by the control signal Eclk2.

The logic high potential Qb2 [m-1] of the (m-1) th QB2 node QB2 [m-1] is applied to the QP node QP when the fourth transistor T4 is turned on. During this period, the eighth transistor T8 is turned off by the logic high potential Qb2 [m-1] of the (m-1) th QB2 node QB2 [m-1]. In this case, since the fifth transistor T5 connected to the QB2 node QB2 together with the eighth transistor T8 is turned on by the potential q of the logic low of the Q node Q, Lt; / RTI > remains in a logic high state.

The eighth transistor T8 is connected to the (m-1) th QB2 node QB2 [m-1] during the period in which the logic low potential Qb2 [m-1] is formed in the (m- 1] of the logic low of Qb2 [m-1]. As the eighth transistor T8 is turned on, the first clock signal Eclk1 is applied to the QB2 node QB2 and the QB2 node QB2 synchronized with the first clock signal Eclk1 is connected to the QP node QP2, Lt; RTI ID = 0.0 > logiclow < / RTI > In this case, since the fifth transistor T5 connected to the QB2 node QB2 together with the eighth transistor T8 is turned off by the potential q of the logic high of the Q node Q, the QB2 node QB2 Is held in a logic low state. Since the QB2 node QB2 is subjected to the low potential voltage bootstrapping effect by the second capacitor CQP during the above operation, the potential of the logic low of the second clock signal Eclk2 is more reliably maintained.

As described above, the embodiment includes the QB2 node controller 134 which can move the potential (Qb2 [m-1]) of the (m-1) th QB2 node QB2 [m-1] like a shift register and apply it to the QB2 node QB2. . The embodiment allows the logic high output to be made through the second-1 output buffer unit T7a based on the potential Qb1 of the QB1 node QB1 and the potential Qb2 of the QB2 node QB2 based on the potential Qb1 of the QB1 node QB1 And a logic high output is performed through the second-2 output buffer unit T7b.

16, since the potential Qb1 of the QB1 node QB1 is transferred from the QB2 node QB2 by the turned-on ninth transistor T9, the potential drop by the ninth transistor T9 is present do. However, since the potential Qb2 of the QB2 node QB2 is on the QB2 node QB2 without passing through the turned-on ninth transistor T9, there is a potential drop by the potential Qb1 of the QB1 node QB1 I never do that. Therefore, the second-2 output buffer unit T7b operates based on the potential having no drop compared to the second-1 output buffer unit T7a. Therefore, the embodiment can be compensated by the output of the second-2 output buffer unit T7b even if the output characteristic of the second-1 output buffer unit T7a is lowered due to the influence of the potential drop.

The embodiment comprises second output buffer units T7a and T7b based on at least two seventh and seventh transistors T7a and T7b. The second output buffer unit T7 according to the experimental example has a size (width, length, and WL value) of the second output buffer unit T7 for stable operation such as outputting and holding a logic high signal It can be somewhat large. However, since the second output buffer units T7a and T7b according to the embodiment are implemented with two transistors connected in parallel, the sizes of the second output buffer units T7a and T7b are the same as those of the second output buffer unit T7) (width, length, and WL value).

The embodiment can lower the size (also called width and length, WL value) of at least two of the seventh and seventh transistors T7a and T7b compared to the experimental example. In this case, the size of the second output buffer units T7a and T7b may be reduced to provide an advantage of Narrow Bezel implementation of the display panel. It is also possible to eliminate the risk of margin reduction due to the shift of the threshold voltage of the second output buffer units T7a and T7b so that the threshold voltage shift Vth Shift in one of the second output buffer units T7a and T7b ) Can be complemented and compensated by another operation.

In addition, as in the experimental example, the light emitting signal generation circuit based on the inverter circuit repeats the turn-on and turn-off states of the fourth transistor T4 corresponding to the second clock signal, The second capacitor CQP is charged and discharged according to the constant voltage fluctuation. However, as in the embodiment, the shift register based light emitting signal generating circuit is provided with the second capacitor CQP so as not to be influenced by the second clock signal Charging and discharging due to voltage fluctuations hardly occur. Therefore, in the embodiment, the charging / discharging operation of the second capacitor CQP is not greatly affected by the load of the clock signal line, so that the signal delay due to the load of the clock signal line can be solved.

Therefore, the present specification can improve the driving capability of the transistor and maintain the stable output characteristics, and it is possible to provide the built-in scan driver which is advantageous to the narrow bezel. In this specification, even when the threshold voltage of a transistor operating as an output buffer is shifted, a normal output can be maintained by compensating for a threshold voltage, so that driving reliability can be improved.

The scan driver according to embodiments of the present invention and the electroluminescent display including the scan driver may be described as follows.

The scan driver according to an embodiment of the present invention includes a first output buffer unit turned on based on a potential of a Q node to output a first emission control signal and a second output buffer unit configured with a double buffer, , The double buffer includes two transistors, and the two transistors are connected to gate electrodes of different nodes, respectively, and output the same second emission control signal.

According to another aspect of the present invention, there is provided a QB2 node controller for controlling a QB2 node based on a potential of a Q node and a QB1 node controller for controlling a QB1 node based on a potential of the QB2 node, May have different potentials.

According to another aspect of the present invention, the second output buffer unit includes a 2-1 output buffer unit including a transistor operating in correspondence to the potential of the QB1 node, a 2-1 output buffer unit including a transistor operating in correspondence with the potential of the QB2 node, And an output buffer unit.

The QB2 node controller controls the QB2 node based on the potential of the Q node. The QB2 node controller controls the QB2 node based on the potential of the Q node. The QB2 node controller controls the QB2 node based on the start signal transmitted through the start signal line. A first output buffer unit that is turned on based on the potential of the Q node to output a first emission control signal, and a second output buffer unit that is turned on based on the potential of the second node, And a second output buffer portion having at least two transistors for outputting the emission control signal.

According to another aspect of the present invention, the first output buffer section outputs a logic low light emission control signal, and the second output buffer section outputs a logic high light emission control signal which is a voltage higher than a logic low.

According to another aspect of the present invention, in the second output buffer section, the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrode of the at least two transistors is connected to a different node And may have a connected parallel connection structure.

According to another aspect of the present invention, the second output buffer section includes: a 2-1 output buffer section composed of a transistor operating in correspondence with the first potential; and a 2-1 output buffer section composed of a transistor operating in correspondence with the second potential, 2-2 output buffer unit.

According to another aspect of the present invention, the first potential may be the potential of the QB1 node and the second potential may be the potential of the QB2 node.

An electroluminescent display device according to an embodiment of the present invention includes a display panel for displaying an image; And a scan driver including scan signal generating circuits for outputting a scan signal to the display panel and emission signal generating circuits for outputting an emission signal to the display panel, wherein m is a positive integer ) The emission signal generation circuit includes: a first output buffer unit that is turned on based on the potential of the Q node and outputs a first emission control signal; And a second output buffer unit composed of a double buffer, wherein the double buffer includes two transistors, and the two transistors are connected to gate electrodes of different transistors and output the same second emission control signal .

According to another aspect of the present invention, in the second output buffer section, the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrode of the at least two transistors is connected to a different node And may have a connected parallel connection structure.

According to another aspect of the present invention, the second output buffer section includes: a 2-1 output buffer section composed of a transistor operating in correspondence with the first potential; and a 2-1 output buffer section composed of a transistor operating in correspondence with the second potential, 2-2 output buffer unit.

According to another aspect of the present invention, the mth emission signal generating circuit further includes a QB2 node controller for controlling a QB2 node based on a potential of a Q node and a QB1 node controller for controlling a QB1 node based on a potential of the QB2 node , And the QB1 node and the QB2 node may have different potentials.

According to another aspect of the present invention, the second output buffer unit includes a 2-1 output buffer unit including a transistor operating in correspondence to the potential of the QB1 node, a 2-1 output buffer unit including a transistor operating in correspondence with the potential of the QB2 node, And an output buffer unit.

According to another aspect of the present invention, there is provided an mth light emitting signal generating circuit including a first transistor having a gate electrode connected to a second clock signal line, a first electrode connected to a start signal line and a second electrode connected to a Q node, A second transistor having a gate electrode connected to the node and a first electrode connected to the first clock signal line, a gate electrode connected to the QB2 node, a first electrode connected to the Q node, and a second electrode connected to the high- A fourth transistor having a gate electrode connected to the second clock signal line and a first electrode connected to the (m-1) th QB2 node of the (m-1) th emission signal generating circuit and a second electrode connected to the QP node; A fifth transistor having a gate electrode connected to the Q node, a first electrode connected to the QB2 node, and a second electrode connected to the high voltage line, a gate electrode connected to the Q node, and a first electrode connected to the low potential voltage line And the m < th > A seventh transistor having a gate electrode connected to the node QB1 and having a first electrode connected to the output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line, A 7-2 transistor having a gate electrode connected to the node QB2 and having a first electrode connected to the output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line, and a gate electrode connected to the QP node A first electrode connected to the first clock signal line and a second electrode connected to the QB2 node, a gate electrode connected to the first clock signal line, a first electrode connected to the QB2 node, and a second electrode connected to the QB1 node, And a tenth transistor having a gate connected to a node Q, a first electrode connected to a node QB1, and a second electrode connected to a high potential line.

According to another aspect of the present invention, the m-th light emitting signal generating circuit includes a first capacitor having one end connected to the second electrode of the second transistor and the other end connected to the Q electrode and the first electrode of the third transistor, And a third capacitor having one end connected to the node QB1 and the other end connected to the high potential voltage line.

According to another aspect of the present invention, the first transistor, the second transistor, the third transistor and the first capacitor are included in a Q-node control unit for controlling the Q-node, and the fifth transistor, the tenth transistor, The fourth transistor, the eighth transistor, and the second capacitor are included in a QB2 node control unit for controlling a QB2 node, and the sixth transistor is included in a QB1 node control unit for controlling a first output And the seventh and eighth transistors may be included in a second output buffer unit for outputting a second emission control signal.

An electroluminescent display according to an embodiment of the present invention includes a display panel for displaying an image, scan signal generating circuits for outputting a scan signal to the display panel, and emission signal generating circuits for outputting an emission signal to the display panel (M is a positive integer) emission signal generation circuit of the emission signal generation circuits includes a Q node controller for controlling a Q node based on a start signal transmitted through a start signal line, A QB2 node controller for controlling the QB2 node based on the potential, a QB1 node controller for controlling the QB1 node based on the potential of the QB2 node, a first output buffer for turning on the first node based on the potential of the Q node, And a second output buffer portion having at least two transistors, wherein at least two transistors are turned on based on the potential of the different node, And outputs a call.

According to another aspect of the present invention, in the second output buffer section, the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrode of the at least two transistors is connected to a different node And may have a connected parallel connection structure.

According to another aspect of the present invention, the second output buffer unit includes a 2-1 output buffer unit including a transistor operating in correspondence to the potential of the QB1 node, a 2-1 output buffer unit including a transistor operating in correspondence with the potential of the QB2 node, And an output buffer unit.

According to another aspect of the present invention, there is provided an mth light emitting signal generating circuit including a first transistor having a gate electrode connected to a second clock signal line, a first electrode connected to a start signal line and a second electrode connected to a Q node, A second transistor having a gate electrode connected to the node and a first electrode connected to the first clock signal line, a gate electrode connected to the QB2 node, a first electrode connected to the Q node, and a second electrode connected to the high- A fourth transistor having a gate electrode connected to the second clock signal line and a first electrode connected to the (m-1) th QB2 node of the (m-1) th emission signal generating circuit and a second electrode connected to the QP node; A fifth transistor having a gate electrode connected to the Q node, a first electrode connected to the QB2 node, and a second electrode connected to the high voltage line, a gate electrode connected to the Q node, and a first electrode connected to the low potential voltage line And the m < th > A seventh transistor having a gate electrode connected to the node QB1 and having a first electrode connected to the output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line, A 7-2 transistor having a gate electrode connected to the QB2 node and having a first electrode connected to the output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line, and a gate electrode connected to the QP node A first electrode connected to the first clock signal line and a second electrode connected to the QB2 node, a gate electrode connected to the first clock signal line, a first electrode connected to the QB2 node, and a second electrode connected to the QB1 node, And a tenth transistor having a gate connected to a node Q, a first electrode connected to a node QB1, and a second electrode connected to a high potential line.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

120: timing control unit 140:
130: scan driver 150: display panel
133: Q node control unit 1 34: QB2 node control unit
137: QB1 node control unit T6: first output buffer unit
T7, T7a, and T7b: the second output buffer unit

Claims (20)

A first output buffer unit that is turned on based on the potential of the Q node to output a first emission control signal; And
And a second output buffer unit composed of a double buffer,
Wherein the double buffer includes two transistors and the gate electrodes of the two transistors are connected to different nodes and output the same second emission control signal. The method according to claim 1,
A QB2 node controller for controlling a QB2 node based on the potential of the Q node,
And a QB1 node controller for controlling the QB1 node based on the potential of the QB2 node,
Wherein the QB1 node and the QB2 node have different potentials. 3. The method of claim 2,
The second output buffer unit
A 2-1 output buffer unit composed of transistors operating in correspondence with the potential of the QB1 node,
And a 2-2 output buffer unit including a transistor operating in accordance with the potential of the QB2 node. A Q node controller for controlling a Q node based on a start signal transmitted through a start signal line;
A QB2 node controller for controlling a QB2 node based on the potential of the Q node;
A QB1 node controller for controlling the QB1 node based on the potential of the QB2 node;
A first output buffer unit that is turned on based on the potential of the Q node and outputs a first emission control signal; And
And a second output buffer unit having at least two transistors for turning on the second node and outputting a second emission control signal based on the potentials of the different nodes. 5. The method of claim 4,
Wherein the first output buffer unit outputs a logic low light emission control signal,
And the second output buffer unit outputs a light emission control signal of a logic high which is higher than the logic low. 5. The method of claim 4,
The second output buffer unit
Wherein the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrodes of the at least two transistors are connected to different nodes. The method according to claim 6,
The second output buffer unit
A second-1 output buffer section composed of transistors operating in correspondence with the first potential,
And a second-2 output buffer unit including a transistor which operates in correspondence to the first potential and the second potential. 8. The method of claim 7,
The first potential is a potential of the QB1 node,
And the second potential is a potential of the QB2 node. A display panel for displaying an image; And
And a scan driver including scan signal generating circuits for outputting a scan signal to the display panel and emission signal generating circuits for outputting an emission signal to the display panel,
The mth (m is a positive integer) emission signal generating circuit of the emission signal generating circuits
A first output buffer unit that is turned on based on the potential of the Q node to output a first emission control signal; And
And a second output buffer unit composed of a double buffer,
Wherein the double buffer includes two transistors, and the two transistors have gate electrodes connected to different nodes, respectively, and output the same second emission control signal. 10. The method of claim 9,
The second output buffer unit
Wherein the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrodes of the at least two transistors are connected to different nodes. 10. The method of claim 9,
The second output buffer unit
A second-1 output buffer section composed of transistors operating in correspondence with the first potential,
And a second-2 output buffer unit including a transistor that operates in correspondence with the first potential and a second potential different from the first potential. 10. The method of claim 9,
The Nth emission signal generation circuit
A QB2 node controller for controlling a QB2 node based on the potential of the Q node,
And a QB1 node controller for controlling the QB1 node based on the potential of the QB2 node,
And the QB1 node and the QB2 node have different potentials. 13. The method of claim 12,
The second output buffer unit
A 2-1 output buffer unit composed of transistors operating in correspondence with the potential of the QB1 node,
And a 2-2 output buffer unit including a transistor operating in correspondence to the potential of the QB2 node. 10. The method of claim 9,
The m < th >
A first transistor having a gate electrode connected to the second clock signal line, a first electrode connected to the start signal line and a second electrode connected to the Q node,
A second transistor having a gate electrode connected to the Q node and a first electrode connected to a first clock signal line,
A third transistor having a gate electrode connected to the QB2 node, a first node connected to the Q node and a second electrode connected to the high potential voltage line,
A fourth transistor having a gate electrode connected to the second clock signal line and having a first electrode connected to the (m-1) th QB2 node of the (m-1) th emission signal generating circuit and a second electrode connected to the QP node,
A fifth transistor having a gate electrode connected to the Q node, a first electrode connected to the node QB2 and a second electrode connected to the high potential voltage line,
A sixth transistor having a gate electrode connected to the Q node, a first electrode connected to a low potential voltage line, and a second electrode connected to an output terminal of the mth emission signal generating circuit,
A seventh transistor having a gate electrode connected to the QB1 node and having a first electrode connected to an output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line;
A seventh transistor having a gate electrode connected to the QB2 node and having a first electrode connected to an output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line,
An eighth transistor having a gate electrode connected to the QP node, a first electrode connected to the first clock signal line and a second electrode connected to the QB2 node,
A ninth transistor having a gate electrode connected to the first clock signal line, a first electrode connected to the QB2 node and a second electrode connected to the QB1 node,
And a tenth transistor having a gate electrode connected to the Q node, a first electrode connected to the node QB1, and a second electrode connected to the high potential voltage line. 15. The method of claim 14,
The m < th >
A first capacitor having one end connected to the second electrode of the second transistor and the other end connected to the Q node and the first electrode of the third transistor;
A second capacitor having one end connected to the QP node and the other end connected to the QB2 node,
And a third capacitor having one end connected to the node QB1 and the other end connected to the high potential voltage line. 16. The method of claim 15,
Wherein the first transistor, the second transistor, the third transistor, and the first capacitor are included in a Q-node control unit that controls the Q-node,
Wherein the fifth transistor, the tenth transistor, and the third capacitor are included in a QB1 node controller for controlling the QB1 node,
Wherein the fourth transistor, the eighth transistor, and the second capacitor are included in a QB2 node controller for controlling the QB2 node,
The sixth transistor is included in the first output buffer unit for outputting the first emission control signal,
And the seventh transistor and the seventh transistor are included in the second output buffer unit for outputting the second emission control signal. A display panel for displaying an image; And
And a scan driver including scan signal generating circuits for outputting a scan signal to the display panel and emission signal generating circuits for outputting an emission signal to the display panel,
The mth (m is a positive integer) emission signal generating circuit of the emission signal generating circuits
A Q node controller for controlling a Q node based on a start signal transmitted through a start signal line;
A QB2 node controller for controlling a QB2 node based on the potential of the Q node;
A QB1 node controller for controlling the QB1 node based on the potential of the QB2 node;
A first output buffer unit that is turned on based on the potential of the Q node and outputs a first emission control signal; And
And a second output buffer portion having at least two transistors,
Wherein the at least two transistors are turned on based on a potential of a different node to output a second emission control signal. 18. The method of claim 17,
The second output buffer unit
Wherein the first electrode of the at least two transistors is connected to the first electrode, the second electrode is connected to the second electrode, and the gate electrodes of the at least two transistors are connected to different nodes. 18. The method of claim 17,
The second output buffer unit
A 2-1 output buffer unit composed of transistors operating in correspondence with the potential of the QB1 node,
And a 2-2 output buffer unit including a transistor operating in correspondence to the potential of the QB2 node. 18. The method of claim 17,
The m < th >
A first transistor having a gate electrode connected to the second clock signal line, a first electrode connected to the start signal line and a second electrode connected to the Q node,
A second transistor having a gate electrode connected to the Q node and a first electrode connected to a first clock signal line,
A third transistor having a gate electrode connected to the QB2 node, a first node connected to the Q node and a second electrode connected to the high potential voltage line,
A fourth transistor having a gate electrode connected to the second clock signal line and having a first electrode connected to the (m-1) th QB2 node of the (m-1) th emission signal generating circuit and a second electrode connected to the QP node,
A fifth transistor having a gate electrode connected to the Q node, a first electrode connected to the node QB2 and a second electrode connected to the high potential voltage line,
A sixth transistor having a gate electrode connected to the Q node, a first electrode connected to a low potential voltage line, and a second electrode connected to an output terminal of the mth emission signal generating circuit,
A seventh transistor having a gate electrode connected to the QB1 node and having a first electrode connected to an output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line,
A seventh transistor having a gate electrode connected to the QB2 node and having a first electrode connected to an output terminal of the mth emission signal generating circuit and a second electrode connected to the high potential voltage line,
An eighth transistor having a gate electrode connected to the QP node, a first electrode connected to the first clock signal line and a second electrode connected to the QB2 node,
A ninth transistor having a gate electrode connected to the first clock signal line, a first electrode connected to the QB2 node and a second electrode connected to the QB1 node,
And a tenth transistor having a gate electrode connected to the Q node, a first electrode connected to the node QB1, and a second electrode connected to the high potential voltage line.

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