KR20180079102A - Light emitting display device - Google Patents

Abstract

The present invention provides a light emitting display device capable of increasing an aperture ratio and realizing a high resolution. The light emitting display device comprises: a display panel including a plurality of pixels each provided in a pixel region defined by a plurality of gate lines, a plurality of data lines and a plurality of driving power supply lines arranged in parallel with the gate lines; and a pixel driving voltage supply unit connected to at least one of one end and the other end of each of the plurality of driving power supply lines and selectively supplying a high potential driving voltage and a low potential driving voltage to each of the plurality of driving power supply lines, wherein pixel columns provided along the longitudinal direction of the gate lines share adjacent driving power supply lines.

Description

[0001] LIGHT EMITTING DISPLAY DEVICE [0002]

The present invention relates to a light emitting display.

The light emitting display device has advantages of high response speed, high luminance efficiency, and large viewing angle.

A conventional light emitting display device has a plurality of pixels provided in each of pixel regions defined by a plurality of gate lines, a plurality of data lines, and a plurality of pixel driving power supply lines arranged in parallel with a plurality of data lines.

Each of the plurality of pixels applies a data voltage supplied to the data line to the gate electrode of the driving transistor using the transistor turned on by the scan pulse supplied to the corresponding gate line to charge the capacitor to the gate electrode of the driving transistor, And outputs the charged data voltage to the storage capacitor to emit the light emitting element.

Such a conventional light emitting display device is disclosed in Korean Patent Laid-Open Publication No. 10-2016-0019627 (hereinafter referred to as "prior patent document").

However, since the conventional light emitting display device disclosed in the prior patent document can not exceed one horizontal period by combining the sampling period and the lighting period, the higher the resolution of the display panel becomes, the shorter the sampling time required for compensation becomes, Since the emission control transistor and the emission control signal line are disposed for each pixel, the aperture ratio is reduced and it is difficult to realize a high resolution display panel.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the background art, and it is an object of the present invention to provide a light emitting display capable of increasing the aperture ratio and realizing a high resolution.

The present invention provides a light emitting display device capable of realizing a high resolution and compensating a threshold voltage of a driving transistor while solving the problem of the background art.

According to an aspect of the present invention, there is provided a light emitting display including a plurality of pixels arranged in a pixel region defined by a plurality of gate lines, a plurality of data lines, and a plurality of driving power supply lines aligned with the gate lines, And a pixel driving voltage supply unit connected to at least one end of each of the plurality of driving power supply lines and selectively supplying a high potential driving voltage and a low potential driving voltage to each of the plurality of driving power supply lines, The pixel columns provided along the longitudinal direction of the gate lines share the adjacent driving power supply lines.

According to the solution of the above problem, the light emitting display according to the present application has an effect of increasing the aperture ratio, thereby enabling a high resolution, and realizing a high resolution and compensating the threshold voltage of the driving transistor.

In addition to the effects of the present application discussed above, other features and advantages of the present application will be set forth below, or may be apparent to those skilled in the art to which the present application belongs from such description and description.

1 is a view schematically showing a light emitting display according to an example of the present application.
FIG. 2 is a view for explaining a pixel according to the example shown in FIG. 1, which shows an i-th pixel column provided in the display panel.
3 is a diagram showing an example of the i-th pixel train shown in Fig.
4 is a view for explaining a pixel driving voltage supply unit according to the example shown in FIG.
5 is a view for explaining a pixel driving voltage supply unit according to the example shown in FIG.
FIG. 6 is a view for explaining the i-th voltage supply circuit shown in FIG.
7 is a view for explaining the gate driving circuit shown in Fig.
8 is a waveform diagram showing an input / output signal of the gate driving circuit shown in Fig.
9 is a diagram showing the i-th stage shown in Fig.
10 is a diagram for explaining the gate driving circuit shown in FIG.
11 is a view showing the i-th stage shown in Fig.
12 is a view for explaining a light emitting display according to an example of the present application.
13 is a driving waveform diagram for explaining the driving method of the pixel shown in FIG.

Brief Description of the Drawings The advantages and features of the present application, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that this application is not limited to the examples disclosed herein, but may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein, To fully disclose the scope of the invention to those skilled in the art, and this application is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like described in the drawings for describing an example of the present application are illustrative, and thus the present application is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the description of the present application, a detailed description of known related arts will be omitted if it is determined that the gist of the present application may be unnecessarily obscured.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the scope of the present application.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

Each of the features of the various embodiments of the present application may be combined or combined with each other partially or entirely, technically various interlocking and driving are possible, and the examples may be independently performed with respect to each other, .

Hereinafter, preferred embodiments of the light emitting display according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to the constituent elements of each drawing, the same constituent elements may have the same sign as possible even if they are indicated on other drawings

1 is a view schematically showing a light emitting display according to an example of the present application.

1, a light emitting display according to an embodiment of the present invention includes a display panel 100, a timing controller 200, a data driving circuit 300, a gate driving circuit 400, and a pixel driving voltage supplier 500 ).

The display panel 100 includes a first substrate and a second substrate facing each other.

The first substrate includes a display area AA and a non-display area IA provided around the display area AA.

The display area AA includes a plurality of data lines DL1 to DLm, a plurality of gate lines GL1 to GLn, a plurality of driving power supply lines PL1 to PLn, and a plurality of pixels P.

The plurality of data lines DL1 to DLm are provided on the front surface of the first substrate and are spaced apart from each other along the first horizontal axis direction X and extend along the second horizontal axis direction Y It extends long. Here, the first horizontal axis direction X may be parallel to the first longitudinal direction X of the first substrate, for example, the plurality of gate lines GL1 to GLn, the longitudinal direction of the first substrate, And the second horizontal axis direction Y may be parallel to the second longitudinal direction Y of the first substrate, for example, the longitudinal direction or the longitudinal direction of the short side of the first substrate.

Each of the plurality of gate lines GL1 to GLn is provided on the front surface of the first substrate so as to intersect with the plurality of data lines DL1 to DLm and extends in the first horizontal axis direction X And are spaced at regular intervals along the second horizontal axis direction (Y).

The plurality of driving power lines PL1 to PLn are provided on the first substrate so as to be parallel to the plurality of gate lines GL1 to GLn and may be formed together with each of the plurality of gate lines GL1 to GLn . For example, one driving power supply line PL is arranged in parallel with the gate lines GL1 to GLn with the pixel P therebetween.

Each of the plurality of pixels P is provided in a pixel region defined by the intersection of the plurality of data lines DL1 to DLm and the plurality of gate lines GL1 to GLn. Each of the plurality of pixels P displays an image through light emission of the light emitting device according to a data voltage supplied from the data lines DL1 to DLm connected to the scan pulse supplied from the connected gate lines GL1 to GLn.

The second substrate covers the entire first substrate excluding a part of the non-display area IA. At this time, when the light emitting element of each pixel P emits white light, a color filter layer overlapping each pixel P may be formed on the second substrate.

The timing controller 200 generates pixel-by-pixel data Pdata by aligning the input image data Idata so as to be suitable for driving the display panel 100 and generates data Pdata for each pixel based on the input timing synchronization signal TSS. And provides the control signal DCS to the data driving circuit 300. The timing controller 200 generates a gate control signal GCS including a gate start signal, a plurality of gate shift clocks, and a plurality of carry shift clocks based on the timing synchronization signal TSS, . The timing controller 200 according to an exemplary embodiment includes a data control signal DCS and a gate control signal PCS for driving the pixel P divided into an initialization period, a sampling period, a data address period, and a light emission period for one frame Can be generated. Alternatively, the timing controller 200 may control the voltage level of the pixel driving voltage supplied from the pixel driving voltage supply unit 500 to the driving power supply lines PL1 to PLn in accordance with the driving period of the pixel P, Can be generated.

The data driving circuit 300 is connected to a plurality of data lines DL1 to DLm provided on the display panel 100. [ The data driving circuit 300 receives the pixel-by-pixel data signal Pdata, the data control signal DCS, and the plurality of reference gamma voltages, supplied from the timing controller 200, Pixel data voltage, and supplies the converted data voltage for each pixel to the data lines DL1 to DLm. The data driving circuit 300 according to an example may supply the pixel-by-pixel data voltage to the corresponding data line DL during the data address period of the pixel P in response to the data control signal DCS. Alternatively, in response to the data control signal DCS, the data driving circuit 300 may supply an initialization voltage Vdata corresponding to a predetermined initialization data signal Pdata during the initialization period of the pixel P and a part of the sampling period, And supplies the pixel data voltages to the corresponding data lines DL during the data address period of the pixels P. [

The gate driving circuit 400 is provided in the left non-display region of the first substrate 210 together with the manufacturing process of the thin film transistor of the pixel. The gate driving circuit 400 supplies the scan pulses to the gate lines GL1 to GLn corresponding to the predetermined order. The gate driving circuit 400 according to an exemplary embodiment generates scan pulses in accordance with a gate control signal GCS provided from the timing controller 200 and supplies the generated scan pulses to corresponding gate lines GL1 to GLn in a predetermined sequence. For example, the gate driving circuit 400 supplies scan pulses to the corresponding gate lines GL1 to GLn during the data addressing period in response to the gate control signal GCS.

The pixel driving voltage supplier 500 is connected to one end of each of the plurality of driving power lines PL1 to PLn to selectively supply a high potential driving voltage and a low potential driving voltage to the plurality of driving power lines PL1 to PLn, do. That is, the pixel driving voltage supply unit 500 is provided in the left non-display region of the first substrate adjacent to the gate driving circuit 400 and is electrically connected to the left end of each of the plurality of driving power supply lines PL1 to PLn. The pixel driving voltage supplying unit 500 applies high voltage driving to each of the plurality of driving power lines PL1 to PLn in response to a power source selecting signal from the timing controller 200 or a power source selecting signal from the gate driving circuit 400 Voltage and a low-potential driving voltage. The pixel driving voltage supplier 500 according to an exemplary embodiment supplies the low potential driving voltage to the corresponding driving power supply lines PL1 to PLn during the initialization period of the pixel P in response to the power source control signal, And supplies the high potential driving voltage to the corresponding driving power supply line PL during the sampling period, the data address period, and the light emission period.

In the light emitting display according to this example, the plurality of driving power lines PL1 to PLn are arranged in parallel with the gate lines GL having a relatively small number of data lines DL, The aperture ratio of the pixel P can be increased by selectively supplying the pixel driving voltage to the plurality of driving power supply lines PL1 to PLn through the pixel driving circuit 500. [ In particular, since the emission control transistor and the emission control signal line are removed as compared with the conventional pixel, the light emitting display according to the present embodiment increases the aperture ratio, thereby enabling high resolution.

FIG. 2 is a view for explaining a pixel according to the example shown in FIG. 1, which shows an i-th pixel column provided in the display panel.

1 and 2, a plurality of pixels P provided in an i-th pixel column according to the present example are connected in a one-to-one manner to a plurality of data lines DL1 to DLm and share an i-th gate line GLi, i Th pixel driving power supply line PLi.

Each of the plurality of pixels P according to an example includes a pixel circuit PC and a light emitting element ELD.

The pixel circuit PC includes a switching thin film transistor Tsw, a driving thin film transistor Tdr, and a capacitor Cst.

The switching thin film transistor Tsw includes a gate electrode connected to the i-th gate line GLi, a first electrode connected to the data lines DL1 to DLm and a gate electrode of the driving thin film transistor Tdr through a first node N1. And a second electrode connected to the electrode. Here, the first and second electrodes of the switching thin film transistor Tsw may be a source electrode or a drain electrode depending on the direction of current. This switching thin film transistor Tsw is switched according to the scan pulse SP supplied to the i-th gate line GLi to supply the data voltage Vdata supplied to the data lines DL1 to DLm to the first node N1 Supply.

The driving thin film transistor Tdr is turned on by the voltage of the first node N1 to control a voltage (or current) applied from the driving power supply lines PL1 to PLn to the light emitting element ELD. For this, the driving thin film transistor Tdr according to an example includes a gate electrode connected to the second electrode N1 of the switching thin film transistor Tsw, a drain electrode connected to the i-th driving power supply line PLi, And a source electrode connected to the light emitting element ELD through the N2. The driving thin film transistor Tdr is turned on by a voltage difference between the gate and the source based on the data voltage Vdata supplied from the switching thin film transistor Tsw to be supplied to the light emitting element ELD ) Of the current flowing through the capacitor.

The capacitor Cst is provided in an overlapped region between the gate electrode N1 and the source electrode N2 of the driving thin film transistor Tdr and stores the difference voltage between the gate electrode and the source electrode of the driving thin film transistor Tdr , And turns on the driving thin film transistor Tdr with the stored voltage.

The light emitting device ELD is connected between the pixel circuit PC and the common power supply electrode VSS. That is, the light emitting element ELD is electrically connected to the source electrode of the driving thin film transistor Tdr through the second node N2 provided in the pixel circuit PC. The light emitting device ELD according to an example includes a first electrode connected to the source electrode of the driving thin film transistor Tdr, a second electrode connected to the common power supply electrode, and an electron emitter formed between the first electrode and the second electrode . Here, the electron emitter may be an organic emitter, a quantum dot emitter, or an inorganic emitter including a quantum dot emitter. The light emitting element ELD emits light by the voltage (or current) supplied from the driving thin film transistor Tdr.

3 is a diagram showing an example of the i-th pixel train shown in Fig.

1 and 2, a plurality of pixels P provided in an i-th pixel column according to the present example are connected in a one-to-one manner to a plurality of data lines DL1 to DLm and share an i-th gate line GLi, i Th pixel driving power supply line PLi.

Each of the plurality of pixels P according to an example includes a pixel circuit PC and a light emitting element ELD.

The pixel circuit PC includes a switching thin film transistor Tsw, a driving thin film transistor Tdr, and a capacitor Cst.

The switching thin film transistor Tsw includes a gate electrode connected to the i-th gate line GLi, a first electrode connected to the data lines DL1 to DLm and a gate electrode of the driving thin film transistor Tdr through a first node N1. And a second electrode connected to the electrode. Here, the first and second electrodes of the switching thin film transistor Tsw may be a source electrode or a drain electrode depending on the direction of current. The switching thin film transistor Tsw is switched according to the i-th scan pulse SPi supplied from the gate driving circuit 400 to the i-th gate line GLi to generate a data voltage Vdata To the first node N1.

The driving thin film transistor Tdr is turned on by the voltage of the first node N1 to emit light based on the pixel driving voltage EVDD supplied from the gate driving circuit 400 to the i th driving power supply line PLi, And controls the voltage (or current) applied to the element ELD. For this, the driving thin film transistor Tdr according to an example includes a gate electrode connected to the second electrode N1 of the switching thin film transistor Tsw, a drain electrode connected to the i-th driving power supply line PLi, And a source electrode connected to the light emitting element ELD through the N2. The driving thin film transistor Tdr is turned on by a voltage difference between the gate and the source based on the data voltage Vdata supplied from the switching thin film transistor Tsw to be supplied to the light emitting element ELD ) Of the current flowing through the capacitor.

The capacitor Cst is provided in an overlapped region between the gate electrode N1 and the source electrode N2 of the driving thin film transistor Tdr and stores the difference voltage between the gate electrode and the source electrode of the driving thin film transistor Tdr , And turns on the driving thin film transistor Tdr with the stored voltage.

The light emitting device ELD is connected between the pixel circuit PC and the common power supply electrode VSS. That is, the light emitting element ELD is electrically connected to the source electrode of the driving thin film transistor Tdr through the second node N2 provided in the pixel circuit PC. The light emitting device ELD according to an example includes a first electrode connected to the source electrode of the driving thin film transistor Tdr, a second electrode connected to the common power supply electrode, and an electron emitter formed between the first electrode and the second electrode . Here, the electron emitter may be an organic emitter, a quantum dot emitter, or an inorganic emitter including a quantum dot emitter. The light emitting element ELD emits light by the voltage (or current) supplied from the driving thin film transistor Tdr.

In addition, the pixel circuit PC of the pixel P according to the present example may further include an auxiliary capacitor formed between the second node N2 and the DC power source. The auxiliary capacitor increases the charge amount of the capacitor Cst when charging the voltage of the capacitor Cst. The auxiliary capacitor according to an example has a smaller capacitance than the capacitor Cst. Alternatively, the auxiliary capacitor may be electrically connected in parallel with the light emitting element ELD.

As described above, the pixel P according to the present embodiment can increase the aperture ratio by disposing the driving power supply lines PL1 to PLn in parallel with the gate lines GL1 to GLn, Since the emission control signal line is removed, the aperture ratio can be further increased.

FIG. 3 is a view for explaining a pixel according to an example shown in FIG. 1, which shows an i-th pixel column provided in a display panel.

Referring to FIGS. 1 and 3, the display panel 100 according to the present application further includes a plurality of initialization voltage lines IL1 to ILm arranged in parallel with a plurality of data lines DL1 to DLm, respectively.

The plurality of pixels P provided in the i-th pixel column according to the present example are connected in a one-to-one manner to the plurality of data lines DL1 to DLm and the plurality of initialization voltage lines IL1 to ILm, respectively, Sharing the i-th pixel driving power supply line PLi while sharing.

Each of the plurality of pixels P according to an example includes a pixel circuit PC and a light emitting element ELD.

The pixel circuit PC includes a switching thin film transistor Tsw, an initial thin film transistor Tini, a driving thin film transistor Tdr, and a capacitor Cst.

The switching thin film transistor Tsw includes a gate electrode connected to the i-th gate line GLi, a first electrode connected to the data lines DL1 to DLm and a gate electrode of the driving thin film transistor Tdr through a first node N1. And a second electrode connected to the electrode. Here, the first and second electrodes of the switching thin film transistor Tsw may be a source electrode or a drain electrode depending on the direction of current. The switching thin film transistor Tsw is switched according to the i-th scan pulse SPi supplied from the gate driving circuit 400 to the i-th gate line GLi to generate a data voltage Vdata To the first node N1.

The initialization thin film transistor Tini includes a gate electrode connected to the i-1th gate line GLi-1, a first electrode connected to the initialization voltage lines IL1 through ILm, And a second electrode connected to the gate electrode of the second transistor Tdr. Here, the first and second electrodes of the initialization thin film transistor Tini may be a source electrode or a drain electrode depending on the direction of current. The initialization thin film transistor Tini is switched according to the (i-1) th scan pulse SPi-1 supplied from the gate driving circuit 400 to the (i-1) th gate line GLi-1, And supplies the initialization voltage Vini to the first node N1.

The driving thin film transistor Tdr is turned on by the voltage of the first node N1 to emit light based on the pixel driving voltage EVDD supplied from the gate driving circuit 400 to the i th driving power supply line PLi, And controls the voltage (or current) applied to the element ELD. For this, the driving thin film transistor Tdr according to an example includes a gate electrode connected to the second electrode N1 of the switching thin film transistor Tsw, a drain electrode connected to the i-th driving power supply line PLi, And a source electrode connected to the light emitting element ELD through the N2. The driving thin film transistor Tdr is turned on by a voltage difference between the gate and the source based on the data voltage Vdata supplied from the switching thin film transistor Tsw to be supplied to the light emitting element ELD ) Of the current flowing through the capacitor.

The capacitor Cst is provided in an overlapping region between the gate electrode N1 and the source electrode N2 of the driving thin film transistor Tdr and is connected to the gate electrode of the driving thin film transistor Tdr and the source electrode N2, (Vdata-Vini) between the initialization voltage Vdata and the initialization voltage Vini, and turns on the driving transistor Tdr with the stored voltage.

The light emitting device ELD is connected between the pixel circuit PC and the common power supply electrode VSS. That is, the light emitting element ELD is electrically connected to the source electrode of the driving thin film transistor Tdr through the second node N2 provided in the pixel circuit PC. The light emitting device ELD according to an example includes a first electrode connected to the source electrode of the driving thin film transistor Tdr, a second electrode connected to the common power supply electrode, and an electron emitter formed between the first electrode and the second electrode . Here, the electron emitter may be an organic emitter, a quantum dot emitter, or an inorganic emitter including a quantum dot emitter. The light emitting element ELD emits light by the voltage (or current) supplied from the driving thin film transistor Tdr.

In addition, the pixel circuit PC of the pixel P according to the present example may further include an auxiliary capacitor formed between the second node N2 and the DC power source. The auxiliary capacitor increases the charge amount of the capacitor Cst when charging the voltage of the capacitor Cst. The auxiliary capacitor according to an example has a smaller capacitance than the capacitor Cst. Alternatively, the auxiliary capacitor may be electrically connected in parallel with the light emitting element ELD.

As described above, the pixel P according to the present embodiment can increase the aperture ratio by disposing the driving power supply lines PL1 to PLn in parallel with the gate lines GL1 to GLn, Since the emission control signal line is removed, the aperture ratio can be further increased.

4 is a view for explaining a pixel driving voltage supply unit according to the example shown in FIG.

Referring to FIG. 4, a pixel driving voltage supplier 500 according to an exemplary embodiment includes a plurality of voltage supply circuits 5001 to 500n connected to a plurality of driving power lines PL1 to PLn, respectively, on a one-to-one basis.

Each of the plurality of voltage supply circuits 5001 to 500n includes a first power control transistor PT1 and a second power control transistor PT2.

The first power source control transistor PT1 is provided between one end of each of the plurality of driving power source lines PL1 to PLn and the gate driving circuit and the display region and is provided in the same structure as the thin film transistor provided in the pixel P .

The first power source control transistor PT1 according to an exemplary embodiment may include driving power supply lines PL1 to PLn corresponding to the sampling period of the pixel P, the data addressing period, and the light emission period according to the first power source selection signals PSS1 to PSSn, (EVDD_H). Here, the first power supply selection signals PSS1 to PSSn are power supply selection signals supplied from the timing controller 200. [ The first power source control transistor PT1 according to an example includes a gate electrode to which the first power source selection signals PSS1 to PSSn are supplied, a drain electrode connected to the high potential driving voltage line to which the high potential driving voltage EVDD_H is supplied, And a source electrode connected to one end of the driving power supply lines PL1 to PLn through an output terminal Nt. Here, the source electrode and the drain electrode of the first power source control transistor PT1 may be switched according to the direction of the current.

The second power source control transistor PT2 is provided in parallel with the first power source control transistor PT1 along the longitudinal direction or the gate line of the driving power source lines PL1 to PLn and includes a first power source control transistor PT1, Can be provided in the same structure.

The second power source control transistor PT2 according to an exemplary embodiment applies a low potential driving voltage EVDD_L to the driving power source line PL corresponding only to the initialization period of the pixel P in accordance with the second power source selection signals BPSS1 to BPSSn The high-potential driving voltage EVDD_H supplied to the light-emitting element of the pixel P is cut off to stop the light emission of the light-emitting element. Here, the second power supply selection signals BPSS1 to BPSSn have logic voltage levels that are opposite (or inverted) to the power supply selection signal supplied from the timing controller 200. [ The second power source control transistor PT2 according to one example includes a gate electrode to which the second power selection signals BPSS1 to BPSSn are supplied, a drain electrode connected to the low potential driving voltage line to which the low potential driving voltage EVDD_L is supplied, And a source electrode connected to one end of the driving power supply lines PL1 to PLn through an output terminal Nt. Here, the source electrode and the drain electrode of the second power source control transistor PT2 may be switched according to the direction of the current.

Alternatively, the first power selection signals PSS1 to PSSn and the second power selection signals BPSS1 to BPSSn may not be provided from the timing controller 200, but may be provided from a separate power selection signal generator. The power selection signal generation unit generates the first power selection signals PSS1 to PSSn in response to the power control signal from the timing controller 200 and supplies the generated first power selection signals PSS1 to PSSn to the inverter circuit The second power selection signals BPSS1 to BPSSn can be generated.

The pixel driving voltage supplying unit 500 according to this example has the same structure as that of the pixel driving method in response to the first power selecting signals PSS1 to PSSn and the second power selecting signals BPSS1 to BPSSn And the high potential driving voltage EVDD_H and the low potential driving voltage EVDD_L are selectively supplied to the corresponding driving power supply lines PL1 to PLn and the role of the conventional emission control transistor and the high potential driving voltage (EVDD_H). Therefore, the pixel driving voltage supplier 500 according to the present embodiment increases the aperture ratio of the pixel P, thereby enabling the display panel 200 to have a high resolution.

FIG. 5 is a view for explaining a pixel driving voltage supply unit according to the example shown in FIG. 1, and FIG. 6 is a view for explaining the i-th voltage supply circuit shown in FIG.

Referring to FIG. 5, a pixel driving voltage supplier 500 according to an exemplary embodiment includes a plurality of voltage supply circuits 5101 to 510n connected to a plurality of driving power lines PL1 to PLn, respectively.

Each of the plurality of voltage supply circuits 5101 to 510n includes an output terminal Nt, a first voltage supply unit 511, a second voltage supply unit 513, a first power supply control transistor PT1, PT2). Hereinafter, the configuration of each of the plurality of voltage supply circuits 5101 to 510n will be described taking the i-th voltage supply circuit 510i as an example.

The output terminal Nt is electrically connected to one end of the i-th driving power supply line PLi.

The first voltage supply unit 511 supplies the internal node Ni with a high potential logic voltage Vdd supplied from the high potential logic voltage line to the internal node Ni in response to the node control signal NCS, To the logic voltage (Vdd). The first voltage supply unit 511 according to an example includes a first power supply transistor M1.

The first power supply transistor Ml is turned on or off by the node control signal NCS and is turned on by turning on the high potential logic voltage Vdd supplied from the high potential logic voltage line to the internal node No . The first power supply transistor M1 according to an example includes a gate electrode to which a node control signal NCS is supplied, a drain electrode connected to the high potential logic voltage line, and a source electrode connected to the internal node Ni. Here, the drain electrode and the source electrode of the first power supply transistor M1 may be mutually changed depending on the direction of the current.

The node control signal (NCS) may be an alternating voltage repeatedly circulated in a period of a low voltage and a high voltage or a direct voltage maintaining a constant voltage level. When the node control signal NCS is an AC voltage, the rising point of the high potential driving voltage EVDD_H output from the output node Nt can be adjusted.

Alternatively, the first power supply transistor M1 may have a diode connection structure in which a gate electrode and a drain electrode are coupled together to a high-potential logic voltage line. In this case, the node control signal NCS is omitted.

The second voltage supply unit 513 supplies the internal node Ni with a low potential logic voltage VL supplied to the low potential logic voltage line in response to the i-th power supply select signal PSSi, And discharges the voltage to a low-potential logic voltage line. The second voltage supply unit 513 according to one example includes a 2-1 power supply transistor M2a, a 2-2 power supply transistor M2b, and a 2-3 power supply transistor M2c.

The second power supply transistor M2a is turned on or turned on by the i-th power supply select signal PSSi and transmits a voltage between the internal node Ni and the intermediate node Nm at the turn-on time . The 2-1 power supply transistor M2a according to an example includes a gate electrode to which the i-th power supply select signal PSSi is supplied, a drain electrode connected to the internal node Ni, and a source electrode connected to the low potential logic voltage line . Here, the drain electrode and the source electrode of the (2-1) power supply transistor M2a may be switched according to the direction of the current.

The second-second power supply transistor M2b is turned on or turned on by the i-th power supply selection signal PSSi, and the low-potential logic voltage VL supplied to the low-potential logic voltage line at turn- And supplies it to the internal node Ni. The 2-2 power supply transistor M2b according to an example includes a gate electrode to which the i-th power supply selection signal PSSi is supplied, a drain electrode connected to the intermediate node Nm, and a source electrode connected to the low- . Here, the drain electrode and the source electrode of the second-second power supply transistor M2b may be switched according to the direction of the current.

The second power supply transistor M2c is turned on or turned on by the voltage of the internal node Ni and supplies the high potential driving voltage EVDD_H to the intermediate node Nm during turn- Thereby stably maintaining the turn-off state of each of the 2-1 power supply transistor M2a and the 2-2 power supply transistor M2b and preventing current leakage of the internal node Ni. The second power supply transistor M2c according to an exemplary embodiment includes a gate electrode connected to the internal node Ni, a drain electrode connected to the high potential driving voltage line to which the high potential driving voltage EVDD_H is supplied, And a source electrode connected to the source electrode. Here, the drain electrode and the source electrode of the second power supply transistor M2c may be switched according to the direction of the current.

The i-th power supply selection signal PSSi may have a gate-off voltage level only during an initialization period of the driving period of the pixels P provided in the i-th pixel column, and may have a gate-on voltage level during the remaining period. This i-th power supply selection signal PSSi may be provided from the gate driving circuit 400. [

The first power source control transistor PT1 is turned on or off by the voltage of the internal node Ni and outputs the high potential driving voltage EVDD_H at the output terminal Nt, And supplies a high potential driving voltage (EVDD_H) to the line PLi. The first power source control transistor PT1 according to an exemplary embodiment includes a gate electrode connected to the internal node Ni, a drain electrode connected to a high potential driving voltage line to which a high potential driving voltage EVDD_H is supplied, Source electrode.

The second power control transistor PT2 is turned on or off by the voltage of the internal node Ni and outputs the high potential driving voltage EVDD_H at the output terminal Nt at the turn- And supplies a high potential driving voltage (EVDD_H) to the line PLi. The first power source control transistor PT1 according to an example includes a gate electrode to which an i-th power source selection signal PSSi is supplied, a drain electrode connected to a low-potential driving voltage line to which a low-potential driving voltage EVDD_L is supplied, (Nt).

The pixel driving voltage supply unit 500 according to the present embodiment applies the driving power to the corresponding driving power lines PL1 to PLn in response to the power selection signals PSS1 to PSSn supplied to correspond to the driving period of the pixel P. [ And supplies the high potential driving voltage EVDD_H to each pixel P by selectively supplying the upper driving voltage EVDD_H and the low potential driving voltage EVDD_L. Therefore, the pixel driving voltage supplier 500 according to the present embodiment increases the aperture ratio of the pixel P, thereby enabling the display panel 200 to have a high resolution.

FIG. 7 is a view for explaining the gate driving circuit shown in FIG. 1, FIG. 8 is a waveform chart showing input / output signals of the gate driving circuit shown in FIG. 7, and FIG. Fig.

7 to 9, the gate driving circuit 400 according to an exemplary embodiment is connected to a plurality of gate lines GL1 to GLn in a one-to-one manner and connected to a pixel driving voltage supply unit, (ST1 to STn) selectively connected to a plurality of clock lines to which a plurality of carry shift clocks (CCLK1 to CCLK4) and a plurality of carry shift clocks (CCLK1 to CCLK4) are supplied.

Each of the plurality of gate shift clocks GCLK1 to GCLK4 cyclically repeats a high period having a gate on voltage level H of the transistor and a low period having a gate off voltage level L of the transistor at a constant period. The high period of each of the plurality of gate shift clocks GCLK1 to GCLK4 may be set to one horizontal period or less of the display panel 100, for example, two thirds of one horizontal period, . Each of the plurality of carry shift clocks CCLK1 to CCLK4 has the same form as that of each of the plurality of gate shift clocks GCLK1 to GCLK4 and is connected to one of the plurality of gate shift clocks GCLK1 to GCLK4, 2. For example, the first gate shift clock GCLK1 may be incremented after 1/2 of one horizontal period at the rising time of the first carry shift clock CCLK1.

Each of the first to n-th stages ST1 to STn is driven dependent on the gate start pulse Vst to output the scan pulse SP and the power source selection signal PSS. Here, the gate start signal Vst is supplied to the first stage ST1. Each of the second to n-th stages ST2 to STn receives the scan pulses SP1 to SPn-1 of the previous single stage ST1 to STn-1 as the gate start signal Vst. Each of the first to n-1 stages ST1 to STn-1 supplies the scan pulses SP2 to SPn output from the second to n-th stages ST2 to STn to the reset signal Vrst Receive.

Each of the first to n-th stages ST1 to STn according to an example includes a first output unit 410, a second output unit 430, a first node control unit 450, and a second node control unit 470 . Hereinafter, the configuration of each of the first to n-th stages ST1 to STn will be described taking the i-th stage STi as an example.

The first output unit 410 outputs the a-th gate shift clock GCLKa supplied from the corresponding gate shift clock line of the plurality of gate shift clock lines according to the voltage of the first node Q to the i-th scan pulse SPi And outputs the first gate-off voltage Vss1 according to the voltage of the second node QB.

The first output unit 410 according to an exemplary embodiment includes a first pull-up thin film transistor Tu1 for outputting a first gate shift clock GCLKa to the gate output node No1 in response to a voltage of the first node Q, And a first pull-down thin film transistor Td1 for outputting a first gate-off voltage Vss1 to the gate output node No1 in response to the voltage of the second node QB.

The first pull-up thin film transistor Tu1 includes a gate electrode connected to the first node Q, a drain electrode connected to the a-th gate shift clock line, and a source electrode connected to the gate output node No1. Here, the drain electrode and the source electrode may be mutually changed depending on the direction of the current. The first pull-up thin film transistor Tu1 is turned on according to the voltage of the first node Q to turn on the i-th scan pulse SPi made up of the a-th gate shift clock GCLKa to the gate output node No1, To the i-th gate line.

The first pull-down thin film transistor Td1 includes a gate electrode connected to the second node QB, a source electrode connected to the first gate-off voltage line to which the first gate-off voltage Vss1 is supplied, No1). Here, the drain electrode and the source electrode may be mutually changed depending on the direction of the current. The first pull-up thin film transistor Tu1 is turned on according to the voltage of the second node QB to supply the first gate-off voltage Vss1 to the i-th gate line via the gate output node No1 .

The second output unit 430 outputs the a-carry shift clock CCLKa supplied from the corresponding carry shift clock line among the plurality of carry shift clock lines according to the voltage of the first node Q, PSSi and outputs the second gate-off voltage Vss2 according to the voltage of the second node QB.

The second output unit 430 according to an exemplary embodiment includes a second pull-up thin film transistor Tu2 for outputting the a-carry shift clock CCLKa to the carry output node No2 in response to the voltage of the first node Q, And a second pull-down thin film transistor Td1 for outputting the second gate-off voltage Vss2 to the carry output node No2 in response to the voltage of the second node QB.

The second pull-up thin film transistor Tu2 includes a gate electrode connected to the first node Q, a drain electrode connected to the a-th carry shift clock line, and a source electrode connected to the carry output node No2. Here, the drain electrode and the source electrode may be mutually changed depending on the direction of the current. The second pull-up thin film transistor Tu2 is turned on in accordance with the voltage of the first node Q to turn on the i-th power supply control signal PSSi made up of the a-carry shift clock CCLKa to the carry output node No2 To the i < th > voltage supply circuit 500i of the pixel drive voltage supply unit 500 shown in Figs. 5 and 6.

The second pull-down thin film transistor Td2 includes a gate electrode connected to the second node QB, a source electrode connected to the second gate-off voltage line to which the second gate-off voltage Vss2 is supplied, No2). Here, the drain electrode and the source electrode may be mutually changed depending on the direction of the current. The second pull-up thin film transistor Tu2 is turned on according to the voltage of the second node QB to turn on the second gate-off voltage Vss2 via the carry output node No2 in Figs. 5 and 6 To the i < th > voltage supply circuit 500i of the pixel driving voltage supplier 500. [

The first node control circuit 450 is responsive to the gate start pulse Vst (or a previous output signal from any of the pre-previous stages) and a subsequent output signal from any of the following stages) Q) and the second node (QB).

The first node control circuit 450 according to an exemplary embodiment includes a first switching thin film transistor T1 for charging the first node Q with a high potential logic voltage Vdd in response to a gate start pulse Vst, And a second switching thin film transistor T2 for discharging the voltage of the first node Q to the third gate-off voltage Vss3 in response to the rear output Vrst from the first node Q2.

The first switching thin film transistor Tl constitutes a first set circuit for setting the voltage of the first node Q to a high potential logic voltage Vdd and the second switching thin film transistor T2 comprises a first node Q of the first reset circuit.

The second node control circuit 470 uses a high voltage VH and a low voltage VL to generate a voltage which is opposite to the voltage of the first node Q according to the voltage of the first node Q, (QB). The second node control circuit 450 according to one example may be configured as an inverter circuit.

8 and 9 with FIG. 6, the operation of the i-th stage according to an example will be described.

First, in the first period t1, the first node Q is driven by the high-potential logic voltage Vdd by the first thin film transistor T1 turned on in response to the start pulse Vst (or the front end output signal) And the voltage of the second node QB is discharged to the low voltage VL which is opposite to the voltage of the first node Q by the second node control circuit 470. [ Accordingly, the first pull-up thin film transistor Tu1 and the second pull-up thin film transistor Tu2 are turned on according to the voltage of the first node Q, The a-carry shift clock CCLKa having the i-th power supply selection signal PSSi through the second pull-up thin film transistor Tu2 and the carry output node No2, which are turned on, . Therefore, the i-th voltage supply circuit 500i supplies the low potential driving voltage EVDD_L to the i-th driving power supply line PLi according to the i-th power supply selecting signal PSSi. At this time, the first pull-up thin film transistor Tu1 turned on in accordance with the voltage of the first node Q is turned on when the gate-off voltage level L reaches the gate shift clock GCLKa through the gate output node No1 Th gate line.

Then, in the second period t2, the first node N1 is floated due to the turn-off of the first thin film transistor T1, and the a-gate shift clock GCLKa having the gate-on voltage level H, Is supplied to the drain electrode of the first pull-up thin film transistor Tu1 and the a-th carry shift clock CCLKa having the gate on voltage level H is supplied to the drain electrode of the second pull- . Accordingly, the voltage of the first node Q is amplified by the capacitor provided between the gate electrode and the source electrode of the first pull-up thin film transistor Tu1, so that the first pull-up thin film transistor Tu1 is more stable The second pull-up thin film transistor Tu2 is turned on to output the i-th scan pulse SPi having the gate-on voltage of the a-th gate shift clock GCLKa to the gate output node No1, And maintains the operating state of the first period (t1) according to the voltage of the first node (Q).

Subsequently, in the third period t3, as the a-gate shift clock GCLKa polls to the gate-off voltage, the voltage of the first node Q becomes higher than the high-potential logic GCLKa according to the polling of the a-gate shift clock GCLKa. And falls to the voltage Vdd. The first pull-up thin film transistor Tu1 and the second pull-up thin film transistor Tu2 maintain the turn-on state of each of the first pull-up thin film transistor Tu1 and the second pull-up thin film transistor Tu2 according to the voltage of the first node Q, The voltage level L is supplied to the i-th gate line via the gate output node No1 and at the same time the gate off voltage level L of the a-carry shift clock CCLKa is supplied to the i- Th voltage supply circuit 500i. Therefore, the i-th voltage supply circuit 500i supplies the high potential driving voltage EVDD_H to the i-th driving power supply line PLi according to the i-th power supply selecting signal PSSi.

Subsequently, in the fourth period t4, the voltage of the first node Q is lowered to the third gate-off voltage V2 by the second thin film transistor T2 turned on in response to the output signal Vrst (or the reset pulse) (Vss3) and the first and second pull-up thin film transistors Tu1 and Tu2 are turned off. At this time, the voltage of the second node QB is charged to the high voltage VH which is opposite to the voltage of the first node Q by the second node control circuit 470. Thus, each of the first and second pull-down thin film transistors Td1 and Td2 is turned on by the voltage of the second node QB, so that the first gate-off voltage Vss1 becomes the gate output node No1 And the second gate-off voltage Vss1 is supplied to the i-th voltage supply circuit 500i through the carry output node No2. Therefore, the i-th voltage supply circuit 500i supplies the high potential driving voltage EVDD_H to the i-th driving power supply line PLi according to the i-th power supply selecting signal PSSi of the second gate-off voltage Vss1.

The gate driving circuit 400 according to this embodiment generates scan pulses SP1 to SPn based on the plurality of gate shift clocks GCLK1 to GCLK4 and supplies the generated scan pulses SP1 to SPn to the gate lines GL1 to GLn, The power supply selection signals PSS1 to PSSn may be generated and supplied to the pixel driving voltage supplier 500 based on the carry shift clocks CCLK1 to CCLK4 of FIG. Accordingly, this example can simplify the circuit configuration for supplying the power supply selection signal to the pixel driving voltage supply unit 500 shown in FIG.

Fig. 10 is a diagram for explaining the gate driving circuit shown in Fig. 1, and Fig. 11 is a diagram showing the i-th stage shown in Fig. 10, which embeds the pixel driving voltage supply in the gate driving circuit.

10 and 11 are combined with FIG. 1, the gate driving circuit 400 according to the present example supplies a scan pulse to each of the plurality of gate lines GL1 to GLn, and supplies the pixel driving voltage EVDD to the plurality of driving power To each of the lines PL1 to PLn. That is, the gate driving circuit 400 supplies the pixel driving voltage EVDD to the plurality of driving power supply lines PL1 to PLn while driving the plurality of gate lines GL1 to GLn. The gate driving circuit 400 according to an exemplary embodiment generates scan pulses in accordance with a gate control signal GCS provided from the timing controller 200 and supplies the generated scan pulses to corresponding gate lines GL in a predetermined sequence, And supplies the generated pixel driving voltage to the corresponding driving power supply lines PL1 to PLn.

The gate driving circuit 400 according to the present embodiment is connected in one-to-one relation to a plurality of gate power lines PL1 to PLn while being connected in one-to-one relation to a plurality of gate lines GL1 to GLn, and a plurality of gate shift clocks GCLK1 to GCLK4 And first through n-th stages ST1 through STn selectively connected to a plurality of clock lines to which a plurality of carry shift clocks CCLK1 through CCLK4 are supplied.

Each of the first to n < th > stages ST1 to STn according to an example includes a gate signal generation unit 480 and a voltage supply circuit 490. [ Hereinafter, the configuration of each of the first to n-th stages ST1 to STn will be described taking the i-th stage STi as an example.

The gate signal generator 480 includes a first output unit 410, a second output unit 430, a first node controller 450, and a second node controller 470. The gate signal generator 480 having such a configuration has the same configuration as that of the i-th stage STi shown in FIG. 7, and a duplicate description thereof will be omitted.

The voltage supply circuit 490 includes an output terminal Nt, a first voltage supply unit 511, a second voltage supply unit 513, a first power supply control transistor PT1 and a second power supply control transistor PT2 . The voltage supply circuit 490 having such a configuration has the same configuration as that of the i-th voltage supply circuit 500i shown in FIG. 5, and a duplicate description thereof will be omitted.

The gate driving circuit 400 according to the present embodiment as described above supplies the high potential driving voltage EVDD_H and the low potential driving voltage EVDD_L to the plurality of driving power supply lines PL1 to PLn by embedding the pixel driving voltage supply unit The circuit configuration for the second embodiment can be further simplified.

12 is a view for explaining a light emitting display according to an example of the present application.

12, the light emitting display according to this example includes a display panel 100, a timing controller 200, a data driving circuit 300, a first gate driving circuit 400a, a second gate driving circuit 400b, A first pixel drive voltage supplier 500a, and a second pixel drive voltage supplier 500b.

Each of the display panel 100, the timing controller 200, and the data driver circuit 300 has the same configuration as the display panel, the timing controller, and the data driver circuit shown in FIG. 1, .

The first gate driving circuit 400a is provided in the left non-display region of the first substrate 210 together with the manufacturing process of the thin film transistor of the pixel P, The gate driving circuit 400 has the same configuration as that of the gate driving circuit 400, and a duplicate description thereof will be omitted.

The second gate driving circuit 400b is provided in the right side non-display region of the first substrate 210 along with the manufacturing process of the thin film transistor of the pixel P, And the gate driving circuit 400 shown in FIG. 1 and FIG. 7 to FIG. 11 except for that the gate driving circuit 400 shown in FIG.

The first pixel driving voltage supplier 500a is connected to one end of each of the plurality of driving power lines PL1 through PLn to selectively supply a high potential driving voltage and a low potential driving voltage to the plurality of driving power lines PL1 through PLn, And it has the same configuration as the pixel driving voltage supplier 500 shown in FIG. 4 to FIG. 6, so that a duplicate description thereof will be omitted. Alternatively, the first pixel drive voltage supply part 500a may be embedded in the first gate drive circuit 400a as shown in FIGS.

The second pixel driving voltage supplier 500b is connected to the other end of each of the plurality of driving power lines PL1 to PLn to selectively supply a high potential driving voltage and a low potential driving voltage to the plurality of driving power lines PL1 to PLn, And it has the same configuration as the first pixel drive voltage supplier 500a, and thus a duplicate description thereof will be omitted. Alternatively, the second pixel driving voltage supply part 500b may be embedded in the second gate driving circuit 400b as shown in FIGS.

The light emitting display device according to this example as described above supplies the high potential driving voltage EVDD_H and the low potential driving voltage EVDD_L on both sides of the plurality of driving power supply lines PL1 to PLn to the plurality of driving power supply lines PL1 to PLn, PLn) can be minimized.

13 is a driving waveform diagram for explaining the driving method of the pixel shown in FIG.

Referring to FIG. 13 and FIG. 4, a method of driving a pixel according to an exemplary embodiment of the present invention will be described.

First, the pixel P may be driven in the initialization period Ti, the sampling period Ts, the data addressing period Tw, and the light emission period Te.

In the initialization period Ti, a constant voltage is applied to the capacitor Cst between the first node N1 and the second node N2. That is, the low potential driving voltage EVDD_L is supplied to the driving power supply line PLi according to the power source selection signal, and the initialization thin film transistor Tini is turned on according to the (i-1) th scanning pulse SPi- And initializes the capacitor Cst by supplying the voltage Vini to the first node N1.

Then, in the sampling period Ts, the initialization voltage Vini supplied to the first node N1 is maintained as it is by maintaining the turn-on state of the initialization thin film transistor Tini, And supplies the high potential driving voltage EVDD_H to the capacitor PLi to sample the threshold voltage of the driving thin film transistor Tdr into the capacitor Cst. That is, since the voltage of the first node N1 is maintained at the initializing voltage Vini and the voltage of the second node N2 is increased to the initializing voltage Vdd due to the high potential driving voltage EVDD_H supplied to the driving power supply line PLi Vini between the threshold voltage of the driving thin film transistor Tdr and the threshold voltage of the driving thin film transistor Tdr so that the voltage corresponding to the threshold voltage of the driving thin film transistor Tdr is stored in the capacitor Cst.

Then, in the data addressing period Tw, the initial thin film transistor Tini is turned off according to the (i-1) th scan pulse SPi-1, the switching thin film transistor Tini turned on according to the i- (Vdata) to the first node (N1) through the second node (Tsw). Accordingly, a voltage corresponding to Va (Vdata-Vini) + Vth is induced in the capacitor Cst by coupling between the stored voltage and the data voltage. Here, Va is an auxiliary voltage applied to the auxiliary capacitor.

In the light emission period Te, the driving thin film transistor Tdr is turned on by the voltage induced in the capacitor Cst so that the voltage of the second node N2 rises, The voltage of the first node N1 is raised by the coupling of the voltage of the second node N2 when the switching thin film transistor Tsw is turned off according to the voltage level SPi of the capacitor Cst, The turn-on state of the driving thin film transistor Tdr is maintained by the voltage so that the light emitting element ELD emits light in the initializing period Ti of the next frame.

The light emitting display according to this example can compensate the threshold voltage of the driving thin film transistor Tdr by storing the threshold voltage of the driving thin film transistor Tdr in the capacitor Cst during the sampling period Ts, By adjusting the initialization period (Ti) and the sampling period (Ts) through the selection signal, the sum period of the initialization period (Ti) and the sampling period (Ts) can be secured over one horizontal period, Do.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the scope of the present application is to be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present application.

100: display panel 200: timing controller
300: Data driving circuit 400: Gate driving circuit
410: first output unit 430: second output unit
450: first node controller 470: second node controller
480: Gate signal generator 490: Voltage supply circuit
500: Pixel driving voltage supply unit 511: First voltage supply unit
513: Second voltage supply unit

Claims (12)

A display panel including a plurality of pixels each provided in a pixel region defined by a plurality of gate lines, a plurality of data lines, and a plurality of driving power supply lines aligned with the gate lines;
A data driving circuit for supplying a data voltage corresponding to each of the plurality of data lines;
A gate driving circuit for supplying a scan pulse to each of the plurality of gate lines;
And a pixel driving voltage supply unit connected to at least one of the one end and the other end of each of the plurality of driving power supply lines and selectively supplying a high potential driving voltage and a low potential driving voltage to each of the plurality of driving power supply lines,
And pixel lines provided along the longitudinal direction of the gate lines share adjacent driving power lines. The method according to claim 1,
Wherein each of the plurality of pixels comprises:
A pixel circuit connected to a gate line, a data line, and a driving power supply line adjacent to the pixel region; And
And a light emitting element connected between the pixel circuit and the common power supply electrode. 3. The method of claim 2,
The pixel circuit includes:
A switching thin film transistor having a gate electrode connected to the gate line, a first electrode connected to the data line and a second electrode connected to the first node;
A driving thin film transistor having a gate electrode connected to the first node, a drain electrode connected to the driving power supply line, and a source electrode connected to the light emitting element through a second node; And
And a capacitor formed between the first node and the second node. 3. The method of claim 2,
The display panel further comprises a plurality of initialization voltage lines arranged in parallel with each of the plurality of data lines,
The pixel circuit includes:
A switching thin film transistor having a gate electrode connected to the gate line, a first electrode connected to the data line and a second electrode connected to the first node;
An initialization thin film transistor having a gate electrode connected to the previous gate line, a first electrode connected to the initialization voltage line, and a second electrode connected to the first node;
A driving thin film transistor having a gate electrode connected to the first node, a drain electrode connected to the driving power supply line, and a source electrode connected to the light emitting element through a second node; And
And a capacitor formed between the first node and the second node. 5. The method of claim 4,
Wherein each of the plurality of pixels is driven by an initialization period, a sampling period, a data addressing period, and a light emission period,
Wherein the pixel driving voltage supply unit includes:
Supplying a low potential driving voltage to the driving power supply line during the initialization period,
And supplies a high potential driving voltage to the driving power supply line during the sampling period, the data addressing and the light emission period. 6. The method of claim 5,
Wherein the pixel driving voltage supply unit includes a plurality of voltage supply circuits connected to each of the plurality of driving power supply lines,
Wherein each of the plurality of voltage supply circuits comprises:
A first power supply control transistor for supplying the high potential driving voltage to a corresponding driving power supply line during the sampling period, the data addressing period and the light emission period according to a first power supply selection signal; And
And a second power supply control transistor for supplying the low potential driving voltage to a corresponding driving power supply line only during the initialization period according to a second power supply selection signal. 6. The method of claim 5,
Wherein the pixel driving voltage supply unit includes a plurality of voltage supply circuits connected to each of the plurality of driving power supply lines,
Wherein each of the plurality of voltage supply circuits comprises:
An output terminal connected to the corresponding driving power supply line;
A first voltage supply for supplying a high potential logic voltage to the internal node;
A second voltage supply for supplying a low potential logic voltage to the internal node in response to the power supply selection signal;
A first power supply control transistor for supplying the high potential driving voltage to the output terminal in response to a voltage of the internal node; And
And a second power source control transistor which supplies the low potential driving voltage to the output terminal in response to the power source selection signal. 8. The method of claim 7,
Wherein each of the initialization period and the sampling period has a first period and a second period,
The initializing thin film transistor is turned on only during a second period of the initialization period and a first period of the sampling period,
The switching thin film transistor is turned on in the data addressing period,
The first power control transistor is turned on during the sampling period, the data addressing period and the light emitting period,
And the second power source control transistor is turned on during the initialization period. 9. The method of claim 8,
Wherein the first voltage supply comprises a first transistor for supplying a high potential logic voltage to the internal node in response to a node control signal, 9. The method of claim 8,
Wherein the second voltage supply unit includes:
A 2-1 transistor for connecting the internal node to an intermediate node according to the power supply selection signal;
A second 2-2 transistor for supplying the low potential logic voltage to the intermediate node according to the power supply selection signal; And
And a second thin film transistor for supplying the high potential driving voltage to the intermediate node in accordance with the voltage of the internal node. 11. The method according to any one of claims 7 to 10,
Wherein the gate drive circuit includes a plurality of stages,
Wherein each of the plurality of stages includes:
A first output unit for outputting a gate shift clock supplied from one of the plurality of gate shift clock lines according to a voltage of the first node as the scan pulse and outputting a gate off voltage according to a voltage of the second node;
A second output unit for outputting a carry shift clock supplied from one of the plurality of carry shift clock lines according to a voltage of the first node to the power supply selection signal and outputting a gate off voltage according to a voltage of the second node;
A first node controller for controlling the voltage of the first node based on a scan pulse output from the previous stage; And
And a second node control unit for controlling the voltage of the second node based on the voltage of the first node. 12. The method of claim 11,
Wherein the pixel driving voltage supply unit is built in the gate driving circuit,
And the plurality of voltage supply circuits are connected one-to-one with the plurality of stages.

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