KR20180078603A - Read-out integrated circuit - Google Patents

Abstract

The configuration of the present invention includes an integration circuit for integrating the detected charge signal, an LPF & Sampling (track-and-hold) circuit for sampling the waveform at the same time as noise removal, A control signal generating unit for performing the operation, and a memory for storing the calculation value derived from the arithmetic operation unit.

Description

A read-out integrated circuit

The present invention relates to a detection circuit.

Referring to FIG. 1, an X-ray detector using a conventional TFT flat panel is equipped with a CMOS readout IC at the outer edge of the panel to detect a signal charge generated in the photodiode.

Referring to FIGS. 2 and 3, the charge amplifier of each channel of the detection circuit integrates (accumulates) the signal charge of the pixel and converts it into a voltage.

A low-pass filter is built in each detector circuit so as to effectively reduce the noise of the white noise characteristic caused by each pixel included in the signal source converted into the voltage from the charge detector and the white noise characteristic caused by the detection circuit, Prevent degradation.

A correlated double sampling (CDS) noise reduction technique with a sampling switch and a capacitor is additionally used to eliminate low-frequency noise and DC-offset errors in the low-pass filter.

The low-pass filter (LPF) limits the degree of change of the signal within a specific frequency band, thereby suppressing the degree of change of the signal source having a high rate of change, thereby suppressing high frequency noise. By suppressing the high frequency noise contained in the signal source, it greatly reduces the influence of noise, preventing the sensitivity drop caused by high frequency noise.

CDS (correlated double sampling) samples the output voltage of the detection circuit of the initial-state before charge integration just after reset through sample1, samples the output voltage output from the detection circuit after integration of the charge signal through sample2, By taking the difference between the values, the DC offset error of the detection circuitry is removed and a high-pass filter (HPF) function is performed to eliminate low frequency noise according to the period of two sampling intervals.

In order to obtain high accuracy in the LPF, each sampling time has an additional sampling time of Ts settling time, and the cycle Tcds of the completion of the sampling operation of the CDS should be set to be equal to or greater than the sum of Ts generated by Tint and LPF .

The cut-off frequency in LPF is determined by 1 / RC, and the cut-off frequency of HPF formed by CDS is determined by 2x (1 / Tcds).

The high accuracy and the operation speed of the detection circuit part form a trade-off relationship with each other, since the TL (1 Row Line time) of one row has a relation of increasing proportionally as Ts is increased for high accuracy. If Ts is used, the sensitivity of the detection circuit system is reduced due to the influence of low frequency noise. Therefore, proper coordination between Ts or Tcds and TL is required.

Although the low-pass filter formed by the RC network has the infinite period to reach the final value theoretically, and to reduce the infinite period to a finite period to obtain the desired accuracy, the RC time constant And it requires a long settling time of about 11 times that of

In order to have a high high-frequency noise removal bandwidth, the sampling capacitor constituting the RC time-constant must be largely constituted, which is unreasonable in terms of layout in the integrated circuit design.

Increased Ts to obtain high accuracy significantly reduces the speed of the detection system by the proportionally increasing TL, which is a critical limitation in constructing a detection system that requires high speed such as moving images.

The increase in Ts also reduces the cut-off frequency of the HPF formed by the CDS, thereby reducing the CDS low-frequency noise attenuation and ultimately attenuating the sensitivity of the detection system.

Due to the above problems, the accuracy and speed of the detection system and the low and high frequency noise reduction characteristics are tightly bound to each other in the trade-off relationship, so that there is a limit to improving the characteristics of each other individually.

SUMMARY OF THE INVENTION The present invention has a problem to improve the influence of noise on the output portion of the signal detecting circuit including the LPF and to greatly improve the operation speed of the detecting circuit.

The configuration of the present invention includes an integration circuit for integrating the detected charge signal, an LPF & Sampling (track-and-hold) circuit for sampling the waveform at the same time as noise removal, A control signal generating unit for performing the operation, and a memory for storing the calculation value derived from the arithmetic operation unit.

According to the present invention, it is suitable for constructing a video system such as a moving picture X-ray which requires a high system speed due to improvement of the operation speed of the signal detection circuit (ROIC).

Improvement of sensitivity of X-ray detector due to improved performance of noise elimination.

In the case of a moving image X-ray system in which a continuous dose is to be injected, the speed increase of the signal detection system such as the present invention provides an effect of greatly reducing the irradiation time of the X-ray dose to the patient.

Compared with the conventional system, the reduction of the layout area of the circuit part is expected to reduce the production cost according to the final design structure.

Compared to competitors, it has strong competitiveness due to its suitability for video X-ray system, low noise, high sensitivity, low dose, and cost saving effect.

Figures 1 to 5 are diagrams related to the prior art.
Figures 6-26 relate to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

6 is a CMOS signal detection circuit in which an LPF corresponding to one channel is inserted and can accommodate multiple channels.

The detection circuit including the LPF includes an "integration circuit portion" that integrates the detected charges connected to each channel of the TFT pixel matrix, a common resistance (Rcommon) for constituting the RC network, and an input signal of the charge integration circuit portion , "LPF & Sampling", which consists of several capacitors that follow the sampling of the input signal, and "Arithmetic operation part" which integrates the existing data with the currently measured data. Finally, Control unit ", and a" data memory unit "for storing and storing the signal data output through the existing LPF.

Each single sampling unit corresponding to "LPF & Sampling Unit" tracks and momentarily keeps momentary moment of the output waveform of the integration circuit unit at a constant interval according to the signal synchronized with the system timing clock of the corresponding system, The integration value of the signal can be obtained by CDS processing the sampling capacitor.

The arithmetic operation unit calculates the RC time constant factor related to the RC network of the channel through the data obtained from the sampling unit. By using the RC-related factor, only the initial value data of the waveform measured in the normal operation process in the future is collected, Final value is calculated.

The first operation (Mode 1) is to obtain a factor related to the time constant of the LPF RC network corresponding to each channel of the signal detection circuit. The second operation (Mode 2) In the operation of detecting a general charge, only a part of the follow-up value is measured and the final value is predicted.

In order to clearly distinguish the two modes divided by the operation method of the present invention, the name is temporarily referred to herein as a first mode 1 as a preset mode and a second mode 2 as a normal mode.

Preset mode can be performed either at the beginning of the operation independently of the normal mode or immediately before the execution of the normal mode according to the user's selection, and it is an operation mode added for the invention, Must be executed more than once.

In all modes, all nodes of the integration circuit and LPF & Sampling are set to the reference voltage level through the INTRST switch just before operation.

In the preset mode, a specific test charge according to the user's selection is applied and the integration circuit outputs the voltage to the LPF & Sampling unit according to the amount of applied charge. As the potential of the output part rises due to the integration circuit part, the voltage is sequentially stored in the sampling capacitor for each specific clock synchronized. Then, the sampled value is taken into the CDS among the adjacent capacitors, converted into a factor related to the RC time constant through an external arithmetic operation device, and the value is stored in the memory.

The normal mode is the most common operation mode that operates in the same situation as the conventional system. When the charge is applied to the integration circuit part according to the amount of the external signal, the voltage signal is outputted to the LPF & Sampling part according to the applied value. Here, in the conventional system, the sampling voltage of the integration circuit portion and the final settling value of the integration circuit portion are sampled to the sampling capacitor and the value is read to the CDS. In the proposed method, however, Sampling is performed several times on different sampling capacitors per specific clock, and the values are read. The value read here is combined with the factor obtained in Preset Mode to calculate the final value.

The synchronized specific clock emphasized in both of the above is the sampling period determined by the user. The sampling period should be the same value in Preset Mode and Normal Mode, and this sampling period is controlled by the internal signal controller being.

The output waveform of all the signals obtained from the same RC network form the same low-frequency pass characteristic bandwidth having a cutoff frequency of 1 / RC, that is, the characteristic that suppresses unnecessary high frequency change amounts is attributed to the RC network Therefore, waiting for a long time in the RC network to obtain a certain level of accreditation without changing amount is an analog trade-off cost to be sacrificed by using the RC network, and the wait time for setting a specific signal Since the compliance itself is not an essential element to eliminate the noise, if you can use the same RC network to estimate the final value without the wait time, only the trend of the initial waveform changes, the unnecessary wait time for high accuracy The noise bandwidth can be maintained as it is. .

Referring to FIG. 7, the basic RC network shows the following time response for the following input signals. If the current time t, time t and output value Vout according to time t and the RC time constant value constituting the RC network are known in advance, the signal value Vin initially applied can be known.

FIG. 8 is a schematic diagram for obtaining the time constant (RC) of the signal detection circuit in which the LPF is inserted. When a specific signal is applied to the input of the signal detection circuit, (Or synchronize to a specific clock), and keep track & hold the value output from the signal detection circuit to the sampling capacitor at regular intervals according to the predefined period. Since the output value Vout according to the constant time t is known in advance and the specific signal value Vin is also known, the LPF can obtain the RC time constant.

9 to 11, the CDS scheme is a technique for reading low frequency noise / offset error by reading the difference value of the track and hold values of two adjacent capacitors together. In the CDS scheme, two adjacent sampling In order to apply CDS to a capacitor, a sampling time (T _CDS ) including an integration time (Tint) in which a charge is injected into a charge integration circuit and an addition of a settling time (Ts) due to an LPF is required. The CDS operation system of the discrete region is developed by the Z-transform and then re-developed in the frequency domain. The CDS system with the LPF applied is developed as follows.

The meaning of the equation is that the longer the integration time and the settling time, the wider the frequency region to pass the low-frequency signal in the frequency domain. This means that it allows low-frequency noise input. In the present invention, by greatly reducing the time corresponding to Ts, the size of the Tcds is greatly reduced, and the influence of the low noise is largely restrained by greatly reducing the influence of the low noise.

FIG. 12 shows an integrated circuit part and an LPF & Sampling part, which can be designed to apply the method of the present invention.

The corresponding detection circuit with LPF consists of one common LPF resistor, one large main capacitor, and a relatively small number of sub-capacitors in parallel to form an LPF & Sampling circuit.

Since the number of sub-sampling capacitors is smaller than that of the main sampling capacitor, the RC time constant formed by the LPF & Sampling unit can be approximated by Rcommon * Cmain.

In order to obtain the RC time constant factor in Preset Mode, various offset errors that may occur in the signal detection circuit should be considered. Therefore, considering the various possible errors, the RC time constant factor is obtained using the following equation.

The embodiment is operated in two modes of Preset Mode and Normal Mode. It is necessary to execute Preset Mode more than once before Normal Mode is executed, and the output waveform of the integration circuit portion to be sampled for each mode is as shown in FIG.

In the circuit of FIG. 14, which is an example of the operation mode, the LPF & Sampling section consists of one main capacitor and four sub capacitors.

[Preset Mode]

Referring to FIG. 15, the potential of all nodes is set to Vref through a reset operation (INTRST, all SWsub ON) before detecting a specific test signal.

Turn off the INTRST switch and turn on the Inject switch to integrate the charge of the test signal source.

Sampling is performed on the first sub-sampling capacitor by turning off the SWsub1 switch at the moment of completion of the integration when the injection switch is turned off. (V0 sampling)

Then, the output waveforms are sampled by turning off the switches SWsub2 and SWsub3, respectively, at a predetermined time interval according to the synchronized clock. (V1, V2 sampling)

Finally, the final sampling is performed by turning off Vin SWsub4 after a sufficiently long integration time (16-bit base 11tau) to match the ADC accuracy. (Vin sampling)

V0 and Vin values, and V1 and V2 values are read by CDS method, respectively. Then, they are integrated together, or the RC factor is calculated through the calculation of an arithmetic operation unit existing in the outside, and the corresponding factor value is stored in the memory.

The preset factor obtained through the Preset Mode can be calculated by the following equation.

[Normal Mode]

16, before the signal of each pixel is detected, the potential of all nodes is set to Vref through the reset operation (INTRST, SWsub ON), and the Vref potential is sampled to the first sub-sampling capacitor by turning off the SWsub1 switch . (Vref sampling)

Turn off the INTRST switch and turn on the Inject switch to integrate the charge from the pixel source.

Sampling is performed on the third sub-sampling capacitor by turning off the SWsub3 switch at the moment of completion of integration where the injection switch is turned off. (V0 sampling)

The output waveforms are then sampled on the second and fourth subsampling capacitors by turning off SWsub2, SWsub4, and SWsub4, respectively, at constant time intervals according to the synchronized clock. (V1, V2 sampling)

Vref and V0 values, V1 and V2 values are read by CDS method, and the factor obtained in Preset Mode is taken out from the memory, and then integrated together or predicted final settling value using an external arithmetic unit. .

The calculated value obtained through the corresponding Normal Mode is used as follows to obtain the final value.

Detailed sequences for each clock synchronized to the Preset Mode and the Normal Mode are specifically indicated in the embodiment.

In this embodiment, a common LPF resistor, a large main capacitor, and a plurality of sub capacitors constitute an LPF & Sampling circuit.

The operation sequence of the embodiment is described above.

The sequence of FIG. 19 is based on the preset mode.

The sequence of FIG. 20 is based on Normal Mode.

In the present invention, a pipeline operation can be used according to the user's desire for continuous signal detection of the signal detection circuit unit. Further, a plurality of additional sub-sampling capacitors for further sampling a plurality of Row of pixels corresponding to each channel It is possible to add. See FIGS. 21 and 22 in this regard.

Referring to FIG. 23, by reducing the sampling period in comparison with the prior art, the high frequency noise removal characteristic is the same as that of the prior art, while having a fast signal detection speed.

Referring to FIG. 24, the CDS operation period Tcds is also reduced due to a significantly reduced sampling period Ts compared with the prior art, thereby further increasing the range of the low frequency noise removed through the CDS operation.

Referring to FIG. 25, in comparison with a conventional circuit using two large capacitors for each row of channels for CDS operation to improve the noise canceling characteristic, the proposed circuit has a large main capacitor and a plurality of small sub capacitors The position preemption is more advantageous in terms of semiconductor layout due to the use of the dog. Maximize the benefits of that method when you need to perform a preliminary Row sampling operation for pipeline operation.

It is suitable for constructing video systems such as video X-ray which requires fast system speed due to improvement of operation speed of signal detection circuit (ROIC).

Improvement of sensitivity of X-ray detector due to improved performance of noise elimination.

In the case of a moving image X-ray system in which a continuous dose is to be injected, the speed increase of the signal detection system such as the present invention provides an effect of greatly reducing the irradiation time of the X-ray dose to the patient.

Compared with the conventional system, the reduction of the layout area of the circuit part is expected to reduce the production cost according to the final design structure.

Compared to competitors, it has strong competitiveness due to its suitability for video X-ray system, low noise, high sensitivity, low dose, and cost saving effect.

Fig. 26 shows the result of the simulation (the sampling rate is reduced by 8 times or more as compared with the conventional system based on the 12-bit Accuracy).

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

Claims (7)

An integration circuit connected to the channel of the TFT pixel matrix to integrate the detected charge;
A common resistor connected at one end to the output terminal of the integrating circuit and a plurality of capacitors connected in parallel at the other end of the common resistor to constitute an RC network and to sequentially sample and output signals output from the integrating circuit, Wealth;
An arithmetic operation unit for reading a sampled signal from the plurality of capacitors by a correlated double sampling (CDS)
≪ / RTI >
The method according to claim 1,
Wherein the LPF sampling unit further includes a plurality of sub capacitors as the plurality of capacitors and a main capacitor connected in parallel with the plurality of sub capacitors and having a larger capacity than the plurality of sub capacitors,
Wherein each of the plurality of sub-capacitors is connected to the common resistor through a switch,
The main capacitor is connected directly to the common resistor
Detection circuit.
The method according to claim 1,
The arithmetic operation unit,
Calculating a RC time factor of the channel through a sampled signal of the plurality of capacitors in a preset mode,
In the normal mode, the RC time constant factors are combined with the sampled signals of the plurality of capacitors to calculate an output value
Detection circuit.
The method of claim 3,
Wherein the sampling cycles of the plurality of capacitors in the preset mode and the normal mode are the same
Detection circuit.
The method of claim 3,
A memory unit for storing the RC time constant factor;
≪ / RTI >
The method of claim 3,
In the preset mode,
Wherein the integration circuit part receives and integrates a test signal,
The first capacitor samples the potential output from the integration circuit portion at the moment when the input of the test signal is terminated,
The second and third capacitors sample the potentials output from the integration circuit section at a first time interval according to the synchronized clock after sampling of the first capacitor,
The fourth capacitor samples the potential output from the integration circuit part at a second time longer than the first time after sampling the third capacitor
Detection circuit.
The method of claim 3,
In the normal mode,
The first capacitor samples the reference potential output from the integration circuit portion in the reset state,
Wherein the integration circuit unit receives and integrates a signal from the channel after the reset state,
The third capacitor samples the potential output from the integration circuit portion at the moment when signal input to the channel is terminated,
The second and fourth capacitors sample the potentials output from the integration circuit section at predetermined time intervals according to the synchronized clock after sampling of the third capacitor
Detection circuit.

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