KR20180036449A - Organic Light Emitting Display - Google Patents

Abstract

The present invention relates to an organic light emitting display device, which comprises a pixel array, a light emitting control signal generating unit, and a scan signal generating unit. In the pixel array, pixels including an organic light emitting diode, a scan line connected to the pixels and an emission line are arranged. The light emitting control signal generating unit applies a light emitting control signal to the emission line during a light emitting period; the scan signal generating unit applies a scan signal to the scan line in a period other than the light emitting period; and the scan signal generating unit includes a plurality of scan signal stages which are dependently connected to each other. At least one of the scan signal stages includes: a start control transistor for maintaining the Q node at a low potential voltage in response to a voltage of a start signal input terminal; a pull-up transistor including a gate connected to the Q node, a source electrode for receiving a clock signal, and a drain electrode connected to an output terminal; and a Q node control transistor including a gate electrode connected to a QB node, a source electrode connected to the Q node, and a drain connected to an input terminal of a high potential voltage. The QB node directly receives the light emitting control signal, and the gate electrode of the Q node control transistor receives a turn-on voltage during the light emitting period.

Description

[0001] The present invention relates to an organic light emitting display,

The present invention relates to an active matrix type organic light emitting display.

The organic light emitting device OLED, which is a self-luminous device, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light. An active matrix type organic light emitting display includes various organic light emitting diodes (OLEDs) that emit light by themselves, and are widely used because of their high response speed, light emitting efficiency, brightness, and viewing angle.

The organic light emitting display device arranges the pixels each including the organic light emitting diode in a matrix form and adjusts the brightness of the pixels according to the gradation of the video data. Each of the pixels includes a driving transistor for controlling the driving current flowing in the organic light emitting diode according to the gate-source voltage, and at least one switch transistor for programming the gate-source voltage of the driving transistor. The driving current is determined by the gate-source voltage of the driving transistor according to the data voltage and the threshold voltage of the driving transistor, and the luminance of the pixel is proportional to the magnitude of the driving current flowing through the organic light emitting diode.

Due to the characteristics of the manufacturing process, each of the driving transistors formed in the pixels deviates from the threshold voltage (Vth). The current supplied to the organic light emitting diode may be different from the designed value due to the deviation of the threshold voltage of the driving transistor, and accordingly, the luminance to emit light may be different from the desired value. In order to compensate this, the organic light emitting diode adopts a driving method in which a data voltage is applied after a sampling period for detecting a threshold voltage of a driving transistor. To detect the threshold voltage of the driving transistor, pixels require a number of transistors to control the sampling operation. Therefore, a scan signal or emission control signal for controlling each of the transistors is required.

A gate driver for generating scan signals or emission control signals may be implemented as a gate-in-panel (GIP) type in a display panel. In the OLED display device, the number of scan signals or emission control signals for controlling pixels increases, so that the size of a gate driver implemented in a GIP form increases, resulting in an increase in the number of bezels of the display panel.

The present invention provides an organic light emitting display capable of reducing a bezel.

According to an aspect of the present invention, there is provided an organic light emitting display including a pixel array, a light emission control signal generator, and a scan signal generator. In the pixel array, pixels including an organic light emitting diode, a scan line and an emission line connected to the pixels are disposed. The light emission control signal generator applies the light emission control signal to the emission line during the light emission period. The scan signal generating unit applies a scan signal to the scan line in a period other than the light emission period. The scan signal generating unit includes a plurality of scan signal stages to which the scan signal generating unit is connected. At least one of the scan signal stages includes a start control transistor for maintaining the Q node at a low voltage in response to the voltage at the start signal input terminal, a gate connected to the Q node, a source electrode for receiving a clock signal, And a Q node control transistor including a gate connected to the QB node, a source electrode connected to the Q node, and a drain connected to the high potential voltage input terminal. The QB node directly receives the emission control signal, and the gate electrode of the Q node control transistor receives a turn-on voltage during the emission period.

According to the embodiments of the present invention, the scan signal stage can stably maintain the Q-node voltage in a section where the number of transistors is not increased and the scan signal is not output. As a result, the present invention can stably output the scan signal while reducing the size of the bezel.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
2 is an equivalent circuit diagram of a pixel according to the present invention.
3 is a diagram showing the timing of driving signals for driving a pixel.
4A to 4C are equivalent circuit diagrams of pixels according to a driving period.
5 is a view showing a shift register according to the present invention.
6 shows a part of the emission control signal stage and the scan signal stages;
7 is a circuit diagram showing a configuration of a scan signal stage according to the first embodiment.
8 is a timing chart of driving signals and output signals for driving the scan signal stage shown in FIG.
9 is a circuit diagram showing a configuration of a scan signal stage according to the second embodiment.
10 is a circuit diagram showing a configuration of a scan signal stage according to the third embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The switching elements in the pixels and the shift register of the present invention may be implemented as transistors of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. In the following embodiments, a p-type transistor is exemplified, but it should be noted that the present invention is not limited to this. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following embodiments, the invention should not be limited to the source and drain of the transistor.

In addition, the turn-on voltage in this specification refers to the operating voltage of the transistor. Since the present specification describes a p-type transistor as an embodiment, it defines a low potential voltage as a turn-on voltage.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.

1, the OLED display includes a display panel 100 on which pixels P are formed, a data driver 120 for driving the data lines DL1 to DLm, And a timing controller 110 for controlling the driving timings of the gate driver 130, the data driver 120 and the gate driver 13 for driving the lines EML and SL.

The display panel 100 includes a pixel array 100A and a non-display area 100B. In the pixel array 100, a plurality of pixels P are arranged in a matrix form. The pixels P can be commonly supplied with the high and low potential driving voltages VDD and VSS and the initializing voltage Vini from a power source not shown. The initialization voltage Vini may be selected within a voltage range sufficiently lower than the operation voltage of the organic light emitting device OLED so that unnecessary light emission of the organic light emitting device OLED is prevented in the initial period and the sampling period. That is, it may be set to be equal to or lower than the low-potential driving voltage VSS. Therefore, by applying a voltage lower than the initialization voltage Vini and the low-potential driving voltage VSS in the initial period, the lifetime of the organic light emitting diode OLED can be improved.

The transistors (TFTs) constituting the pixel P may be implemented with a transistor including an oxide semiconductor layer. The oxide semiconductor layer is advantageous for large-sized display panel 100 in consideration of both electron mobility and process variations. When formed of an oxide semiconductor, it may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO). However, the present invention is not limited to this, and the semiconductor layer of the transistor may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

The timing controller 110 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 100 and supplies the digital video data RGB to the data driver 120. The timing controller 110 is also connected to the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver 130 are generated.

The data driver 120 converts the digital video data RGB input from the timing controller 110 into an analog data voltage based on the data control signal DDC.

The gate driver 130 may generate a scan signal and a light emission control signal based on the gate control signal GDC. The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in an IC form. The level shifter 130 level-shifts the gate control signals and supplies them to the shift register 140. The shift register 140 includes a plurality of stages that are connected in a dependent manner. The shift register 140 may be formed directly in the non-display area 100B of the display panel 100 according to a gate-driver in panel (GIP) scheme.

2 is a diagram showing the pixel structure of the pixels arranged in the i-th horizontal line. In FIG. 2, the gate electrode of the fifth transistor T5 receives the (i-1) th scan signal. If the pixels arranged in the ith pixel line are pixels arranged in the first horizontal line, the fifth transistor T5 can be controlled using a dummy scan signal which is not connected to the pixels in the pixel array 100A .

Referring to FIG. 2, a detailed configuration of the pixel will be described below.

Each of the pixels PXL includes an organic light emitting diode (OLED) driving transistor DT, first through sixth transistors T1 through T6, and a capacitor Cst.

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the organic light emitting diode OLED. The organic compound layer may include at least one hole transporting layer, an electron transporting layer, and an emission layer (EML). Here, the hole transport layer is a layer that injects holes into the light emitting layer or transmits holes, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer blocking layer, EBL). The electron transport layer is a layer for injecting electrons into the light emitting layer or for transporting electrons, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer blocking layer, HBL). The anode electrode of the organic light emitting diode OLED is connected to the fourth node N4 and the cathode electrode of the organic light emitting diode OLED is connected to the input terminal of the low potential driving voltage VSS.

The driving transistor DT controls the driving current applied to the organic light emitting element OLED according to its source-gate voltage Vsg. The source electrode of the driving transistor DT is connected to the first node N1, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

The first transistor T1 includes a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode connected to the ith scan line SLi. The first transistor T1 is diode-connected to the gate-drain electrode of the driving transistor DT in response to the i-th scan signal SCAN [i].

The second transistor T2 includes a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to the ith scan line SLi. As a result, the second transistor T2 applies the data voltage Vdata supplied from the data line DL1 to the first node N1 in response to the i-th scan signal SCAN [i].

The third transistor T3 includes a source electrode connected to the high potential driving voltage line VDD, a drain electrode connected to the first node N1, and a gate electrode connected to the emission line EMLi. As a result, the third transistor T3 applies the high potential driving voltage VDD to the first node N1 in response to the i th emission control signal EMi.

The fourth transistor T4 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the emission line EL. The fourth transistor T4 forms a current path between the third node N3 and the fourth node N4 in response to the i th emission control signal EMi.

The fifth transistor T5 is connected to the drain electrode connected to the second node N2, the source electrode connected to the initializing voltage Vini input terminal and the (i-1) th scan signal SCAN [i-1] Gate electrode. The fifth transistor T5 applies the initialization voltage Vini to the second node N2 in response to the (i-1) th scan signal SCAN [i-1].

The sixth transistor T6 includes a source electrode connected to an input terminal of a drain electrode initialization voltage Vini connected to the fourth node N4 and a gate electrode connected to the ith scan line SLi. The fifth transistor T5 applies the initializing voltage Vini to the fourth node N4 in response to the ith scan signal SCAN [i].

The storage capacitor Cst includes a first electrode coupled to the second node N2 and a second electrode coupled to the high potential drive voltage line VDD.

3 is a waveform diagram showing a gate signal driving a pixel and a diagram showing a main node voltage of the pixels according to the waveform diagram. FIG. 4A is an equivalent circuit diagram of the pixel during the initial period, FIG. 4B is an equivalent circuit diagram of the pixel during the sampling period, and FIG. 4C is an equivalent circuit diagram of the pixel during the emission period.

The driving of the organic light emitting display according to the present invention will be described with reference to FIGS. 2 to 4C.

In the OLED display according to the present invention, one frame period may be divided into an initial period (Ti), a sampling period (Ts), and an emission period (Te). The initial period Ti is a period for initializing the voltage of the gate electrode of the driving transistor. The sampling period Ts is a period for initializing the voltage of the anode electrode of the organic light emitting diode OLED and sampling the threshold voltage of the driving transistor DT and storing it in the node B. The emission period Te includes programming the source-gate voltage of the driving transistor DT including the sampled threshold voltage and causing the organic light emitting diode OLED to emit light with the driving current according to the programmed source- Period. The initial period Pi of the ith pixel line overlaps the sampling period of the (i-1) th pixel line. That is, according to the present invention, the sampling period Ts can be sufficiently secured, so that the compensation of the threshold voltage can be more accurately performed.

Referring to FIG. 4A, during the initial period Pi, the fifth transistor T5 is turned on in response to the (i-1) th scan signal SCAN (i-1) Vini). As a result, the gate electrode of the driving transistor DT is initialized to the initializing voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting device OLED and can be set to a voltage equal to or lower than the low potential driving voltage ELVSS. In the initial period Pi, the data voltage Vdata of the previous frame is held in the first node N1.

Referring to FIG. 4B, during the sampling period Ts, the sixth transistor T6 applies the initialization voltage Vini to the fourth node N4 in response to the ith scan signal SCANi. As a result, the anode electrode of the organic light emitting diode OLED is initialized to the initializing voltage Vini.

The second transistor T2 applies the data voltage Vdata supplied from the data line DL1 to the first node N1 in response to the i-th scan signal SCAN [i]. The first transistor T1 is turned on in response to the i-th scan signal SCAN [i] so that the driving transistor DT is diode-connected (the gate electrode and the drain electrode are short- )do.

In the sampling period Ps, a current Ids flows between the source and the drain of the driving transistor DT. Since the gate electrode and the drain electrode of the driving transistor DT are diode-connected, the voltage of the second node N2 gradually rises due to the current Ids flowing from the source electrode to the drain electrode. During the sampling period Ts, the voltage of the second node N2 increases from the data voltage Vdata (n) to the value (Vdata (n) -Vth) obtained by subtracting the threshold voltage Vth of the driving transistor DT.

4C, during the emission period Pe, the third transistor T3 applies a high-level driving voltage VDD to the first node N1 in response to the i-th emission control signal EM [i] . The fourth transistor T4 forms a current path of the third node N3 and the fourth node N4 in response to the i th emission control signal EM [i]. As a result, the driving current Ioled passing through the source electrode and the drain electrode of the driving transistor DT is applied to the organic light emitting diode OLED.

During the emission period Pe, a relational expression for the driving current Ioled flowing through the organic light emitting diode OLED is as shown in the following equation (1).

[Equation 1]

_{I OLED = k / 2 (Vgs} + | Vth |) 2 = k / 2 (Vg-Vs + | Vth |) 2 = k / 2 (Vdata- | Vth | -VDD + | Vth |) 2 = k / 2 (Vdata- VDD) ²

In Equation (1), k / 2 represents a proportional constant determined by electron mobility, parasitic capacitance, channel capacity, and the like of the driving transistor DT.

The threshold voltage (Vth) component of the driving transistor DT is erased in the relational expression of the driving current Ioled as shown in the following formula (1). This is because the organic light emitting display according to the present invention has the threshold voltage The drive current Ioled does not change.

As described above, the OLED display according to the present invention can program the data voltage regardless of the variation of the threshold voltage Vth during the sampling period Ts.

FIG. 5 is a diagram showing a shift register according to the present invention, and FIG. 6 is a diagram showing a part of a light emission control signal stage and a scan signal stage. FIG. 7 is a diagram showing the configuration of the scan signal stage shown in FIG.

5 to 7, the shift register according to the present invention includes a light emission control signal generator 141 and a scan signal generator 142. The emission control signal generator 141 sequentially generates first to nth emission control signals EM1 to EMn and the scan signal generator 142 sequentially outputs the first to nth scan signals SCAN1 to SCANn . The emission control signal generation section 141 includes a plurality of emission control signal stages that are connected to each other. The i-th emission control signal stage EM_Di generates the i-th emission control signal EMi and applies it to the pixels Pi of the i-th pixel line. The scan signal generating unit 142 includes a plurality of scan signal stages that are connected to each other. The ith scan signal stage SCAN_Di generates an ith scan signal SCANi and applies it to the pixels Pi of the ith pixel line. The ith scan signal stage SCAN_Di controls the QB node by using the i < th > emission control signal EMi in a period in which the scan signal SCAN is not output.

In addition, the light emission control signal generator 141 may include a dummy stage for generating a carry signal. Similarly, the scan signal generating unit 142 may include a dummy stage for generating a carry signal.

In the following description, the term "front stage" means that the stage is located at the upper portion of the reference stage. For example, based on the i-th stage (i is a natural number satisfying 1 <i <n), the front stage may be a dummy stage or any one of the first stage STG1 to the i-1 stage STG [i-1] do. Quot; rear stage "refers to a stage located at the bottom of the reference stage. For example, on the basis of the i-th stage (1 <i <n) stage STGi, the succeeding stage designates any one of the i + 1 stage STG [i + 1] through the n-th stage STGn .

Referring to FIG. 7, the i-th scan signal stage will be described in detail as follows. The ith scan signal stage SCAN_Di according to the present invention includes a pull-up transistor Tpu, a pull-down transistor Tpd, a start control transistor Tvst, a Q node control transistor Tqc1, And a Q-node reset control transistor Tqc2.

The pull-up transistor Tpu includes a gate electrode connected to the Q node, a source electrode connected to the gate clock (CLK) input terminal, and a drain electrode connected to the output terminal Nout.

The pull-down transistor Tpd includes a gate electrode connected to the QB node, a source electrode connected to the output node Nout, and a drain electrode connected to the gate low voltage input.

The start control transistor Tvst includes a gate electrode connected to a start signal input terminal, a source electrode connected to a low potential voltage (VGL) input line, and a drain electrode connected to the Q node. The start control transistor Tvst discharges the Q node to the low potential voltage VGL in response to the start pulse VST or the carry signal SCAN [i-1] applied to the start signal input terminal.

The Q node control transistor Tqc1 includes a gate electrode connected to the QB node, a source electrode connected to the Q node, and a drain electrode connected to a high potential voltage (VGH) input. The Q node control transistor Tqc1 charges the Q node to the high potential voltage VGH in response to the QB node voltage.

The Q node reset control transistor Tqc2 includes a gate electrode receiving the reset signal RST, a source electrode connected to the Q node, and a drain electrode connected to the input terminal of the high potential voltage VGH. The Q node reset control transistor Tqc2 charges the Q node to the high potential voltage VGH in response to the reset signal RST.

FIG. 8 is a timing chart of the driving signal timing of the scan signal stage according to the present invention shown in FIG.

The driving of the scan signal stage according to the present invention will now be described with reference to FIGS. 5 to 8. FIG.

At the start of the frame, the first transistor (T1) of the ith scan signal stage (SCAN_Di) precharges the Q node to the negative (-) low potential voltage in response to the voltage at the start signal input terminal. The Q node control transistor Tqc1 of the dummy stage operates in response to the start signal VST and the first to nth scan signal stages SCAN_D are operated by receiving the scan signal of the previous single stage as a carry signal .

When the clock signal CLK is input to the source electrode of the pull-up transistor Tpu with the Q node precharged, the Q node is bootstrapped as the source electrode voltage of the pull-up transistor Tpu falls. As the Q node is bootstrapped, the potential difference between the gate and the source of the pull-up transistor Tpu becomes large, and eventually the pull-up transistor Tpu is turned on when the voltage difference between the gate and the source reaches the threshold voltage. When the pull-up transistor Tpu is turned on, the voltage of the output node Nout is discharged to the low potential voltage level of the gate clock CLK. As a result, the ith scan signal stage SCAN_Di outputs the ith scan signal SCANi through the output terminal Nout.

The Q node control transistor Tqc1 charges the Q node to a high voltage in response to the QB node voltage. The QB node is connected to the output terminal of the emission control signal stage EM_D and directly receives the emission control signal EMi. The i &lt; th &gt; emission control signal EMi maintains the low potential voltage during the light emission period of the pixels Pi of the ith pixel line. For example, the second emission control signal P maintains a low potential voltage during the emission period Te2 of the pixels of the second pixel line. As a result, the Q node control transistor Tqc1 of the second scan signal stage SCAN_D2 charges the Q node to the high potential voltage in response to the QB node voltage. That is, during the light emission period Te, the Q node maintains a high potential voltage. As a result, since the output terminal Nout of the scan signal stage SCAN_D stably maintains the high potential voltage, the scan signal SCAN is not output. Therefore, during the light emission period Te, the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 of the pixels P may maintain the turn-off state, respectively . In particular, the shift register 140 of the present invention can reduce its size because it does not use additional transistors to stabilize the Q-node voltage of the scan signal stage SCAN_D. That is, the output of the scan signal can be stabilized while the bezel is reduced.

The Q node reset transistor Tqc2 resets the Q node to a high potential voltage in response to the reset signal RST. The reset signal RST may be applied at the end of the frame period, for example, in the vertical blank period VB. That is, the third switch element T3 initializes the Q node of the scan signal stage SCAN_D to the high potential voltage VGH every frame period. The active period AT is a period of time required to write one frame of data to all pixels of the pixel array 100A. The vertical blanking period VB includes a vertical sync time VS based on the Video Electronic Standards Association (VESA) standard, a vertical front porch (FP), and a vertical back porch (BP) .

The capacitor C prevents the voltage of the drain electrode from being changed by the coupling phenomenon when the voltage of the clock signal CLK applied to the source electrode of the pull-up transistor Tpu is changed.

9 is a diagram illustrating a scan signal stage according to another embodiment.

9, the ith scan signal stage SCAN_Di according to another embodiment includes a pull-up transistor Tpu, a pull-down transistor Tpd, a start control transistor Tvst, A Q node control transistor Tqc1, a Q node reset control transistor TQC2, and an auxiliary transistor Tbv. In the embodiment shown in Fig. 9, the same reference numerals are used for substantially the same configurations as those of the above-described embodiment, and a detailed description thereof will be omitted.

The auxiliary transistor Tbv includes a gate electrode connected to the low potential voltage (VGL) input terminal, a source electrode connected to the Q node, and a drain electrode connected to the Q 'node. The gate electrode of the pull-up transistor Tpu is connected to the node Q '. That is, the auxiliary transistor Tbv precharges the Q 'node to the same voltage level as the Q node when the Q node is precharged in the negative, in response to the voltage at the input terminal of the low potential voltage (VGL).

The gate electrode and the source electrode of the auxiliary transistor Tbv are both connected to a low potential voltage (VGL) input terminal and serve as a diode. As a result, the voltage of the Q 'node can be stably maintained regardless of the voltage of the Q node.

Fig. 10 shows a shift register according to the third embodiment.

Referring to FIG. 10, the i-th scan signal stage SCAN_Di includes first and second pull-up transistors Tpu, first and second pull-down transistors Tpd, A transistor Tvst, a Q node control transistor Tqc1, and a Q node reset control transistor Tqc2. 10, the same reference numerals are used for the same components as those in the above-described embodiment, and a detailed description thereof will be omitted.

The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a source electrode connected to the input terminal of the first gate clock CLK1, and a drain electrode connected to the first output terminal Nout1. The first pull-down transistor Tpd1 includes a gate electrode connected to the QB node, a source electrode connected to the first output terminal Nout2, and a drain electrode connected to the gate low voltage input terminal.

The second pull-up transistor Tpu2 includes a gate electrode connected to the Q node, a source electrode connected to the input terminal of the second gate clock CLK2, and a drain electrode connected to the second output terminal Nout2. The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a source electrode connected to the second output terminal Nout2, and a drain electrode connected to the gate low voltage input terminal.

The scan signal stage shown in FIG. 10 may be driven using the drive signal shown in FIG.

The i th scan signal stage SCAN_Di according to the third embodiment uses the second pull-up transistor Tpu2 connected to the second output terminal Nout2 to generate the (i + 1) th scan signal SCAN [i + 1] . That is, the i-th scan signal stage SCAN_Di according to the third embodiment outputs scan signals applied to two adjacent pixel lines by using one stage. As a result, the area occupied by the scan signal stage in the shift register 140 can be reduced to half, thereby further reducing the bezel area.

In the above embodiments, the QB node of the i &lt; th &gt; scan signal stage SCAN_Di shown in Fig. 6 shows a shift register controlled by the i &lt; th &gt; emission control signal EMi to be controlled to a low potential voltage. However, the technical idea of the present invention is not limited thereto. For example, as shown in FIG. 8, the i-th emission control signal EMi maintains a turn-off voltage having a high level voltage for 6H and maintains a turn-on voltage for a remaining period in one frame. Therefore, in addition to the i-th scan signal stage SCAN_Di, the (i-1) th scan signal stage can also control the QB node using the i-th emission control signal EMi. 8, the i-th emission control signal EMi can control the QB node of the (i-5) th scan signal stage to the i-th scan signal stage (SCAN_Di) in the embodiment having the timing chart shown in Fig. .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: Data driver 130: Level shifter
140: shift register 141: emission control signal stage
142: scan signal stage

Claims (7)

A pixel array in which pixels including an organic light emitting diode, a scan line and an emission line connected to the pixels are arranged;
A light emission control signal generator for applying an emission control signal to the emission line during a light emission period; And
And a scan signal generating unit for applying a scan signal to the scan line in a period other than the light emission period,
The scan signal generating unit may include a plurality of scan signal stages to which the scan signal generating unit is connected,
At least one of the scan signal stages
A start control transistor for maintaining the Q node at a low potential voltage in response to a voltage of a start signal input terminal;
A pull-up transistor comprising a gate electrode connected to the Q node, a source electrode receiving a clock signal, and a drain electrode connected to the output terminal; And
And a Q node control transistor having a gate electrode connected to the QB node, a source electrode connected to the Q node, and a drain electrode connected to the high potential input terminal,
Wherein the QB node receives the emission control signal directly, and the gate electrode of the Q node control transistor is applied with a turn-on voltage during the emission period. The method according to claim 1,
The start control transistor precharges the Q node with a low potential voltage applied through the source electrode,
Wherein the pull-up transistor is bootstrapped by a low potential voltage of the clock signal in a state where the Q node is precharged and outputs the scan signal having a low potential voltage through the output terminal. The method according to claim 1,
The scan signal stage
And a Q-node reset control transistor having a gate electrode for receiving a reset signal, a source electrode connected to the Q-node, and a drain electrode connected to the high-potential voltage input terminal. The method of claim 3,
And the reset signal is applied within a vertical blank period of the frame period. The method according to claim 1,
A pull-up transistor comprising a gate electrode connected to the QB node, a source electrode connected to the output terminal, and a drain electrode connected to the high potential voltage input terminal. The method according to claim 1,
The pixel array includes first through n-th (n is a natural number) pixel lines,
Wherein the emission control signal generation unit includes first through n-th emission control signal stages for outputting first through n-th emission control signals, respectively,
The scan signal generating unit may include first to n-th scan signal stages for outputting first to n-th scan signals,
wherein the QB node of the i-th scan signal stage (i is a natural number of n or less) of the n scan signal stages directly receives the i-th emission control signal. The method according to claim 6,
And the i th scan signal output from the ith scan signal stage maintains a turn-off voltage while the i th emission control signal is applied as a turn-on voltage.

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