KR20180007930A - Phase control apparatus for time interleaving sampling adc - Google Patents

Abstract

Disclosed is a phase controlling device for a time interleaving sample ADC. The phase controlling device for a time interleaving sampling ADC comprises: a first clock buffer which outputs an input clock, an in-phase clock and an inverted clock; a first-stage phase delay control unit which receives the output of the first clock buffer and delays a phase of a channel 2 output on the basis of a channel 1 output; a second clock buffer which outputs in-phase clocks and inverted clocks, respectively for the channel 1 output and the channel 2 output according to the phase delay control in the first-stage phase delay control unit; and a second-stage phase delay control unit which controls clocks output from the second clock buffer to have a phase of an accurate delayed value. Therefore, a phase can be stably controlled.

Description

[0001] PHASE CONTROL APPARATUS FOR TIME INTERLEAVING SAMPLING ADC [0002]

The present invention relates to a phase control apparatus for a time interleaved sampling ADC, and more particularly, to a time interleaving sampling ADC capable of obtaining a high sampling rate with a combination of ADCs having a low sampling rate, To a phase control apparatus for a time interleaved sampling ADC for compensating for system performance degradation caused by a phase difference of a clock by allowing a phase to be supplied with a predetermined time difference.

Time Interleaving Sampling ADC is a technique that combines several ADCs with low sampling rates in parallel to increase the sampling rate by the number of ADCs combined to achieve high-speed sampling. The performance of a digital signal processing system that receives analog signals is often very limited to the rate at which analog signals are converted to digital. Systems requiring high-speed signal sampling techniques have the disadvantage that they use very high-speed, high-speed ADCs to sample the data received in real time, but in this case the cost is very high.

In order to solve this problem, it is possible to increase the sampling rate of the entire system by reconstructing the analog signals received by using a plurality of low-speed ADCs after sampling each ADC with a predetermined time interval. The system design is possible.

The time interleaved sampling ADC uses n ADCs in parallel. Assuming that the sampling rate of the entire system is fs, each ADC has a sampling rate of fs / n, and sequential selection and reconstruction of the sampled digital data from these ADCs It can have the same result as sampling at the speed of fs again.

The high-speed analog signal is input to each ADC equally, and the clock used is supplied by delaying the phase by T / n for each ADC with respect to the reference clock supplied to the first ADC. In this case, The size and offset voltage must be the same, the sampling clock interval should be uniform, and if this problem is not solved, the performance of the entire system can be reduced.

Since the analog signal input to each ADC is a voltage signal input, it is designed to have the same line length from the input signal line to the input of each ADC in the PCB design, so that the signal size is constantly supplied, To remove the input offset. However, if the sampling clock supplied to each ADC is supplied at a constant interval, a method of correcting the phase error of each clock must be applied.

It is an object of the present invention to overcome the above problems and to provide a time interleaving sampling ADC system capable of precisely adjusting the phase of a clock supplied to each ADC to reduce system performance degradation caused by a phase error, And to provide a phase control device for an ADC.

In addition, when the phase delay of the clock is generated by using the propagation delay of the gate inside the FPGA, since the length of the internal wiring of the FPGA is not constant and the placement of the logic cell buffer may be changed every time the compile is performed, I can not. In addition, when using a digital phase shifter (DPS) that uses multiple delay logic to delay the phase, if a phase delay is generated for a high-speed clock of several hundred MHz or more, a clock jitter of about hundreds of ps is generated, impossible. Therefore, a time interleaved sampling that precisely controls the phase of the clock supplied to each ADC by using a clock buffer and a delay line capable of delay control in several ps units can provide a clock delayed by T / n. Device.

According to an aspect of the present invention, there is provided a phase control apparatus for a time interleaved sampling ADC, including: a first clock buffer for outputting a clock having an identical phase to an input clock and an inverted clock; Phase delay control unit for receiving the output of the first delay unit and delaying the phase of the channel 2 output based on the output of the channel 1, A second clock buffer for outputting a clock having the same phase and an inverted clock, and a two-stage phase delay controller for controlling the clock outputted from the second clock buffer to have a phase exactly delayed.

According to the phase control method for the time interleaved sampling ADC as described above, even when a high-speed clock is used by using the phase delay control method, a clock necessary for each ADC is generated and supplied through accurate phase control, A sampling ADC can be implemented.

FIG. 1 is a block diagram showing the overall configuration of a clock phase delay control and distribution unit according to an embodiment of the present invention.
2 is an output waveform diagram of the 1-stage phase delay control unit.
3 is an output waveform diagram of the two-stage phase delay control unit.
4 is an overall block diagram of a time interleaved sampling ADC using four ADCs.
5 is a full clock phase diagram of a time interleaved sampling ADC using four ADCs.
6 is a flowchart illustrating a phase control method for a time interleaved sampling ADC according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. In the present application, the term "connect" should be understood to include not only physical connections of the elements described in the specification but also timely connections, network connections, and the like.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and are to be interpreted in an ideal or overly formal sense unless explicitly defined in the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to facilitate the understanding of the present invention, the same reference numerals are used for the same constituent elements in the drawings and redundant explanations for the same constituent elements are omitted.

FIG. 1 is a block diagram showing the overall configuration of a clock phase delay control and distribution unit according to an embodiment of the present invention. FIG. 2 is an output waveform diagram of a 1-stage phase delay control unit, FIG. 4 is an overall block diagram of a time interleaved sampling ADC using four ADCs, and FIG. 5 is a total clock phase diagram of a time interleaved sampling ADC using four ADCs.

1, the clock phase delay control and distribution unit 100 of the present invention includes a first clock buffer 110, a first phase delay control unit 120, a second clock buffer 130, And a phase delay controller 140.

In the present invention, there are four ADCs, each ADC uses a clock of 500 MHz and the overall sampling rate is 2 GSPS. Therefore, the time interleaved sampling ADC requires a clock having a phase delayed by T / 4, 2T / 4 and 3T / 4 based on 0 as shown in FIG.

4, an ADC0 410, an ADC1 420, an ADC2 430, and an ADC3 440 for converting an analog input signal into a digital output signal are provided.

ADC0 410 needs a clock having a phase of?, And ADC1 420 needs a clock having a phase delayed by T / 4.

The ADC2 430 needs a clock having a phase delayed by 2T / 4, and the ADC3 440 needs a clock having a phase delayed by 3T / 4.

The first clock buffer 110 is a 1x2 clock buffer. When receiving the clock, the first clock buffer 110 outputs a clock having the same phase as that of the inputted clock and an inverted clock.

The first stage phase delay controller 120 receives a clock signal having a phase opposite to that of the input clock signal output from the first clock buffer 110 and receives the clock signal having a phase difference of T / . Here, the phase of the channel 1 output is 0 ° and the phase of the channel 2 output is 90 °.

The second clock buffer 130 is a plurality of 1x2 clock buffers. The plurality of second clock buffers 130 receive a clock having no phase change and a clock having a delay of T / 4 from the 1-stage phase delay controller 120 have.

When a clock having no phase change and a clock having a delay of T / 4 are respectively input to the plurality of second clock buffers 130, a clock having the same phase as that of the input clock and a clock having an inverted phase can be output.

When a clock having no phase change is inputted to the second clock buffer 130, a clock having a phase opposite to that of the input clock can be output and input to the two-phase phase delay controller 140. Here, a phase error may occur in the clock having the same phase as that of the inputted clock and the clock having the inverted phase.

When the clock delayed by T / 4 is input, the second clock buffer 130 outputs a clock having an inverted phase and a clock having the same phase with respect to the input clock, and may be input to the two-stage phase delay controller 140.

The two-stage phase delay controller 140 corresponds to the plurality of second clock buffers 130 as a plurality of two-stage phase delay controllers. The plurality of two-stage phase delay control units 140 receive the clocks inverted in phase with the input clocks output from the plurality of second clock buffers 130, and output the phase of the channel 2 output based on the output of the channel 1 Can be delayed.

The two-stage phase delay controller 140 receives a clock having a phase opposite to that of the clock output from the second clock buffer 130 and outputs an output of 0 and 2T / 4 when receiving an input having no phase change.

The two-stage phase delay controller 140 receives the clock of the same phase and the phase of the inverted phase outputted from the second clock buffer 130 and outputs the output of T / 4 and 3T / 4 when receiving the T / 4 delayed input have.

That is, when a plurality of two-stage phase delay controllers 140 receive an input having no phase change finally, clocks with phases delayed by 0 ° and 180 ° can be output. When receiving a T / 4 delayed input, 90 ° and 270 Phase delayed clock can be output.

In this case, the final output clock may be exactly 0, T / 4, 2T / 4, 3T / 4, and so on, since the final output clock may not have an accurate delay value due to the PCB line or other factors. 4 can be precisely adjusted.

6 is a flowchart illustrating a phase control method for a time interleaved sampling ADC according to an embodiment of the present invention.

Referring to FIG. 6, the clock phase delay control and distribution unit of the present invention receives a clock and outputs a clock signal having the same phase as that of the inputted clock signal (S610).

Subsequently, the phase of the channel 2 output is delayed by T / 4 based on the output of the channel 1 (S620). At this time, the phase of the channel 1 output is 0 °, and the phase of the channel 2 output is 90 °.

Subsequently, clocks of the same phase and inverted clocks are output to the channel 1 and channel 2 output clocks, respectively (S630). That is, a clock that is in phase with the channel 1 output clock and an inverted clock may be output, and a clock that is in phase with the channel 2 output clock and an inverted clock may be output.

Then, in the final output stage, outputs of 0 and 2T / 4 are output when receiving an input with no phase change, and outputs of T / 4 and 3T / 4 are output when receiving a delayed input of T / 4 (S640). In this case, the output may not have the correct delay due to the PCB line or other factors. In this case, the final output clock can be precisely adjusted to have exactly 0, T / 4, 2T / 4 and 3T / 4 phases.

In other words, when receiving input with no phase change, it outputs 0 and 2T / 4 outputs by receiving clocks of inverted and inverted clocks, and when receiving T / 4 delayed inputs, input clocks of inverted and inverted clocks T / 4, 3T / 4 can be output.

In the case of receiving input with no phase change finally, 0 ° and 180 ° phase delayed clocks can be output. When T / 4 delayed input is received, 90 ° and 270 ° phase delayed clocks can be output.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

100: Clock phase delay control and distribution unit
110: first clock buffer
120: Single phase delay control unit
130: Second clock buffer
140: Two-stage phase delay control unit

Claims (1)

A phase control device for a time interleaved sampling ADC,
A first clock buffer for outputting a clock having the same phase as that of the input clock and an inverted clock;
A 1-phase delay controller receiving an output of the first clock buffer and delaying a phase of a channel 2 output based on a channel 1 output;
A second clock buffer for outputting clocks inverted in phase with respect to the channel 1 output and the channel 2 output according to the phase delay control in the 1-stage phase delay controller; And
And a two-stage phase delay controller for controlling the clock outputted from the second clock buffer to have a phase of a value that is exactly delayed.

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