KR20180002535A - Direct memory access control device and operating method for the same - Google Patents

Abstract

The present invention is characterized in that it comprises a terminal for connecting the bus system 12 connecting the plurality of bus subscribers 60 with the direct memory access control device 40 and a control for controlling the operation of the direct memory access control device 40 And a direct memory access control device (40) having an apparatus (42). In this case, the control device 42 can be programmed.

Description

[0001] DIRECT MEMORY ACCESS CONTROL DEVICE AND OPERATING METHOD FOR THE SAME [0002]

The present invention relates to a direct memory access control device according to the preamble of claim 1 and a method according to the equivalent independent claim.

There are commercially available processing units, e.g., processors, that have one or more processor cores and are capable of accessing main memory as needed. In addition, computer systems including one or more of such processing units typically include a plurality of additional units, such as input / output modules ("IO"), etc., that interact with the processing unit. At least some of the elements of the computer system may exchange data, e.g., data having an Ethernet structure, over one common bus, preferably a parallel bus. In addition, methods for so-called direct memory access (DMA) are also known, so that data exchange over a common bus can be improved.

Known devices for controlling direct memory access are insufficiently flexible for use in many applications.

The underlying problem of the present invention is solved by means of a direct memory access control device according to claim 1 and by means of a method according to the equivalents claim. Preferred improvements are set forth in the dependent claims. Also, features important for the present invention are identified in the following specification and drawings, which, although not explicitly recited herein, may be important for the present invention as well as in various combinations.

The present invention relates to a direct memory access control device having a terminal for connecting a direct memory access control device with a bus system connecting a plurality of bus subscribers and a control device for controlling the operation of the direct memory access control device . In this case, the control device can be programmed, thereby increasing the flexibility compared to known systems.

In one implementation, the bus system is not connected to main memory, especially to the central unit of the processing unit. Correspondingly, elements that may be connected to the bus system, such as communication modules, for example, may have local memory, such as RAM memory ("Random Access Memory"), Gt; and / or < / RTI >

In one embodiment, the direct memory access controller, bus system, and bus subscriber of at least one of the bus subscribers in accordance with the present invention are elements of a microcontroller. For example, the microcontroller is disposed on a single integrated semiconductor circuit ("chip"). In yet another embodiment, the direct memory access control apparatus according to the present invention may be integrated into, for example, a communication module.

As used herein, the term " programmable "means that method steps that can be executed via a control device or a direct memory access control device are performed, for example, in a corresponding (program) manner during operation of a system including elements connected to the bus system, Which means that it can be freely programmed through the presetting of commands.

In particular, it is also possible to execute so-called " comparison branches "which are also known as pseudo code command names" if "," then "," else "

This may be reproduced via a processing unit (e.g., a CPU, a Multi Channel Sequencer (MCS), or another form also), according to preferred embodiments. The processing unit is characterized, for example, by the presence of a "native" instruction set, whereby the processing unit can be programmed with the use of the instruction set. Thus, for example, the DMA mode can be freely programmed for each application. The advantage of MCS is the configurable mode of sequential program execution that can not be interrupted by other processes.

Consider a programmable controller that includes a set of executable computational steps (e.g., arithmetic / logical operations, e.g., "if", "else", etc.) and forms a program sequence together through a combination of the computational steps .

The direct memory access control apparatus of the present disclosure can be used, for example, for DMA transfer between different bus subscribers and can cooperate with bus subscribers for this purpose. For example, the bus subscribers may be communication modules or storage areas assigned to the communication modules. For example, communication modules may be implemented as Ethernet modules, or as so-called "MCAN modules ". The CAN designates the "Controller Area Network" in English, and the alphabet "M" characterizes the manufacturer's initials. The direct memory access control device of the present application also includes a plurality of processing units or operations using a plurality of processing cores May also cooperate with bus subscribers or communication modules that are not implemented for.

The present invention is based on the fact that a relatively complex structure, in particular data having an interleaving structure, by a programmable controller is also analyzed in a particularly "intelligent" manner and / Can be processed. For example, so-called "Ethernet frames ", i.e. data frames according to the Ethernet protocol, may have additional protocols and / or so called" payload data "interleaving structures throughout the layers of the ISO / OSI layer model. Analysis and filtering of data in relatively higher protocol layers (ISO / OSI layer 3 and above, e.g. layer 4 or layer 5) is also possible according to the invention.

In one implementation, the direct memory access control apparatus of the present disclosure is configured to analyze data of a bus subscriber of a bus system in accordance with the programming of the controller. Through the programming of the control device, the data can be analyzed very favorably and flexibly. Thus, in particular, the above-described analysis can be performed step by step, and in one embodiment, for example, each subsequent analysis step is performed based on each of the preceding analysis steps. In the same way, in the case of additional embodiments, it may be possible to analyze (e.g., filter) the data types or protocols to be defined in the future, And the like.

In one implementation, the analysis is used to determine the length of one or more data to be transmitted and one or more target addresses for transmission to one or more second bus subscribers. If the data includes a plurality of sections to be transmitted separately, a plurality of lengths and a plurality of target addresses may be determined correspondingly.

In one embodiment, the control device may be optionally programmed between each analysis step. E. G., It is likewise carried out according to the respective preceding analysis steps or the results obtained in these analysis steps. Particularly for the direct memory access control apparatus of the present application, the external analysis of the data carried out using the predefined configuration and / or the non-modifiable computer program, e.g. by separate processing units, may be reduced or even unnecessary. Hence, by the programmable controller, the required calculation execution time can be reduced preferably already in the analysis.

In addition, DMA transfers of undesired data can be prevented because the analysis of the data of the bus subscriber can be carried out according to the principles of the present invention and by this analysis the data to be transmitted or the length of this data Is determined. In this way, it is possible to prevent the transfer of irrelevant protocol / header data of another protocol layer, which is not required at all in the target module for DMA transfer, to the DMA transfer, for example. Instead, only a target data packet or a payload of the data frame (or portions of this payload), for example, may be transmitted by the DMA as desired.

In one further implementation, the direct memory access control apparatus of the present disclosure is configured to transfer data from a first bus subscriber to one or more second bus subscribers via a bus system using one or more direct memory accesses in accordance with the programming of the controller do. By programming, the data can be transmitted in a highly desirable manner. The data to be transmitted may include all of the data examined in the analysis as described above or only some of them.

In particular, the direct memory access control device of the present disclosure enables the transfer of data (or a portion thereof) of a first bus subscriber, for example, a communication module or a storage area allocated to the communication module and connected to the bus system. For example, the data may be transferred into the local memory of the processing unit or processing core coupled to the bus system and may be transferred to the processing unit or another processing unit for transmission (and, optionally, prior analysis via a direct memory access control device) Involvement is unnecessary.

The data to be transmitted may preferably be transferred to a specific processing unit, or processing core, or storage area, using the criteria contained in the data ("search features" or filter criteria; Further, a plurality of portions of data to be transferred may be transferred to and distributed to a plurality of processing units or processing cores or storage regions. In this case, all data of one message (e.g. Ethernet frame) may be transmitted, or only certain pre-configurable parts of the message may be transmitted.

The transmission of only certain parts that can be preset is very advantageous, especially when the Ethernet frame is long because the undesired information (header, other protocols) can already be removed before DMA transmission. The unnecessary byte transmissions thus avoided reduce the load on the bus system (e.g., the internal bus of the microcontroller μC) and, in particular, reduce the load on the bus subscriber to which the data is to be transferred, Simplify software. In this case, the overall required computational processing power or execution time to characterize the transmission of data may be reduced because the last unnecessary frame parts are excluded in advance. The execution time described above may include, among other things, protocol decisions used for analysis, data retrieval, and the like.

For example, Ethernet frames including the so-called "SOME / IP protocol" may include a plurality of data sections to be transmitted (data segments), each of which may be transmitted to different bus subscribers by direct memory access. In this case, the direct memory access control apparatus according to the present invention has the additional advantage that a single so-called "DMA channel" (DMA: Direct Memory Access) can transfer a plurality of data sections to different bus subscribers. The abbreviation "SOME / IP" stands for "Scalable service-Oriented MiddlewareE over IP" in English.

After the direct memory access control device of the present application determines the data length ("frame length") or the length of each of the sections of data, the direct memory access control device of the present disclosure may be implemented in accordance with one additional embodiment, The validity of the start address and the end address can be checked and, if necessary, can be reacted appropriately using the setting of error flags temporarily. Thus, if necessary, additional checks that may be required to be performed by the software running on the target module for DMA transfer in accordance with the prior art may be unnecessary.

In this case, analysis of the above-described data and control of the direct memory access control device are preferably performed using a programmable controller. Programming of the programmable controller can be accomplished, for example, by providing corresponding (program) instructions for the control device, for example, into a pre-configurable storage area of the memory coupled to the bus system, or in a separate memory (e.g., (Program) instructions for the control device to the local memory in association with the direct memory access control device.

In one further implementation, the programmable controller device comprises a programmable processing unit. Portions of the functionality of the controller for the direct memory access controller of the present application may also be realized by one or more state machines in accordance with a further embodiment.

In addition, the control device (or the programmable processing unit)

- search features, in particular protocol information and / or CAN-ID (Controller Area Network Identity);

- search locations, especially offset addresses;

The length of each search feature;

A preset number of iterations or search runs;

A target address for transmission of one or more sections of data;

And / or < / RTI > the data of the bus subscriber of the bus system by loading one or more sets of parameters comprising at least one of the parameters of the bus system.

By loading one or more sets of parameters (which may include one or more parameters), the analysis of the data can be performed very efficiently and flexibly. The above-described loading may optionally be performed between any of a plurality of steps of analysis, for example, according to the results of each preceding analysis step.

In one further implementation, the direct memory access control apparatus of the subject application is configured to determine information in the data of a bus subscriber, determine the length of each section of data to be transmitted in each of the information, and compare the reference value with the length. To this end, for example, the above-described data may be loaded completely or only partially (e.g., into the local (buffer) memory of a direct memory access controller). If a plurality of sections of data are to be transmitted, the determination of the information and the comparison with the reference value may be performed iteratively, e.g., corresponding to each existing structure of the data. Using the determined length and reference value, errors and / or deliberate manipulations within the data or during transmission of the data may preferably be perceived.

In one further implementation, the direct memory access control apparatus of the present disclosure is adapted to transfer different sections of data to different second bus subscribers, or to different local addresses of the processing units, particularly to bus systems and to different target addresses . Accordingly, the data present in the (source) bus subscriber can preferably be transmitted and distributed to different target areas, e. G., To different target bus subscribers, depending on the data and / or criteria for the meta data of this data. Thereby, in particular, in the case of a (source) bus subscriber formed as a communication module, it is also possible to distribute the data of the communication module's message (e.g., the CAN message received by the communication module, etc.) to different target bus subscribers.

In one further implementation, the direct memory access control apparatus of the present disclosure is configured to determine error information and / or perform analysis and / or transmission of data according to error information. Such as source address and / or target address, as well as the case where the analysis of additional parameters for a particular DMA transfer is based on one or more predefinable error criteria (e.g., a target address outside the allowed address range, The length of the data to be transferred that is greater than the value, etc.), then an error or operation may be inferred and the DMA transfer may be suspended or even not executed. In other embodiments, the introduction of an error response (an entry in the error memory, an interrupt request to the processing unit, etc.) may be considered.

In one further implementation, the direct memory access control apparatus of the present disclosure is configured to determine a start address and / or an end address of data of the first bus subscriber and compare the reference value with the reference value.

In one further implementation, the direct memory access control apparatus of the present application is configured to determine a start address and / or an end address of sections to transmit data and / or data to be transmitted to a second bus subscriber and to compare with a reference value.

In a further implementation, the direct memory access control apparatus of the present disclosure is configured to receive signaling information from a first bus subscriber and / or to set or delete signaling information within a first bus subscriber.

In one further implementation, the direct memory access control apparatus of the present disclosure is configured to transmit signaling information to a second bus subscriber and / or to set or delete signaling information in a second bus subscriber.

In one further implementation, the direct memory access control apparatus of the present disclosure includes the following actions:

- receiving a trigger signal (e.g., a control signal indicating that an analysis of the DMA transfer and / or data should be performed) from the first bus subscriber;

Receiving or reading data to be transferred by direct memory access in the main memory or the memory of the first bus subscriber, in particular according to one trigger signal or the trigger signal;

- determining an entry type that characterizes a memory organization for a target memory of a second bus subscriber and determining a type of an entry from the first bus subscriber via the bus system using one or more direct memory accesses according to the determined entry type, Transferring data into the bus subscriber's target memory;

And is configured to perform one or more of the actions.

The above-described measures, which may be performed separately or in combination with each other and in any order relative to each other, advantageously improve the analysis and transmission of data as well as the operation of the direct memory access control device . Depending on the entry type, it can be preset, for example, whether the data is to be transferred into the last "dedicated" (block) storage area or into a storage area configured as a circular buffer. The storage area may be, for example, each local memory of the central main memory or bus subscriber, and may be, for example, the local memory of the processing unit coupled to the bus system.

In addition, the control device may be integrated into the integrated semiconductor circuit of the direct memory access control device of the present application. Thus, mounting space and cost can be saved.

In addition, the direct memory access control device of the present application can be formed as a hardware circuit having a structure size in the range of 20 nm (nanometer) to 60 nm, particularly using the semiconductor technology (especially including the programmable control device). Therefore, the execution time necessary for the analysis and transmission of the data is preferably reduced and efficient operation can be ensured.

In one implementation, the direct memory access control apparatus of the present disclosure is configured to perform the following steps.

- receiving or reading a set of one or more parameters of one or more bus subscribers, under the condition that the parameter set comprises one or more presettable parameters;

- receiving or reading data from a first bus subscriber;

Determining first information in a first region of data, under a condition that a first region of data is determined according to one or more parameters;

- comparing the first information with a first criterion, for example a "search feature" and determined in a parameter set;

Performing the following steps (a) to (c) conditionally based on the compared and / or determined first information:

(a) determining each additional information in each one or more additional areas of data, with each additional area of data being determined according to one or more additional parameters and / or first information and / or additional information ;

(b) comparing the additional information with the additional criteria determined in the parameter set;

(c) conditionally repeating steps (a) through (c) based on the comparison and / or determined additional information;

Determining one or more target addresses of the one or more second bus subscribers according to the first information and / or additional information and / or one or more parameters;

Determining the length of one or more sections of data to be transmitted to the one or more target addresses according to the first information and / or additional information and / or one or more parameters;

- transferring one or more sections of data from the first bus subscriber to one or more target addresses of the one or more second bus subscribers using direct memory access to the one or more second bus subscribers.

Each mentioned area of data is preferably characterized by one or more addresses of the bus system, or one or more addresses of the memory associated with the bus system. The present direct memory access control apparatus described through the described steps is particularly preferably formed for the analysis and transmission of data.

In one implementation of this, before transmission of one or more sections of data, repetition of at least a part of the preceding steps of the transmission step is performed. In this way, preferably, information about a plurality of sections to be transmitted from the data can be determined, and subsequent transmissions of the sections can be performed in succession.

In addition, the present invention provides a direct memory access control device having a terminal for connecting a direct memory access control device with a bus system connecting a plurality of bus subscribers, and a control device for controlling the operation of the direct memory access control device And to a method for operating the same. In this case, the control device is programmed according to the method.

In one embodiment of the method, the data of a bus subscriber of the bus system is analyzed according to the programming of the control device, or the data is transferred to the first bus subscriber through the bus system using one or more direct memory access, To one or more second bus subscribers.

In one further embodiment of the method, the information is determined from the data of the bus subscriber, the length of each section of the data to be transmitted in the information is determined and compared with a reference value.

In the case of the method according to the invention, successive advantages corresponding to those already described with respect to the direct memory access control device and its implementations hereinbefore are achieved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, exemplary embodiments according to the present invention will be described with reference to the drawings.

1 is a simplified diagram illustrating a system including a bus system, a direct memory access controller, and a plurality of bus subscribers coupled to the bus system.
2 is a schematic diagram of data of an Ethernet frame.
3 is a program flow diagram of a control apparatus for controlling the operation of the direct memory access control apparatus of FIG.
4 is a first diagram of an extension according to the selection of the program flow diagram of FIG.
5 is a second diagram of an extension according to the selection of the program flow diagram of FIG.
6 is a diagram illustrating an exemplary allocation of data sections of an Ethernet frame to respective local memories of processing units connected to a bus system;
7 is a diagram illustrating a first further embodiment of a bus subscriber implemented as a communication module for the system according to FIG.
8 is a diagram illustrating a second additional embodiment of a bus subscriber implemented as a communication module for the system according to FIG.

The same reference numerals are used for elements and variables that are functionally equivalent in all figures even if the embodiments are different.

1, there is shown a computer system 10 including a plurality of processing units 20_1 to 20_n and local memories 30_1 and 30_2 to 30_n respectively assigned to the processing units 20_1 to 20_n have. Further, the central main memory 30 is connected to the bus system 12. The main memory 30 is optional and is shown in broken lines in FIG. The left block in FIG. 1 characterizes the direct memory access controller 40, which is also connected to the bus system 12 via a terminal 41. In Figure 1, on top of the direct memory access control device 40 is shown a control device 42 which is capable of controlling the operation of the direct memory access control device 40. [

1 also shows a plurality of communication modules 50_1 to 50_n connected to the bus system 12, these communication modules being also denoted by reference numeral 50 in its entirety. An Ethernet network, a CAN bus, etc., for example, are connected to the communication modules 50_1 to 50_n, respectively. Each of the components 20_1, 20_2 to 20_n, 30_1, 30_2 to 30_n, 30, 40 and 50_1, 50_2 to 50_n connected to the bus system 12 characterizes each "bus subscriber" , Bus subscribers are generalized and indicated at 60 instead.

In one embodiment, the processing units 20_1 through 20_n are formed through respective processor cores of the processing units (not shown in FIG. 1 by itself). In one embodiment, the processing unit is implemented as a monolithic integrated semiconductor circuit. In one embodiment, the computer system 10 is a microcontroller.

In addition, in FIG. 1, a plurality of data paths shown through lines of arrow type are also symbolically shown. The data paths are transferred from the communication module 50_n (in the lower right portion of FIG. 1) to the local memories 30_1, 30_2 (in the upper region of FIG. 1) via the bus system 12 To < RTI ID = 0.0 > 30_n. ≪ / RTI >

For example, communication modules 50 write data received via their respective communication channels (not shown) in main memory 30 because communication modules 50 generally interpret data I can not do it. Then, each communication module 50 can send a trigger signal directly to the memory access control device 40 (see below, block 202 in FIG. 3).

In addition, the communication modules 50 may at least temporarily store the data received via their respective communication channels in a local memory (not shown), and then at least portions of the received data, May be transmitted via system 12 to one or more other bus subscribers.

In other words, Figure 1 generally shows a terminal for the connection of the direct memory access controller 40 with the bus system 12 connecting the plurality of bus subscribers 60 and the terminal of the direct memory access controller 40 There is shown a computer system 10 including a direct memory access control device 40 having a control device 42 for controlling a memory device 40. [ In this case, the control device 42 can be programmed.

In one embodiment, the direct memory access control apparatus 40 is configured to analyze the data of the bus subscriber 60 of the bus system 12 in accordance with the programming of the control device 42.

In one additional embodiment, direct memory access control device 40 is operable, in accordance with the programming of control device 42, to provide one (1) direct memory access from bus subsystem 60 via bus system 12, To the second bus subscriber (60).

Still in a further embodiment, the programmable controller 42 includes a programmable processing unit 44, shown in phantom in the lower portion of the controller 42 in Fig. The programmable processing unit 44 is preferably (but non-coercively) enabled to operate through, for example, "own" program code or corresponding program instructions that reside in the control device 42, Or program instructions may be executed during the operation of the processing unit 44, preferably without the intervention of the bus system 12. [ The control device 42 may also include one or more state machines for realizing portions of the functionality of the controller 42 for the direct memory access controller 40. In one embodiment,

In addition, in further preferred embodiments, the components 40,42, 44 may each include (or only one, or only two) memory, in particular local memory, Code or corresponding program instructions or programs may be executed in the (local) memory of the associated component 40, 42, 44. This preferably increases performance (processing power) and may contribute to reducing or preventing access to external or central memory, e.g., flash memory.

In one preferred embodiment, direct memory access controller 40 is formed as a hardware circuit. In one further embodiment, the control device 42 is integrated into the integrated semiconductor circuit of direct memory access control device 40. [ In one embodiment, the control device 42 is disposed separately from the direct memory access control device 40.

2, a schematic diagram 100 of an Ethernet frame (data frame according to Ethernet protocol) 120 and data of another protocols or protocol layers contained in this Ethernet frame is shown. The Ethernet frame 120 is implemented in an interleaving manner, which is illustrated here through a total of four data structures extending from left to right in each figure. Ethernet frame 100 'of FIG. 2 (and Ethernet frame 100' of FIG. 6 in the same way) in FIG. 2 is illustratively a data 100 to be analyzed by direct memory access control device 40 and at least partially And then characterizes the data 100 to be transmitted by direct memory access and by direct memory access control device 40. [

2, the lowermost data structure 120 corresponds to a diagram of the Ethernet frame in the MAC ("Medium Access Control") layer (layer 2) of the ISO / OSI layer model, Characterizes an IPv6 structure ("Internet Protocol Version 6 ", ISO / OSI Layer 3) as a component of a payload 130 of the Ethernet frame 120, and a data structure 160 ) Characterizes the TCP structure (Transmission Control Protocol, ISO / OSI Layer 4) as a component of the payload 151 of the IPv6 structure 140, and the block 180 located thereon While symbolically illustrating protocols and possible additional interleaving of the data frames, while expressing the payload content of the TCP structure 160. The lines 190 illustrate the " expansion "of the payload of the lower ISO / OSI layer, respectively, with a data frame of the layer located thereon. For example, lines 190 between block 120 and block 140 indicate that IPv6 structure 140 is derived from the MAC payload of Ethernet frame 120.

Here, the Ethernet frame 120 is characterized by the following fields or data sections listed through their reference numerals (column name: field name, reference code, length).

Preamble 122 8 bytes;

Target address 123 6 bytes;

Source address 124 6 bytes;

TPID 125 2 bytes;

Priority (PCP) 126 3 bits;

DEI / CFI 127 1 bit;

VLAN-ID 128 12 bits;

EtherType 129 2 bytes;

MAC payload 130 42 bytes to 1500 bytes;

CRC checksum 131 4 bytes;

MAC header ("header") 132 18 bytes;

VLAN tag 133 4 bytes.

Where the IPv6 structure 140 is characterized through the following data sections listed through their reference numerals below.

Version 143 4 bits;

Priority 144 1 byte;

Flow label 145 20 bits;

Payload length 146 2 bytes;

Next header 147 1 byte;

Hop Limit 148 1 byte;

Source address 149 16 bytes;

Target address 150 16 bytes;

IPv6 payload 151 0 to 1460 bytes;

IPv6 header 153 40 bytes.

Here, the TCP structure 160 is characterized by the following data sections listed through their reference numerals below.

Source port 164 2 bytes;

Target port 165 2 bytes;

Sequence number 166 4 bytes;

ACK number 167 4 bytes;

Data offset 168 4 bits;

Reserved + flag 169 12 bits;

Window size 170 2 bytes;

Checksum 171 2 bytes;

Emergency Pointer 172 2 bytes;

TCP option 173 0 to 40 bytes;

TCP payload 174 0 to 1440 bytes;

TCP header 175 20 to 60 bytes.

In Figure 2, some data sections, such as MAC-payload 130, IPv6 payload 151, MAC header 132, CRC checksum 131, correspond to (but partially without) the illustrated interleaving, It is listed more than once.

As further described below, the analysis of the data described by way of example above can be performed through a direct memory access controller according to the present invention using predefinable search criteria or filter criteria. Here, the criteria may be, for example, Ethernet protocols (e.g., 0x8100 for "VLAN tag "), CAN-ID, PDUs (" Protocol Data Units ")," Mini Slot Identifiers "," LIN Identifiers " , Or other data structures. Various examples of these search criteria are presented in the tables described above.

However, the analysis of the principle and data according to the present invention is not limited to the Ethernet protocol or the interleaved additional protocols (IPv6, TCP, ...) in FIG. 2, but generally another protocol (E.g., CAN, LIN, FlexRay, ...). The flexibility required for this is preferably provided through the programmability of the control device 42 (FIG. 1).

Data received from the communication module 50 via a particular channel of the communication module may be stored in the main memory 30 or locally as respective communications (as indicated by arrows in FIG. 1) May be stored in the module 50. In FIG. 2, the hatched areas 1, 2, 3, 4 each represent areas to be analyzed by the direct memory access control device 40, each containing, by way of example, specific protocol identifications and / or data lengths. The task of the control device 42 is to identify the areas in the data to determine their respective data lengths and, depending on the loadable parameters that can be determined according to their respective protocols, and / (FIG. 1) in accordance with program instructions that may be executed through the bus subscriber 60 (FIG. 1).

In this case, the target storage area is characterized by the target address in the local memories 30_1 to 30_n of the processing units 20_1 to 20_n (or processing cores), and is characterized by the entry type in a manner of selectively supplementing . Depending on the entry type, it can be preset, for example, whether the data is to be transferred into the last "dedicated" linear storage area or memory block that can be preset, or into a storage area configured as a circular buffer.

3 shows a terminal for connection of the direct memory access controller 40 with the bus system 12 for connecting the plurality of bus subscribers 60 and a control for controlling the operation of the direct memory access controller 40 There is shown a program flow diagram of a method for operating a direct memory access control apparatus 40 having an apparatus 42. [ In this case, the control device 42 is programmed. In addition to Fig. 3, the diagram of Fig. 2 is used here for the purpose of describing the program sequence, in particular the fields indicated by the numbers 1 to 4, which are hatched in Fig.

3, the direct memory access control device 40 receives a trigger signal from the first bus subscriber 60, for example, from a communication module of one of the communication modules 50_1 to 50_n. This is done especially when a new message is entered into the bus subscriber 60, described above, which should be sent via bus system 12 by direct memory access. As a result of the trigger signal, the program sequence characterized by way of example in Fig. 3 begins. The starting address that characterizes the program sequence may be known at the control device 42, or may be determined by pre-configurable measures, particularly a reading process and / or a loading process.

3, the controller 42 (or the programmable processing unit 44) may load one or more sets of parameters, including one or more of the following parameters, For transmission and / or analysis of the data of the bus subscriber 60. [

- search features, in particular protocol information and / or CAN-ID (Controller Area Network Identity);

- search locations, especially offset addresses;

The length of each search feature;

A preset number of iterations or search runs;

- the target address for the transmission of one or more sections of data.

The loading of the parameters described above is characterized via block 204 in FIG. In a following block 206, a (new) address for each search feature is determined by arithmetic and / or logic operations on the respective loaded search locations. For example, the length of the bit field (TPID 125) for field 1 ("first execution") shown in FIG. 2 is ascertained through a loaded set of parameters, ), For example, the value "0x8100" may be read.

In the following query block 210, the read information (0x8100) is compared with each search feature. If necessary, for this, a number of comparisons performed step-by-step until a match is identified may be required. This is illustrated by way of example in FIG. 3 with three additional query blocks 212, 214 and 216.

A method is also described by means of blocks 204, 206, 208, 210, 212, 214, 216, 218 and 220 (see below) The data of the bus subscriber 60 of the first bus subscriber 60 may be analyzed or the data may be transferred from the first bus subscriber 60 via the bus system 12 to one or more And is transmitted to the second bus subscriber 60.

The number of comparisons to be performed step by step in accordance with the "depth" of the above procedure, especially query blocks 210, 212, 214 and 216, can be configured, for example, because anticipated protocols are already known. Alternatively, the depth can also be determined according to, for example, intermediate results of data analysis obtained afterwards, and / or other factors. If no correspondence is identified, each protocol is identified as an "unknown " protocol. Thereby, it is possible to transfer the specific sub-reactions, for example the processing unit of one of the processing units 20_1 to 20_n, and / or the bus subscriber, to the direct memory access controller 40 or controller 42 or the programmable processing unit 44, ("Error flag") for an interrupt request ("error interrupt") to one of the bus subscribers 60 can be performed. This is illustrated via block 218 in FIG.

After the first search feature (the "search criteria") is determined, in the following query block 220, the data of the Ethernet frame 100 To the target address of the second bus subscriber 60 is checked. Such checking may be performed, for example, according to the number of iterations or search operations already performed, or may be performed according to configuration information, or parameters loaded within block 204. [ The above-described iterative steps are performed in accordance with path 222 between the output of query block 220 and the input of block 204 in FIG.

If the " final "search feature is still not identified, then after the passage of path 222, loading of one or more additional parameter sets or parameters, and query block 210 and optional query blocks 212, 214 and 216 are performed. In addition, reference is made to the numbers "2" and "3" indicated in the circles in Fig. 3 ("Additional Runs 2 and 3").

For example, the retrieved protocol may correspond to an Ethernet type IPv6 having the search feature "0x86DD ".

If no (additional) iterative steps through path 222 are required, then the program sequence begins at query block 220 and branches to trailing block 224. [ At block 224, the configuration of direct memory access controller 40 is performed, and the configuration includes the following variables.

A source address determined from a known start address and, for example, an offset address constructed in advance, especially using arithmetic and / or logic operations. In this case, the offset address is preset, for example, according to the search feature, or is determined according to the search feature. This preferably allows, for example, only certain portions of the considered data to be transmitted, and allows unrelated portions (e.g., headers, etc.) to be excluded. Preferably, the offset address is characterized by a parameter loaded in block 204.

- Target address that is preset or determined based on search characteristics. Preferably, the target address is characterized by a parameter loaded in block 204. [

- The number of bytes to transfer each of the data. In one embodiment, the number corresponds directly to the payload length 146 shown in FIG. 2, corresponding to the field indicated by the number "4" in FIG. In one further embodiment, the above-described number is determined by an offset under the use of arithmetic and / or logic operations. For example, the offset is characterized via a parameter loaded in block 204. [

After the direct memory access control device 40 is configured in block 224, a following block 226 is used to transfer a second memory address from the first bus subscriber 60 via the bus system 12, The transmission of data to the bus subscriber 60 is performed. In this case, the data may be transferred into the last "dedicated" storage area that can be preset, or into a storage area configured as a circular buffer. Here, the storage areas may be, for example, the main memory 30 or one of the local memories 30_1 to 30_n (refer to FIG. 1). ("Entry type") of whether the transfer of data is performed in a dedicated storage area or in a circular buffer, respectively, may be predetermined, for example, by parameters loaded in block 204. [

In one embodiment, the controller 42 is programmed such that data to be transferred from the first bus subscriber 60 to the one or more second bus subscribers 60 by direct memory access is transmitted only partially. In particular, this is done by omitting information that is not required in the second bus subscriber 60 (the "target module"), e.g., header information that is not required and / or protocols that are not required.

After the data is transferred by direct memory access at block 226, one or more additional measures may be performed as follows:

Transmission of an interrupt request ("interrupt") to each of the processing units 20_1 to 20_n, or transmission of signals corresponding to other bus subscribers 60 to which the performed transmission of data should be notified;

Deleting trigger information and / or signaling bits ("flags");

- if the data is characterized via the Ethernet protocol, the release of so-called "descriptors";

Release of storage areas in the main memory 30 or the local memories 30_1 to 30_n; And / or

- the setting of the signaling bit ("new flag") for the notification of the performed transmission of data.

In one embodiment, the direct memory access control device 40 is configured to determine information in the data of the bus subscriber 60 and to determine the length of each section of the data to be transmitted in the data, and to compare it with a reference value. Whereby corresponding method steps are also characterized at the same time. Errors and / or deliberate manipulation can be prevented by the length information and the reference value.

The foregoing data of the bus subscriber 60 may be read by some or all of the direct memory access controller 40 as a selection to determine the above described information or may be read directly by the memory access controller 40 and / And may be temporarily stored in the device 30. [ In one embodiment, determination of the information and / or determination of length is performed iteratively.

In one embodiment, direct memory access controller 40 is configured to perform one or more of the following actions.

Receiving a trigger signal from the first bus subscriber 60;

Receiving or reading data to be transmitted by the memory access of the first bus subscriber 60 or by direct memory access in the main memory 30 according to the trigger signal;

- analysis of at least a portion of the data;

- determining the type of entry for the target memory of the second bus subscriber (60), and determining the type of entry for the first bus subscriber (60) via the bus system (12) using one or more direct memory accesses according to the determined entry type ) Into the target memory of the second bus subscriber (60).

If a data block (message, frame, Ethernet frame 100, etc.) existing in the first bus subscriber 60 or in the main storage device 30 is selected if the data to be transmitted ("payload" Can be performed (see FIG. 6). This is characterized by query block 228 in FIG. If there are a plurality of data segments in the data, or if a plurality of data segments are to be processed differently, branching is performed from the program sequence through path 230 and path 222 back to the start point of block 204 . Otherwise, it branches to block 234 via the path 232 (symbol "4") and the pre-configurable actions can be performed using this block.

Different processing of data segments is possible, for example, in the so-called "SOME / IP protocol ", for example, CAN data (CAN:" controller area network ") or tunneling of FlexRay data can be performed. In this case, different data segments may be sent to different target addresses, e.g., to local memories 30_1 to 30_n (see FIG. 1). This is possible because the target address is characterized by each search feature. This is referred to (reloading) of the parameter sets in block 204 of FIG. After the end of the final transfer, the configured action may be executed via the direct memory access controller 40 (see e.g. block 234). "Flexray" is the name for a serial deterministic and fault-tolerant fieldbus system for use in automobiles.

In other embodiments, for example, in the Ethernet frame, a so-called error flag can be checked (see Figure 4 for this) before the direct memory access controller 40 starts transmitting. 3, query sequence 402 may alternatively branch to the input of query block 220 of FIG. 3 or to the input of block 234 .

If the above-mentioned error flag signals an error, branch to block 234 (FIG. 3) and an appropriate action for the error is performed. For example, if there is an error during the transmission of Ethernet data at block 234, the descriptor for further transmission may be released and then branch back to the beginning of block 202 to wait for a trailing trigger signal there . Otherwise, it branches from the query block 402 to the input of the query block 220 and the program sequence continues to be performed as previously described previously.

In addition, additional measures may be considered. ("Frame"), for example, in the presence of an error flag in the case of other embodiments, may still transmit to the second bus subscriber 60 (the "target address") and / . Since the direct memory access control apparatus 40 identifies the number of bytes to be transferred in the embedded protocol, the direct memory access control apparatus 40 can perform the plausibility check of the number of bytes notified by the descriptor. This is preferably done, for example, by monitoring the start address and end address using a hardware circuit that may be part of the control device 42.

In addition, a validity check of the start address can be performed. To this end, the source address determined for direct memory access transmission is compared with the original starting address of the data. In this case, for example, the source address should not be smaller than the start address. The infringement can be signaled via an error flag in the status register for each data. The status register may be located within direct memory access controller 40 and / or within other bus subscriber 60.

In FIG. 5, a selection or validity check according to the selection of an end address for transmission of data from a first bus subscriber to a second bus subscriber 60 is shown.

3, the program sequence may be stored, for example, as an input to the query block 210 of FIG. 3 or as a block 504 of FIG. 5 As shown in FIG. If the end address is to be determined, then it branches to block 504 and then branches back from block 504 to the beginning of block 204 of FIG. 3 (symbol "1"), Corresponding parameters for monitoring the address are loaded. Otherwise, it branches from the query block 502 to the beginning of the query block 210, and the program sequence continues as described above.

For example, after an Ethernet message is transmitted into the main memory 30 ("external RAM") using a descriptor, the number of each of the received bytes is written into a status register ("status information" The direct memory access control device 40 can read the status information and determine the end address of each piece of data ("message") in the status information.

Monitoring of the end address may be performed, for example, as follows. First, a program sequence is provided up to the symbol "2" in FIG. 3 via blocks 204, 206 and 208 starting from the symbol "1 " Then, at query block 502 of FIG. 5, an optional query is made as to whether an end address should be determined. In this way the end address for the data to be transferred can be determined. Because each address for the last executed transfer is known within the direct memory access controller 40, the hardware circuitry of the direct memory access controller 40 may compare the address to the end address. If the current address exceeds the end address, an error message may occur.

6 shows an example assignment of data sections of the Ethernet frame 100 'to the respective local memories 30_1 to 30_n of the processing units 20_1 to 20_n connected to the bus system 12. [

The depicted elements of the Ethernet frame 100 'are listed below with their reference numerals.

- Ethernet header 132 ';

- IP header 153 ';

- UDP header 602; (UDP: User Datagram Protocol)

- SOME / IP packet 1 604;

- SOME / IP packet 2 606;

- SOME / IP packet N 608

Arrows 610 represent an example assignment for the transmission of SOME / IP packets 604, 606 and 608 performed by direct memory access to local memories 30_1, 30_2 and 30_n via bus system 12 . In this case, a method corresponding to the flowchart of Fig. 3 is used.

In Fig. 7, a first further embodiment of a communication module 50 'is shown. Here, the direct memory access control apparatus 40 according to the present invention is integrated in the communication module 50 '. The element 50_x shown inside the communication module 50 'in FIG. 7 corresponds to one of the communication modules 50_1 to 50_n in FIG. The bus system 12 operates as an internal bus 12'in the communication module 50' so that the communication module 50_x and the direct memory access controller 40 are connected to the bus system 12 in parallel do. Even in this case, the direct memory access control apparatus 40 according to the present invention including the programmable control apparatus preferably includes, as described above with reference to Figures 1 to 6, data (module 50 ' ) And / or the analysis of the DMA transfer (s). ≪ / RTI >

8 shows a second further embodiment of the communication module 50 ". The direct memory access control device 40 according to the present invention is integratedly disposed within the communication module 50 ". 7, this is done in such a way that the bus system 12 is connected only to the communication module 50_x only through the direct memory access controller 40. [ The internal bus 12 "connects the communication module 50_x, which corresponds to one of the communication modules 50_1 to 50_n in Fig. 1, and the direct memory access control device 40, as shown in Fig. , A direct memory access control apparatus 40 according to the present invention including a programmable controller is preferably configured to store the local data of the data (module 50 " (Or data of another bus subscriber 60) and / or an analysis of the DMA transfer (s).

In one preferred embodiment, the communication modules 50 'or 50 "or 50_x of Figures 7 and 8 correspond to an Ethernet communication module. In yet another preferred embodiment, a communication module other than the aforementioned modules of the Ethernet type You can also think.

Direct memory access control device 40 in accordance with the present invention, including programmable control device 42, preferably enables flexible data analyzes and / or DMA transfers between bus subscribers 60, Through this, a particular sequence of analysis or DMA transmission can be modified. Also, for example, in this manner, the data analysis or data transfer to be performed by direct memory access control device 40 may also be matched to communication protocols to be defined in the future. Also, particularly preferably, the direct memory access control apparatus 40 according to the present invention enables flexible deep packet inspection of data packets (interleaving) across a plurality of protocol layers, May be excluded from configurable protocol layers and thus not considered in the context of DMA transmissions to one or more receiving-side bus subscribers 60, for example.

Claims (12)

A terminal 41 for connecting the bus system 12 connecting the plurality of bus subscribers 60 with the direct memory access control apparatus 40 and a control unit 40 for controlling the operation of the direct memory access control apparatus 40. [ (42), the direct memory access control device (40)
Characterized in that the control device (42) is programmable. The direct memory access control apparatus (40) according to claim 1, wherein the direct memory access control apparatus (40) is configured to analyze data (100; 100 ') of a bus subscriber (60) of the bus system (12) Direct memory access control device (40). A direct memory access control apparatus (40) according to any one of the preceding claims, wherein the direct memory access control apparatus (40) is adapted to control the first bus subscriber (60) via the bus system (12) ) To at least one second bus subscriber (60). ≪ / RTI > 3. Direct memory access control apparatus (40) according to claim 1 or 2, wherein the programmable control device (42) comprises a programmable processing unit (44). The control device (42) according to claim 1 or 2,
- Search features;
- search location;
The length of each search feature;
A preset number of iterations or search runs; And
- a target address for transmitting one or more sections of data (100; 100 ');
(E.g., the bus subsystem 60) to one or more of a set of parameters including at least one of the following parameters: < RTI ID = 0.0 & A direct memory access control device (40). 3. A direct memory access control device (40) according to claim 1 or 2, wherein the direct memory access control device (40) determines the information in the data (100; 100 ') of the bus subscriber (60) ), And to compare the length of the section to be transmitted with the reference value. The direct memory access control device (40) according to claim 1 or 2,
- receiving (202) a trigger signal from the first bus subscriber (60);
- Data (100; 100 ') to be transferred by direct memory access in the memories (30_1, 30_2, 30_n) of the main memory (30) or the first bus subscriber (60) according to one trigger signal or the trigger signal Receive or read (208);
- determining an entry type characterizing the memory organization for the target memory (30; 30_1, 30_2, 30_n) of the second bus subscriber (60), and using the one or more direct memory accesses according to the determined entry type (100; 100 ') from the first bus subscriber (60) to the target memory (30; 30_1, 30_2, 30_n) of the second bus subscriber (60)
Direct memory access control device (40) is configured to perform one or more of the actions. 3. Direct memory access control device (40) according to claim 1 or 2, wherein the control device (42) is integrated into the integrated semiconductor circuit of the direct memory access control device (40). 3. A direct memory access control apparatus (40) according to claim 1 or 2, wherein the direct memory access control apparatus (40) is formed as a hardware circuit. A terminal 41 for connecting the bus system 12 connecting the plurality of bus subscribers 60 with the direct memory access control apparatus 40 and a control unit 40 for controlling the operation of the direct memory access control apparatus 40. [ A method for operating a direct memory access controller (40) having a memory (42)
Characterized in that the control device (42) is programmed. 11. The method according to claim 10, wherein the data (100; 100 ') of the bus subscriber (60) of the bus system (12) is analyzed according to programming of the controller (42) and / A method of direct memory access control in which data (100; 100 ') is transferred from a first bus subscriber (60) to one or more second bus subscribers (60) via bus system (12) How it works. 12. The method of claim 10 or 11, wherein information is determined from data (100; 100 ') of the bus subscriber (60) and the length of each section of the data (100; 100' Value of the direct memory access control device.

Images