KR20170080298A - Display device - Google Patents

Abstract

An embodiment of the present invention provides a display device capable of preventing loss of lead lines provided for testing whether a data line is defective and preventing line defects. A display device according to an embodiment of the present invention includes panel pads, data lines connected to one side of the panel pads, and first and second lead lines connected to the other side of the panel pads. The first and second lead lines are alternately arranged, and the first lead lines are disposed on different layers from the second lead lines.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device including lead lines.

Background of the Invention As the age of the information society develops, the importance of flat panel display devices (FPDs) having excellent characteristics such as thinning, lightening, and low power consumption is increasing. Examples of the flat panel display include a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED). Recently, Electrophoretic display devices (EPD) are also widely used.

Among them, liquid crystal display devices and organic light emitting display devices including thin film transistors are excellent in resolution, color display, image quality, and are widely commercialized as display devices for televisions, notebooks, tablet computers, or desktop computers.

A display panel constituting a conventional display device includes a display area in which an image is displayed and a non-display area in which no image is displayed. In the display region, pixels are formed in the regions where the gate lines and the data lines cross each other. The non-display area is disposed on at least one side of the display area. The non-display area includes a pad area. The pad areas are provided with panel pads. An inspection area may be provided on the outer side of the display panel to check whether the display panel is defective or not. In the inspection area, inspection pads for inspecting whether the data lines are defective or lead lines for connecting inspection pads and panel pads are provided. These panel pads may be gate pads or data pads.

In a conventional display device, a passivation layer and a planarization layer are provided to expose the panel pads using a separate mask. In this case, however, there is a problem that the process cost is increased. In order to solve this problem, in a conventional display device, a passivation layer is formed on the entire surface of a base substrate, and then a part of a passivation layer provided on the pad region is removed using a laser to expose the panel pads.

However, since a separate protective film is not provided on the lead lines, some of the lead lines may be lost together with a part of the passivation layer by the laser in the process of removing a part of the passivation layer. The connection between the test pads and the panel pads is cut off when some of the lead lines are lost, which makes it difficult to inspect the display device for defects. In addition, since some of the lead lines are not provided with a separate protective film, line defects may be generated in the display panel due to foreign matter.

An embodiment of the present invention provides a display device capable of preventing loss of lead lines provided for testing whether a data line is defective and preventing line defects.

A display device according to an embodiment of the present invention includes panel pads, data lines connected to one side of the panel pads, and first and second lead lines connected to the other side of the panel pads. The first and second lead lines are alternately arranged, and the first lead lines are disposed on different layers from the second lead lines.

The embodiment of the present invention is such that the first and second lead lines are arranged alternately to each other. Further, the first lead line is provided in the same layer as the light blocking layer, and the second lead line is provided in the same layer as the gate line. Accordingly, a passivation layer and a planarization layer for protecting the first and second lead lines may be provided on the first and second lead lines. As a result, the embodiments of the present invention can prevent the first and second lead lines from being lost by the laser in the process of irradiating the passivation layer and the planarization layer with the laser to expose the panel pads.

In addition, since the passivation layer and the planarization layer protect the first and second lead lines, the embodiment of the present invention can prevent line defects due to foreign objects generated in the process of cutting each of the display panels provided on the array mother substrate .

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an exemplary view showing an array motherboard including a plurality of display panels.
FIG. 2 is an exemplary view showing the adjacent display panels of FIG. 1 in detail; FIG.
3 is a cross-sectional view illustrating one side section of the display region of FIG. 2;
4 is a plan view showing the area A of FIG. 2 in detail;
5 is a cross-sectional view taken along line I-I 'of Fig. 4;
6 is a sectional view of II-II 'of FIG. 4;
7 is a sectional view of III-III 'of FIG. 4;
8 is a plan view schematically showing a display device according to an embodiment of the present invention.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms. It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one. The term "on" means not only when a configuration is formed directly on top of another configuration, but also when a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of the display device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is an exemplary view showing an array mother board including a plurality of display panels. Referring to FIG. 1, a plurality of display panels 100 may be formed on the array mother substrate 10 to reduce the manufacturing cost of the display device.

As the number of the plurality of display panels 100 formed on the array mother substrate 10 increases, the manufacturing cost of the display device can be further reduced. In order to increase the number of display panels 100 formed on the array mother substrate 10, each of the display panels 100 may be divided into display panels 100 adjacent thereto in a first direction (y axis direction) As shown in FIG. That is, the upper side and the lower side of one display panel 100 can be brought into contact with another display panel 100. Specifically, the upper side of one display panel 100 is in contact with the lower side of another display panel 100 adjacent in the first direction (y axis direction), and the lower side of the display panel 100 is in the first direction The upper side of the adjacent display panel 100 can be abutted.

Each of the display panels 100 may be formed to be spaced apart from the display panels 100 adjacent thereto in a second direction (x-axis direction) by a predetermined distance s as shown in Fig. The second direction (x-axis direction) may be a direction intersecting the first direction (y-axis direction). That is, the left and right sides of one display panel 100 may be spaced apart from the other display panels 100 by a predetermined distance s. In this case, the thin film transistors provided in each of the display panels 100 and the test pads for inspecting the defects of the pixels may be provided at a predetermined interval s.

When the plurality of display panels 100 are formed to be in contact with the display panels 100 adjacent to the display panels 100 in the first direction as shown in FIG. 1, panel pads connected to the test pads . The test pads and panel pads may be connected to each other through lead lines and test lines. The panel pads, the lead lines, and the inspection lines of the display panel 100 will be described in detail with reference to the following drawings.

FIG. 2 is an exemplary view showing the adjacent display panels of FIG. 1 in detail. 3 is a cross-sectional view for explaining one side section of the display region of Fig. In FIG. 2, only three display panels 100a, 100b, and 100c adjacent to each other in the first direction (y-axis direction) are shown for convenience of explanation. 2, the display panel abutting on the upper side of the first display panel 100a is illustrated as the second display panel 100b, and the display panel abutted on the lower side of the first display panel 100a is referred to as a third display panel 100b 100c).

2 and 3, each of the display panels 100a, 100b, and 100c includes a display area DA and a non-display area NDA. Gate lines GL and data lines DL are formed in the display region DA and pixels P may be formed in the intersecting regions of the gate lines GL and the data lines DL. Although FIG. 2 shows one pixel P provided in a crossing region of one gate line GL and one data line DL, the display region DA may include a plurality of gate lines GL and a plurality of Data lines DL are formed. In addition, a plurality of pixels P may be provided in the intersecting regions of the plurality of gate lines GL and the plurality of data lines DL. In this case, each of the pixels P may include an organic light emitting element for outputting light and a thin film transistor for driving the organic light emitting element.

More specifically, the display panel 100 includes a base substrate 110, a buffer layer 130, a light blocking layer 125, a thin film transistor T, a passivation layer PAS, a planarization layer PAC, (OLED), an encapsulation layer 180, and an upper substrate 190.

The base substrate 110 may be a glass substrate or a flexible plastic film. For example, the base substrate 110 may include a cellulose resin such as triacetyl cellulose (TAC) or diacetyl cellulose (DAC), a cycloolefin polymer (COP) such as Norbornene derivatives, a cycloolefin copolymer (COC) Polyolefin, polyvinyl alcohol (PVA), polyether sulfone (PES), polyetheretherketone (PEEK), polyetheretherketone (PEEK) such as acrylic resin such as poly (methylmethacrylate), polycarbonate, polyethylene (PE) (Polyimide), a polysulfone (PSF), a fluoride resin, or the like, such as polyethylene terephthalate (PET), polyetherimide (PEI), polyethylenenaphthalate (PEN) But is not limited thereto.

The buffer layer 130 is provided on the base substrate 110. The buffer layer 130 includes a first buffer layer 131 and a second buffer layer 133. The first buffer layer 131 is formed on the front surface of the base substrate 110. The first buffer layer 131 functions to prevent water from penetrating into the display panel 100 from the base substrate 110, which is vulnerable to moisture permeation. For example, the first buffer layer 131 may be silicon dioxide (SiON) or silicon oxynitride (SiON). However, the present invention is not limited thereto.

The second buffer layer 133 is provided on the first buffer layer 131. The second buffer layer 133 prevents impurities such as metal ions from being diffused from the base substrate 110 and penetrating the active layer ACT. In addition, the second buffer layer 133 prevents moisture from penetrating into the display panel 100 to deteriorate characteristics of the thin film transistors T. For example, silicon dioxide (SiNx), silicon nitride (SiNx), silicon oxynitride (SiON), or multilayers thereof, but is not limited thereto.

The light blocking layer 125 is provided between the first buffer layer 131 and the second buffer layer 133. A light blocking layer 125 is provided under the active layer ACT. The light blocking layer 125 protects the active layer (ACT) from laser or light that is externally directed. The light blocking layer 125 may be formed at the same time using the same process as that of the first lead line 141 among the lead lines 141 and 142 shown in FIG. The light blocking layer 125 and the first lead line 141 may be provided on the same layer. The light blocking layer 125 and the first lead line 141 may be the same material. For example, the light blocking layer 125 may be formed of a transparent conductive material such as ITO, but is not limited thereto, and may be formed of a conductive metal material.

The thin film transistor T is provided on the base substrate 110. The thin film transistor T includes an active layer ACT, a gate insulating film GI, a gate electrode GE, an interlayer insulating film ILD, a source electrode SE and a drain electrode DE.

The active layer (ACT) is provided on the second buffer layer 133. The active layer ACT has a first end region A1 located on the side of the source electrode SE and a second end region A2 located on the side of the drain electrode DE and a second end region A2 located between the first end region A1 and the second end region A2. And a region A3. The central region A3 is made of a semiconductor material not doped with a dopant, and the one-end region A1 and the other-end region A2 may be made of a semiconductor material doped with a dopant.

A gate insulating film GI is provided on the active layer ACT. The gate insulating film GI functions to insulate the active layer ACT from the gate electrode GE. The gate insulating film GI covers the active layer ACT and is formed on the entire surface of the display area DA. The gate insulating film GI may be formed of an inorganic film, for example, silicon dioxide (SiNx), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof.

The gate electrode GE is provided on the gate insulating film GI. The gate electrode GE overlaps the central region A3 of the active layer ACT with the gate insulating film GI therebetween. The gate electrode GE is connected to the gate line GL. The gate electrode GE and the gate line GL can be formed simultaneously using the same process. The gate electrode GE and the gate line GL can be disposed in the same layer. The gate electrode GE and the gate line GL may be formed of the same material. In this case, the gate electrode GE and the gate line GL may be formed simultaneously using the same process as the second lead line 142 among the lead lines 141 and 142 shown in FIG. The gate electrode GE, the gate line GL, and the second lead line 142 may be disposed in the same layer. The gate electrode GE, the gate line GL, and the second lead line 142 may be the same material. The gate electrode GE may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) But is not limited to, a single layer or a multi-layer made of any one or an alloy thereof.

An interlayer insulating film ILD is provided on the gate electrode GE. The interlayer insulating film ILD covers the gate electrode GE and may be provided on the entire surface of the base film 110. The interlayer insulating film ILD may be formed of the same inorganic film as the gate insulating film GI, for example, silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON) Do not.

The source electrode SE and the drain electrode DE are disposed apart from each other on the interlayer insulating film ILD. The first contact hole CNT1 for exposing a part of the one end region A1 of the active layer ACT and the part of the other end region A2 of the active layer ACT are formed in the gate insulating film GI and the interlayer insulating film ILD, And a second contact hole CNT2 for exposing the second contact hole. The source electrode SE is connected to the first end region A1 of the active layer ACT via the first contact hole CNT1 and the drain electrode DE is connected to the active layer ACT through the second contact hole CNT2. And the other end area A2.

The source electrode SE and the drain electrode DE are connected to the data line DL. The source electrode SE and the drain electrode DE and the data line DL may be provided simultaneously using the same process. The source electrode SE and the drain electrode DE and the data line DL may be arranged in the same layer. The source electrode SE and the drain electrode DE and the data line DL may be formed of the same material. The source electrode SE and the drain electrode DE may be formed of a metal such as Mo, Al, Cr, Au, Ti, Ni, And copper (Cu), or an alloy thereof. However, the present invention is not limited thereto. The configuration of the thin film transistor T is not limited to the example described above, and can be variously modified to a known configuration that can be easily practiced by those skilled in the art.

The passivation layer PAS is provided on the entire upper surface of the base substrate 110. A passivation layer (PAS) is provided on the thin film transistor (T). The passivation layer (PAS) functions to protect the thin film transistor (T). In this case, the passivation layer PAS may also be provided on the lead lines 141 and 142 of the non-display area NDA. The passivation layer (PAS) may be formed of an inorganic film, for example, silicon dioxide (SiNx), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof.

The planarization layer (PAC) is provided on the entire upper surface of the base substrate 110. A planarizing layer (PAC) is provided on the passivation layer (PAS). The planarization layer (PAC) serves to flatten the upper portion of the base substrate 110 on which the thin film transistor T is provided. In this case, the passivation layer PAS may also be provided on the lead lines 141 and 142 of the non-display area NDA. The planarization layer (PAC) may be formed of, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. But is not limited thereto. A third contact hole CNT3 is formed in the passivation layer PAS and the planarization layer PAC located in the display area DA to expose the drain electrode DE of the thin film transistor T. [ And the drain electrode DE and the anode electrode AND are connected through the third contact hole CNT3.

The organic light emitting element OLED is provided on the thin film transistor T. [ The organic light emitting device OLED includes an anode electrode (AND), an organic layer (EL), and a cathode electrode (CAT). The anode electrode AND is connected to the drain electrode DE of the thin film transistor T through the third contact hole CNT3 provided in the passivation layer PAS and the planarization layer PAC. A bank B is provided between the adjacent anode electrodes (AND), so that the adjacent anode electrodes (AND) can be electrically isolated. The bank B may be formed of, for example, an organic film such as a polyimide resin, an acryl resin, a benzocyclobutene (BCB), or the like, but is not limited thereto.

The organic layer EL is provided on the anode electrode AND. The organic layer EL may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. Further, the organic layer (EL) may further include at least one functional layer for improving the luminous efficiency and / or lifetime of the light emitting layer.

The cathode electrode (CAT) is provided on the organic layer (EL) and the bank (B). When a voltage is applied to the anode electrode (AND) and the cathode electrode (CAT), holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

3, the display panel 100 is implemented by a top emission method. However, the present invention is not limited to this, and the display panel 100 may be implemented by a bottom emission method. In the front emission type, it is preferable that the anode electrode (AND) is formed of a metal material having a high reflectivity such as aluminum, a laminate structure of aluminum and ITO, and the cathode electrode (CAT) is formed of a transparent metal material such as ITO or IZO.

The sealing layer 180 is provided on the thin film transistor T and the organic light emitting element OLED. The sealing layer 180 protects the thin film transistor T and the organic light emitting diode OLED from external impact and prevents moisture from penetrating into the display panel 100.

The upper substrate 190 is provided on the sealing layer 180. The upper substrate 190 may be a protection film when the display panel 100 is implemented in a bottom emission manner and may be a polyimide It may be a plastic film that is flexible as well. However, the present invention is not limited thereto, and the upper substrate 190 may be a metal layer for protecting the thin film transistor T and the organic light emitting diode OLED from external impact and preventing moisture from penetrating.

The non-display area NDA of the display panel 100 is disposed at the edge of the display area DA. The gate driver 120, the gate pads GP, the panel pads DP, the test lines 151 to 153, and the lead lines 141 and 142 are provided in the non-display area NDA.

The gate driver 120 may be formed in a gate driver in panel (GIP) manner on one side of the display area DA. However, the present invention is not limited thereto. The gate driver 120 may be formed on both sides of the display area DA by a GIP method. Alternatively, the gate driver 120 may be formed as a driving chip, mounted on a flexible film, (Not shown).

The gate pads GP may be provided on the first side edge of each of the display panels 100a, 100b, and 100c. Here, the first side may be the lower side of each of the display panels 100a. The gate pads GP are connected to the gate control signal lines GCL. Gate control signal lines (GCL) connect the gate pads (GP) and the gate driver 120.

The panel pads DP may be provided on the first side edge of each of the display panels 100a, 100b, and 100c, like the gate pads GP. In this case, one side of the panel pads DP may be connected to the data lines DL, and the other side of the panel pads DP may be connected to the lead lines 141, 142. The panel pads DP may be data pads.

The lead lines 141 and 142 connect the panel pads DP and the test lines 151 to 153, respectively. The lead lines 141 and 142 may be provided between the panel pads DP of the display panel 100 and at least one of the inspection lines 151 to 153. The lead lines 141 and 142 may be formed across two display panels. That is, the lead lines 141 and 142 may be formed on the second side of another display panel extending from the first side of one of the display panels and adjacent to the one of the display panels. For example, the lead lines 141 and 142 are connected to the panel pads DP provided on the first side of the first display panel 100a. The lead lines 141 and 142 are connected to the test lines 151 to 153 provided on the second side of the third display panel 100a adjacent to the first side of the first display panel 100a. Accordingly, the lead lines 141 and 142 may extend from the first side of the first display panel 100a adjacent to each other and be formed on the second side of the third display panel 100c. That is, the lead lines 141 and 142 may be formed across the first side of the first display panel 100a and the second side of the third display panel 100c which are adjacent to each other.

The lead lines 141 and 142 include first and second lead lines 141 and 142, respectively. The first and second lead lines 141 and 142 are alternately arranged. For example, the lead lines 141 and 142 may be alternately arranged in the order of the first lead line 141, the second lead line 142, and the first lead line 141. One side of each of the first and second lead lines 141 and 142 is connected to each of the panel pads DP. The other side of each of the first and second lead lines 141 and 142 is connected to at least one test line 151.

The first lead line 141 may be provided in the same layer as the light blocking layer 125 provided below the thin film transistor T in the display area DA. The light blocking layer 125 is disposed under the gate electrode GE and is insulated from the gate electrode GE by at least one buffer layer 133. And the second lead line 142 is disposed in the same layer as the gate lines GL. The gate lines GL are disposed under the data lines DL. The gate lines GL intersect the data lines DL and are insulated from the data lines DL by a gate insulating film GI. In this case, the second lead line 142 may be disposed in the same layer as the gate lines GL. On the first and second lead lines 141 and 142, a passivation layer (PAS) and a planarization layer may be provided.

The first and second lead lines 141 and 142 connected to the panel pads DP are alternately arranged and the first and second lead lines 141 and 142 are formed on different layers . Also, a passivation layer (PAS) and a planarization layer (PAC) are provided on the first and second lead lines 141 and 142. As a result, in the embodiment of the present invention, since the passivation layer PAS and the planarization layer PAC protect the first and second lead lines 141 and 142, in order to expose the panel pads DP, It is possible to prevent the first and second lead lines 141 and 142 from being lost by the laser in the process of removing a part of the planarization layer (PAS) and the planarization layer (PAC).

In the embodiment of the present invention, since the passivation layer PAS and the planarization layer PAC provided on the first and second lead lines 141 and 142 serve as a protective film, It is possible to reduce line defects due to foreign substances generated in the process of scribing each of the display panels provided. These lead lines will be described later in conjunction with FIG. 4 to FIG.

The inspection lines 151 to 153 may be provided on the second side edge facing the first side of each of the display panels 100a, 100b, and 100c. Here, the second side may be the upper side of each of the display panels 100a. The test lines 151 to 153 connect the test pads IP and the panel pads DP of the display panel 100 adjacent to the test lines 151 to 153 and the gate pads GP. For example, the panel pads DP and the gate pads GP provided on the first side of the first display panel 100a are electrically connected to the inspection lines 151 to 153 provided on the second side of the third display panel 100c Lt; / RTI > The panel pads DP and the gate pads GP provided on the first side of the second display panel 100b are connected to the inspection lines 151 to 153 provided on the second side of the first display panel 100a, Can be connected. The test pads IP may be provided at predetermined intervals s between the display panels 100a, 100b, and 100c and the adjacent display panels in the second direction as shown in FIG. 1, but the present invention is not limited thereto . Although only three test lines 151 to 153 are illustrated in FIG. 2 for convenience of description, the number of test lines is not limited thereto.

Although the present invention has been described with reference to the case where the panel pads are data pads in the description of the present invention, the present invention is not limited thereto. For example, the embodiment of the present invention can be applied to the case where the gate driver 120 is manufactured as a driving chip, mounted on a flexible film, and attached to one side of the display panel 100 by a tape automated bonding (TAB) method. In this case, the panel pads according to embodiments of the present invention may be gate pads, and one side of the panel pads may be connected to the gate lines.

FIG. 4 is a detailed plan view of region A of FIG. 2 according to an embodiment of the present invention. 5 is a cross-sectional view taken along the line I-I 'of FIG. 6 is a cross-sectional view taken along the line II-II 'in FIG. 7 is a sectional view of III-III 'of FIG. Therefore, the same reference numerals are assigned to the same components, and repetitive descriptions of repetitive portions in the materials, structures and the like of the respective components are omitted.

4 to 7, one side of the panel pads DP may be connected to the data lines DL, and the other side of the panel pads DP may be connected to the lead lines 141 and 142. The panel pads DP and the lead lines 141 and 142 may be provided in the non-display area NDA of the display panel 100.

A first buffer layer 131 is provided on the base substrate 110 disposed in the non-display area NDA, as shown in FIG. A first lead line 141 is provided on the first buffer layer 131. In this case, the first lead line 141 may be provided in the same layer as the light blocking layer shown in FIG. 3, and may be the same material. A second buffer layer 133 and a gate insulating film GI are sequentially formed on the first read line 141. [ A second lead line 141 is provided on the gate insulating film GI. In this case, the second lead line 141 may be provided in the same layer as the gate line shown in FIG. 2, and may be the same material. The first and second lead lines 141 and 142 may be insulated by the second buffer layer 133.

As described above, each of the first and second lead lines 141 and 142 may be provided in different layers and may be alternately arranged. An interlayer insulating layer (ILD), a passivation layer (PAS), and a planarization layer (PAC) may be sequentially formed on the first and second lead lines 141 and 142. An interlayer insulating layer (ILD), a passivation layer (PAS), and a planarization layer (PAC) may be sequentially formed on the first and second lead lines 141 and 142.

The panel pads DP may be provided in the non-display area NDA of the display panel 100. [ The panel pads DP are provided on the base substrate 110 as shown in Fig. On the base substrate 110, a buffer layer 130 and a gate insulating film GI are sequentially provided. In this case, the second lead line 142 may be connected to the other side of the panel pad DP. For example, each of the panel pads DP may include first and second panel pads DP1 and DP2. In this case, the first panel pad DP1 may be disposed on the same layer as the gate line, and may be connected to the second lead line 142. [ The second panel pad DP2 is disposed on the same layer as the data line DL and can be connected to the data line DL.

The first and second panel pads DP1 and DP2 may be connected through the pad portion contact hole PCNT. In this case, the data line DL connected to the second panel pad DP2 and the second lead line 142 connected to the first panel pad DP1 may be electrically connected. The protective electrode 150 may be provided on the panel pad DP. The protective electrode 150 functions to protect the panel pad DP. In the embodiment of the present invention, a panel pad DP composed of two layers is shown, but the configuration of the panel pad DP can be variously changed.

The first lead line 141 may be connected to the other side of the panel pads DP as shown in Figs. In this case, the other side of the panel pad DP may be connected to a part of the first lead line 141 provided on the base substrate 110. In this case, the second buffer layer 133, the gate insulating film GI, and the interlayer insulating film ILD provided on the first lead line 141 are provided with a lead portion contact hole (not shown) for exposing a part of the first lead line 141 LCNT). The other side of the panel pad DP is electrically connected to the first lead line 141 through the lead portion contact hole LCNT.

In the embodiment of the present invention, the first and second lead lines 141 and 142 are arranged alternately with each other. Also, the first lead line 141 is provided in the same layer as the light blocking layer 125, and the second lead line 142 is provided in the same layer as the gate line. The passivation layer PAS and the planarization layer PAC that protect the first and second lead lines 141 and 142 may be provided on the first and second lead lines 141 and 142. [ As a result, in the embodiment of the present invention, since the passivation layer (PAS) and the planarization layer (PAC) protect the first and second lead lines 141 and 142, It is possible to prevent the first and second lead lines 141 and 142 from being lost by the laser in the process of irradiating the laser on the planarization layer (PAS) and the planarization layer (PAC).

In addition, since the passivation layer (PAS) and the planarization layer (PAC) protect the first and second lead lines 141 and 142, the embodiment of the present invention can prevent the display panels It is possible to reduce line defects due to foreign matter generated in the step of cutting the substrate.

8 is a plan view schematically showing a display device according to an embodiment of the present invention. 8, the X axis represents the direction parallel to the gate lines, the Y axis represents the direction parallel to the data lines, and the Z axis represents the height direction of the OLED display.

8, a display device according to an embodiment of the present invention includes a display panel 100, a source drive integrated circuit (IC) 310, a flexible film 330, a circuit board (not shown) 350, and a timing controller 400.

The display panel 100 includes a display area DA, and a non-display area NDA. Gate lines and data lines are formed in the display region DA, and pixels may be formed in the intersecting regions of the gate lines and the data lines. The non-display area NDA is provided with a gate driver 120, gate pads, panel pads, test lines, and lead lines. Such a display panel 100 has been described with reference to Figs.

The source drive IC 310 receives the digital video data and the source control signal from the timing controller 400. The source driver IC 310 converts the digital video data into analog data voltages according to the source control signal and supplies the analog data voltages to the data lines. When the source drive IC 310 is manufactured as a driving chip, the source drive IC 310 may be mounted on the flexible film 330 using a chip on film (COF) method or a chip on plastic (COP) method.

In the non-display area NDA of the display panel 100, panel pads such as data pads are provided. Wires connecting the panel pads and the source drive IC 310 and wirings connecting the panel pads and the wirings of the circuit board 350 may be formed on the flexible film 330. The flexible film 330 is attached on the panel pads using an anisotropic conducting film, whereby the wiring of the flexible film 330 can be connected to the panel pads.

The circuit board 350 may be attached to the flexible films 330. The circuit board 350 may be implemented with a plurality of circuits implemented with driving chips. For example, the timing controller 400 may be mounted on the circuit board 350. The circuit board 350 may be a printed circuit board or a flexible printed circuit board.

The timing controller 400 receives digital video data and timing signals from an external system board (not shown). The timing control unit 400 generates a gate control signal for controlling the operation timing of the gate driving unit 120 and a source control signal for controlling the source drive ICs 330 based on the timing signal. The timing controller 400 supplies a gate control signal to the gate driver 120 and a source control signal to the source driver ICs 310. [

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of. Therefore, the scope of the present invention is defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present invention.

100: display panel 110: base substrate
120: gate driver 125: light blocking layer
130: buffer layer 141: first lead line
142: second lead line 150: protective electrode
180: sealing layer 190: upper substrate
310: Source drive IC 330: Flexible film
350: circuit board 400: timing control unit
T: thin film transistor OLED: organic light emitting diode
DL: Data line DP: Panel pad
GL: gate line P: pixel

Claims (7)

Panel pads;
Data lines connected to one side of the panel pads; And
And first and second lead lines connected to the other side of the panel pads,
The first and second lead lines are arranged alternately,
Wherein the first lead lines are disposed on different layers from the second lead lines. The method according to claim 1,
Gate lines disposed below the data lines, intersecting the data lines and insulated from the data lines by a gate insulating film; And
Further comprising a light blocking layer disposed below the gate lines and insulated from the gate lines by at least one buffer layer,
Wherein the first lead lines are disposed in the same layer as the light blocking layer. 3. The method of claim 2,
And the second lead lines are disposed in the same layer as the gate lines. The method according to claim 1,
And a passivation layer and a planarization layer for protecting the first and second lead lines on the first and second lead lines. 3. The method of claim 2,
Wherein the first and second lead lines are insulated from each other by the at least one buffer layer. The method according to claim 1,
Wherein the first lead line is connected to one of the panel pads through a lead portion contact hole. The method according to claim 1,
And a protective electrode provided on the panel pads.

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