KR20170049678A - Method for epitaxy growth and method for forming semiconductor structure using the same - Google Patents

Abstract

The present invention relates to a semiconductor structure forming method using an epitaxial process to prevent deformation due to migration. The semiconductor structure forming method includes the steps of: forming a silicon germanium layer by using low-temperature selective epitaxial growth on a semiconductor substrate including silicon; forming a silicon blocking layer on the silicon germanium layer for suppressing the migration of the silicon germanium layer; executing heat treatment on the semiconductor substrate with the silicon germanium layer and silicon blocking layer formed thereon; removing the silicon blocking layer; and forming a silicon cap layer by using high-temperature selective epitaxial growth on the silicon germanium layer while maintaining the heat treatment temperature.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an epitaxial growth method and a method of forming a semiconductor structure using the epitaxial growth method.

The present invention relates to a semiconductor structure, and more particularly, to a method of epitaxy growth and a method of forming a semiconductor structure using the epitaxy growth method.

The electronic device includes a large number of individual semiconductor devices, such as transistors, capacitors, and resistors. These semiconductor devices are internally connected to form complex integrated circuits such as memory devices, logic devices and microprocessors.

In the manufacturing process of semiconductor devices, epitaxy growth can be applied. A semiconductor layer of silicon, silicon germanium or the like can be formed by epitaxial growth.

Embodiments of the present invention provide an epitaxial growth method capable of preventing deformation by migration and a method of forming a semiconductor structure using the epitaxial growth method.

A method of forming a semiconductor structure according to an embodiment of the present invention includes forming a low temperature growth layer on a semiconductor substrate; Forming a blocking layer on the low-temperature grown layer; A heating process of the semiconductor substrate on which the blocking layer and the low temperature growth layer are formed; Removing the blocking layer; And forming a high-temperature growth layer on the low-temperature growth layer while maintaining the temperature of the heating treatment.

A method of forming a semiconductor structure according to an embodiment of the present invention includes: preparing a semiconductor substrate including a first region and a second region; Forming a first semiconductor layer by low-temperature selective epitaxial growth on the second region; Forming a blocking layer on the first semiconductor layer and the first region; A heating process of the semiconductor substrate on which the blocking layer and the first semiconductor layer are formed; Removing the blocking layer; And forming the second semiconductor layer by high-temperature selective epitaxial growth on the first semiconductor layer while maintaining the heating treatment temperature.

A method of forming a semiconductor structure according to an embodiment of the present invention includes forming a silicon germanium layer by low-temperature selective epitaxial growth on a semiconductor substrate including silicon; Forming a silicon blocking layer on the silicon germanium layer to inhibit migration of the silicon germanium layer; A step of heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed; Removing the silicon blocking layer; And forming a silicon cap layer by high temperature selective epitaxial growth on the silicon germanium layer while maintaining the heating treatment temperature.

A method of forming a semiconductor structure according to an embodiment of the present invention includes: preparing a semiconductor substrate including a silicon-base region and an insulating region; Performing low temperature selective epitaxy growth to form a silicon germanium layer on the silicon-base region; Forming a silicon germanium layer on the silicon germanium layer and an isolation region and a silicon blocking layer having non-selectivity for the isolation region; Heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed; Removing the silicon blocking layer; And performing high temperature selective epitaxial growth to form a silicon cap layer on the silicon germanium layer while maintaining the heating process temperature.

A method of forming a semiconductor structure according to an embodiment of the present invention includes: preparing a semiconductor substrate including a channel forming region and a source / drain forming region; Forming a gate structure on the channel forming region; Etching the source / drain formation region to form a sigmal trench; Performing low temperature selective epitaxy growth to form a silicon germanium layer filling the trench; Forming a silicon blocking layer having non-selectivity on the silicon germanium layer on the silicon germanium layer; Heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed; Removing the silicon blocking layer; And performing high temperature selective epitaxial growth to form a silicon cap layer on the silicon germanium layer while maintaining the heating process temperature.

The technique has the effect of inhibiting the migration of the silicon germanium layer during temperature rise (Temparature-up) for high temperature selective epitaxy growth by forming a blocking layer on the silicon germanium layer.

In addition, this technique has the effect of securing the selective growth of the silicon layer with respect to the silicon germanium layer by removing the blocking layer after suppressing the migration of the silicon germanium layer.

1A to 1E illustrate a method of forming a semiconductor structure according to the first embodiment.
2A to 2F illustrate a method of forming a semiconductor structure according to the second embodiment.
3A and 3B illustrate a method of forming a semiconductor structure according to a modification of the second embodiment.
4A to 4C illustrate a first application example of the present embodiments.
Fig. 5 illustrates a modified example of the first application example.
Fig. 6 illustrates still another modification of the first application example.
Fig. 7 illustrates a second application example of the present embodiments.
Fig. 8 illustrates a second application example of the present embodiments.
Fig. 9 illustrates a third application example of the present embodiments.
Fig. 10 illustrates a fourth application example of the present embodiments.

The embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematics of the present invention. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1A to 1E illustrate a method of forming a semiconductor structure according to the first embodiment.

As shown in Fig. 1A, a semiconductor substrate 101 can be prepared. The semiconductor substrate 101 may comprise suitable materials for semiconductor processing. The semiconductor substrate 101 may comprise a silicon-based substrate. The semiconductor substrate 101 may include a silicon substrate, a silicon germanium (SiGe) substrate, or an SOI (Silicon On Insulator) substrate. The semiconductor substrate 101 may be doped with an N-type dopant or a P-type dopant. For example, the semiconductor substrate 101 may be doped with a P-type dopant at a low concentration. As described above, the semiconductor substrate 101 may be a silicon-base material.

Next, a first semiconductor layer 102 may be formed on the semiconductor substrate 101. The first semiconductor layer 102 may include a low-temperature growth layer. The low temperature growth layer can refer to a material that is grown at a temperature lower than about 700 ° C.

The first semiconductor layer 102 may be formed by Selective Epitaxy Growth (SEG). For example, it may be formed with selectivity with respect to the semiconductor substrate 101. The first semiconductor layer 102 may be formed by Low temperature-SEG (LT-SEG). For example, low temperature selective epitaxial growth for forming the first semiconductor layer 102 may be performed at a first temperature, i.e., a temperature less than 700 ° C. The first semiconductor layer 102 may be a compound containing silicon. The first semiconductor layer 102 and the semiconductor substrate 101 may be different materials. The first semiconductor layer 102 may comprise silicon and germanium. For example, the first semiconductor layer 102 may comprise a silicon germanium layer (SiGe layer). The first semiconductor layer 102 may comprise a silicon germanium layer grown at a low temperature.

For low temperature selective epitaxial growth (LT-SEG) of the first semiconductor layer 102, a growth gas and an etch gas may be used. The growth gas may include a silicon-containing gas and a germanium-containing gas. The silicon-containing gas may comprise silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or dichlorosilane (SiH ₂ Cl ₂ ). The germanium containing gas may comprise germane (GeH ₄ ). The etch gas may include HCl. The first semiconductor layer 102 may comprise a silicon germanium epitaxial layer. The silicon germanium epitaxial layer can be formed by low temperature selective epitaxy growth at 500 to 650 占 폚.

As shown in FIG. 1B, a blocking layer 103 may be formed. The blocking layer 103 may also be referred to as a seed layer. The blocking layer 103 may be a material for suppressing the migration of the first semiconductor layer 102. That is, when the temperature is raised to the growth temperature of the subsequent second semiconductor layer, the migration of the first semiconductor layer 102 can be suppressed. The blocking layer 103 may be non-selective for lower materials.

The blocking layer 103 may be a non-selective growth layer. Blocking layer 103 may be formed by non-selective epitaxial growth (non-SEG). The blocking layer 103 may comprise a silicon layer. The silicon layer may be formed by a CVD reaction of a silicon-containing gas and a hydrogen (H ₂ ) gas. The silicon containing gas may comprise silane, disilane or dichlorosilane. During formation of the silicon layer for non-selectivity, no HCl is spilled. The blocking layer 103 may be formed at a low temperature at which migration of the first semiconductor layer 102 does not occur.

As shown in Fig. 1C, a heating treatment 104 is performed. The semiconductor substrate 101, the first semiconductor layer 102, and the blocking layer 103 can be heated by the heating process 104. The heating process 104 may include a temperature-up process. That is, the temperature is raised to the growth temperature for forming the second semiconductor layer. Migration of the first semiconductor layer 102 is suppressed by the blocking layer 103 since the blocking layer 103 covers the first semiconductor layer 102. [ During the heating process 104, the migration of the silicon-base semiconductor substrate 101 does not occur.

As described above, the heating process 104 is a process of raising the growth temperature to the second growth temperature for forming the second semiconductor layer, that is, the second temperature. The first semiconductor layer 102 is heated by the heating process 104 and migration of the heated first semiconductor layer 102 may occur. However, in this embodiment, by forming the blocking layer 103, The migration of the memory 102 can be suppressed.

The heating process 104 can be raised to a temperature at which migration of the semiconductor substrate 101 does not occur. In the case where the semiconductor substrate 101 is a silicon substrate, the migration of silicon occurs at a temperature higher than 700 ° C. And the second temperature can be raised to 700 DEG C by the heating process 104. [

As shown in FIG. 1D, the removal process 105 of the blocking layer 103 may be performed.

HCl may be used to remove the blocking layer 18. The blocking layer 103 may be removed from the surface of the first semiconductor layer 102.

As shown in FIG. 1E, a second semiconductor layer 106 may be formed. The second semiconductor layer 106 can be formed without changing the temperature, that is, maintaining the heating processing temperature (second temperature). The second semiconductor layer 106 may include a high-temperature growth layer. The second semiconductor layer 106 can be grown at a temperature higher than about 700 캜. The second semiconductor layer 106 may contain silicon. The first semiconductor layer 102 and the second semiconductor layer 106 may be different materials. The second semiconductor layer 106 may comprise a silicon layer. The second semiconductor layer 106 may be formed by selective epitaxial growth (SEG). That is, it can be selectively grown only on the upper surface of the first semiconductor layer 102. The second semiconductor layer 106 may comprise a silicon epitaxial layer grown at a high temperature SEG (HT-SEG).

For high temperature selective epitaxial growth (HT-SEG) of the second semiconductor layer 106, a growth gas and an etching gas may be used. The growth gas may comprise a silicon-containing gas. The silicon-containing gas may comprise silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or dichlorosilane (SiH ₂ Cl ₂ ). The etch gas may include HCl. The second semiconductor layer 106 may be formed by a high-temperature SEG. For example, high temperature selective epitaxial growth (HT-SEG) for forming the second semiconductor layer 106 may be performed at a second temperature, i.e., 700 캜 or higher.

As described above, the hetero semiconductor layer 107 including the first semiconductor layer 102 and the second semiconductor layer 106 can be formed by forming the second semiconductor layer 106. The hetero semiconductor layer 107 may include a low temperature growth layer and a high temperature growth layer. The hetero semiconductor layer 107 may include a low-temperature epitaxial layer and a high-temperature epitaxial layer. The hetero semiconductor layer 107 may comprise a low temperature epitaxial layer by a low temperature selective epitaxy process and a high temperature epitaxial layer by a high temperature selective epitaxy process. The hetero semiconductor layer 107 may include a silicon germanium epitaxial layer and a silicon epitaxial layer. Here, the silicon germanium epitaxial layer may be formed by a low temperature selective epitaxy process, and the silicon epitaxial layer may be formed by a high temperature selective epitaxy process. In another embodiment, the silicon epitaxial layer may be referred to as a silicon cap layer.

2A to 2F illustrate a method of forming a semiconductor structure according to the second embodiment. The second embodiment may be the same as or similar to the first embodiment. The second embodiment describes the non-selectivity of the blocking layer. The remaining elements except the insulating layer and the blocking layer will be referred to the first embodiment.

As shown in Fig. 2A, a semiconductor substrate 101 can be prepared. A trench 201 may be formed in the semiconductor substrate 101. [ The trench 201 may be formed by etching the semiconductor substrate 101.

An insulating region 202 may be formed in the trench 201. The silicon-base region 101A may be defined in the semiconductor substrate by the isolation region 202. [ The isolation region 202 may include at least one or more layers. The isolation region 202 may comprise silicon oxide, silicon nitride, or a combination thereof. The isolation region 202 includes a first insulating layer 203 lining the surface of the trench 201 and a second insulating layer 204 filling the trench 201 on the first insulating layer 203 . The first insulating layer 203 and the second insulating layer 204 may be different materials. For example, the first insulating layer 203 may comprise silicon oxide, and the second insulating layer 204 may comprise silicon nitride. In another embodiment, the isolation region 202 may consist of only one insulating layer.

As shown in FIG. 2B, the first semiconductor layer 102 may be formed. The first semiconductor layer may be selectively formed on the silicon-base region 101A. That is, the first semiconductor layer 102 is not formed on the insulating region 202. The first semiconductor layer 102 may include a low temperature growth layer. The first semiconductor layer 102 may be grown at a temperature less than about 700 < 0 > C. The first semiconductor layer 102 may be a compound containing silicon. The first semiconductor layer 102 and the silicon-base region 101A may be different materials. The first semiconductor layer 102 may comprise silicon and germanium. For example, the first semiconductor layer 102 may comprise a silicon germanium layer (SiGe layer). The first semiconductor layer 102 may comprise a silicon germanium layer grown at a low temperature. The first semiconductor layer 102 may be formed by low temperature selective epitaxial growth (LT-SEG). For low temperature selective epitaxial growth (LT-SEG) of the first semiconductor layer 102, a growth gas and an etching gas may be used. The growth gas may include a silicon-containing gas and a germanium-containing gas. The silicon-containing gas may comprise silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or dichlorosilane (SiH ₂ Cl ₂ ). The germanium containing gas may comprise germane (GeH ₄ ). The etch gas may include HCl. The first semiconductor layer 102 may be formed by low temperature selective epitaxial growth. For example, low temperature selective epitaxial growth for forming the first semiconductor layer 102 can be performed at a first temperature, i.e., 500 to 650 캜.

As described above, the first semiconductor layer 102 has selectivity for the silicon-base region 101A.

As shown in FIG. 2C, a blocking layer 103 may be formed. The blocking layer 103 may also be referred to as a seed layer. The blocking layer 103 may be a material for suppressing the migration of the first semiconductor layer 102. That is, the migration of the first semiconductor layer 102 can be suppressed when the temperature is raised to the growth temperature of the subsequent high temperature growth layer. The blocking layer 103 may be non-selective for the underlying materials. That is, the blocking layer 103 may be formed to cover both the first semiconductor layer 102, the first insulating layer 203, and the second insulating layer 204. The blocking layer 103 may be formed with different deposition rates on the lower materials. For example, the first thickness T1 on the first semiconductor layer 102, the second thickness T2 on the first insulating layer 203, and the third thickness T3 on the second insulating layer 204 are different from each other can be different. May be formed thickest on the first semiconductor layer 102 and may be formed to be thinnest on the first insulating layer 203. [ For example, the blocking layer 103 is formed thickest on the silicon-based material and thinnest on the oxide. The blocking layer 103 is formed thicker on the nitride than the oxide. The third thickness T3 on the second insulating layer 204 may have a value between the first thickness T1 and the second thickness T2. This difference in thickness is due to the nucleation difference due to the lower material.

The blocking layer 103 may be a non-selective growth layer. The blocking layer 103 may be formed by non-selective epitaxy growth on the underlying structure. The blocking layer 103 may comprise a silicon layer. The silicon layer may be formed by a CVD reaction of a silicon-containing gas and a hydrogen (H ₂ ) gas. The silicon containing gas may comprise silane, disilane or dichlorosilane. During formation of the silicon layer for non-selectivity, no HCl is spilled. The blocking layer 103 may be formed at a low temperature at which migration of the first semiconductor layer 102 does not occur.

As shown in FIG. 2D, the heating process 104 is performed. The semiconductor substrate 101, the first semiconductor layer 102, and the blocking layer 103 can be heated by the heating process 104. The heating process 104 may include a temperature elevation process. That is, the temperature is raised to the growth temperature for forming the second semiconductor layer. Migration of the first semiconductor layer 102 is suppressed by the blocking layer 103 since the blocking layer 103 covers the first semiconductor layer 102. [ During the heating process 104, the migration of the silicon-base semiconductor substrate 101 does not occur.

As described above, the heating process 104 is a process of raising the growth temperature to the second growth temperature for forming the second semiconductor layer, that is, the second temperature. Migration of the first semiconductor layer 102 may occur by the heating process 104, but migration of the first semiconductor layer 102 can be suppressed by forming the blocking layer 103 in this embodiment.

The heating process 104 can be raised to a temperature at which migration of the semiconductor substrate 101 does not occur. In the case where the semiconductor substrate 101 is a silicon substrate, the migration of silicon occurs at a temperature higher than 700 ° C. And the second temperature can be raised to 700 DEG C by the heating process 104. [

As shown in FIG. 2E, the removal process 105 of the blocking layer 103 may be performed.

HCl may be used to remove the blocking layer 18. The blocking layer 103 may be removed from the surface of the first semiconductor layer 102 and the isolation region 202.

As shown in FIG. 2F, a second semiconductor layer 106 may be formed. The second semiconductor layer 106 can be formed without changing the temperature, that is, without lowering or raising the temperature, while maintaining the second temperature. The second semiconductor layer 106 may include a high-temperature growth layer. The second semiconductor layer 106 can be grown at a temperature higher than about 700 캜. The second semiconductor layer 106 may contain silicon. The first semiconductor layer 102 and the second semiconductor layer 106 may be different materials. The second semiconductor layer 106 may comprise a silicon layer. The second semiconductor layer 106 may be formed by high temperature selective epitaxial growth (HT-SEG). That is, it can be selectively grown only on the upper surface of the first semiconductor layer 102. The second semiconductor layer 106 may comprise a silicon epitaxial layer grown at a high temperature.

For high temperature selective epitaxial growth (HT-SEG) of the second semiconductor layer 106, a growth gas and an etching gas may be used. The growth gas may comprise a silicon-containing gas. The silicon-containing gas may comprise silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or dichlorosilane (SiH ₂ Cl ₂ ). The etch gas may include HCl. The second semiconductor layer 106 may be formed by high temperature selective epitaxial growth. For example, the high temperature selective epitaxial growth for forming the second semiconductor layer 106 may be performed at a second temperature, i.e., 700 DEG C or higher.

In this manner, the hetero semiconductor layer 107 including the first semiconductor layer 102 and the second semiconductor layer 106 can be formed by forming the second semiconductor layer 106. The hetero semiconductor layer 107 may include a low temperature growth layer and a high temperature growth layer. The hetero semiconductor layer 107 may include a low-temperature epitaxial layer and a high-temperature epitaxial layer. The hetero semiconductor layer 107 may comprise a low temperature epitaxial layer by a low temperature selective epitaxy process and a high temperature epitaxial layer by a high temperature selective epitaxy process. The hetero semiconductor layer 107 may include a silicon germanium epitaxial layer and a silicon epitaxial layer. Here, the silicon germanium epitaxial layer may be formed by a low temperature selective epitaxy process, and the silicon epitaxial layer may be formed by a high temperature selective epitaxy process. In another embodiment, the silicon epitaxial layer may be referred to as a silicon cap layer.

3A and 3B illustrate a method of forming a semiconductor structure according to a modification of the second embodiment. The third embodiment may be similar to the second embodiment. The third embodiment can be used as a seed layer for growing the second semiconductor layer by leaving a part of the blocking layer.

Referring to FIGS. 2A to 2D, a heating process 105 is performed in a state where the blocking layer 103 is formed.

Next, as shown in FIG. 3A, a removal process 105 of the blocking layer 103 may be performed.

HCl may be used to remove the blocking layer 103. The blocking layer 103 is all removed from the surface of the insulating layer 202 and may remain with a constant thickness on the surface of the first semiconductor layer 102. [ Since the thickness formed on the first semiconductor layer 102 is the thickest, the blocking layer 103S can be selectively left only on the first semiconductor layer 102. [ All of the blocking layer 103 may be removed on the isolation region 202. For example, all of the blocking layer 103 is removed on an insulating material such as an oxide and a nitride, and the silicon layer remains only on the silicon germanium epitaxial layer. The residual blocking layer 103S may be used as a seed layer. Hereinafter, it is abbreviated as a seed layer 103S.

As shown in FIG. 3B, the second semiconductor layer 106 may be formed using the seed layer 103S. The second semiconductor layer 106 can be formed without changing the temperature, that is, without lowering or raising the temperature, while maintaining the second temperature. The second semiconductor layer 106 may include a high temperature growth layer. The second semiconductor layer 106 can be grown at a temperature higher than about 700 캜. The second semiconductor layer 106 may contain silicon. The first semiconductor layer 102 and the second semiconductor layer 106 may be different materials. The second semiconductor layer 106 may comprise a silicon layer. The second semiconductor layer 106 may be formed by high temperature selective epitaxial growth (HT-SEG). In other words, it can be selectively grown only on the upper surface of the seed layer 103S. The second semiconductor layer 106 may comprise a silicon epitaxial layer grown at a high temperature.

For high temperature selective epitaxial growth (HT-SEG) of the second semiconductor layer 106, a growth gas and an etching gas may be used. The growth gas may comprise a silicon-containing gas. The silicon-containing gas may comprise silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or dichlorosilane (SiH ₂ Cl ₂ ). The etch gas may include HCl. The second semiconductor layer 106 may be formed by high temperature selective epitaxial growth. For example, the high temperature selective epitaxial growth for forming the second semiconductor layer 106 may be performed at a second temperature, i.e., 700 DEG C or higher.

By forming the second semiconductor layer 106 in this way, the hetero semiconductor layer 107 including the first semiconductor layer 102, the seed layer 103S and the second semiconductor layer 106 can be formed.

As a comparative example, abnormal growth may occur on the isolation region 202, particularly on the nitride, if the removal process 105 using HCl is not carried out. That is, it is difficult to selectively grow the silicon epitaxial layer only on the silicon germanium epitaxial layer.

4A to 4C illustrate a first application example of the present embodiments. A first application example describes a method of forming a field-effect transistor. The field effect transistor according to the first application example may include a PMOSFET.

As shown in FIG. 4A, the semiconductor substrate 301 may include an active region 303 and a device isolation region 302. The element isolation region 302 may be an STI region. As in the second embodiment, the element isolation region 302 may include a first insulating layer and a second insulating layer. A hetero semiconductor layer may be formed on the semiconductor substrate 301. The hetero semiconductor layer may be formed by the above-described embodiments and modifications thereof. For example, the hetero semiconductor layer may include a silicon germanium layer 304 and a silicon cap layer 305. The silicon germanium layer 304 may be formed by a low temperature selective epitaxy process. The silicon cap layer 305 may be formed by a high temperature selective epitaxy process. The migration of the silicon germanium layer 304 is suppressed.

The hetero semiconductor layer including the silicon germanium layer 304 and the silicon cap layer 305 may be a channel region 306. [

Next, a gate structure 307 may be formed on the channel region 306. The gate structure 307 may include a gate insulating layer 308, a gate electrode 309, and a gate cap layer 310.

The gate insulating layer 308 may be formed through thermal oxidation. In another embodiment, the gate insulating layer 308 may be formed by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The gate insulating layer 308 may include a high dielectric material, silicon oxide, silicon nitride, oxynitride, or a combination thereof. The high dielectric material may be an insulating material having a higher dielectric constant than the dielectric constant of silicon oxide and silicon nitride. The high-dielectric material may comprise a metal oxide, a metal oxynitride or a metal silicate. For example, the high-k material may include hafnium oxide, hafnium silicon oxynitride, or hafnium silicate. The high dielectric material may include other high dielectric materials known in addition to the hafnium base material.

After forming the gate insulating layer 308, a gate stack can be formed using a gate stack formation sequence. This can be referred to as an " unetched gate stack. &Quot; To form the gate stack, at least one or more conductive layers may be sequentially deposited. The conductive layer may include a metal-base conductive layer, a silicon-base conductive layer, or a combination thereof. The metal-based conductive layer may be formed of at least one or more layers of a metal base layer. The metal-based conductive layer may comprise titanium, titanium nitride, titanium aluminum nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, aluminum or combinations thereof. In this embodiment, the metal-base conductive layer may comprise a metal or metal base layer having a work function. The silicon-based conductive layer may be doped or undoped. The silicon-based conductive layer may comprise a doped polysilicon layer or an undoped polysilicon layer. The silicon-based conductive layer may initially be formed in an amorphous state or a polycrystalline state, but may be a polycrystalline phase by a subsequent thermal process. Materials for the silicon-based conductive layer may include silicon, silicon germanium or other suitable semiconductors.

After forming the above gate stack, the gate stack can be selectively etched to form the gate structure 307 including the gate insulating layer 308, the gate electrode 309, and the gate cap layer 310. Photolithography and etching processes may be performed to etch the gate stack. For example, the gate stack can be etched using a photoresist pattern (not shown). After etching the gate stack, the gate insulating layer 308 may be etched. The gate electrode 309 may be formed by etching the metal-base conductive layer. The gate cap layer 310 may be formed by etching the silicon-base conductive layer.

As shown in FIG. 4B, a first source / drain region 311 may be formed. A first dopant may be doped to form a first source / drain region 311. A doping technique such as an implant may be applied to dope the first dopant. The first source / drain region 311 may be a lightly doped region. This may be referred to as a source / drain extension region (SDE). The first dopant may comprise a p-type dopant such as boron. In another embodiment, the implant of the first dopant may also be performed on the gate structure. For example, the gate cap layer 310 may be doped with a first dopant.

As shown in FIG. 4C, a sidewall spacer 312 may be formed. Sidewall spacers 312 may comprise silicon oxide, silicon nitride, or combinations thereof. In order to form sidewall spacers 312, a spacer layer may be deposited and etched back.

A second source / drain region 313 may be formed. A second dopant may be doped to form a second source / drain region 313. Doping techniques such as implants can be applied to dope the second dopant. The second source / drain region 313 may be a heavily doped region. This can be referred to as a source / drain region (SD). The second dopant may comprise a p-type dopant such as boron. The first dopant and the second dopant may be of the same type.

Next, a silicide layer 314 may be formed on the second source / drain region 313. The silicide layer 314 may also be formed on the gate cap layer 310. The silicide layer 314 may comprise cobalt suicide, nickel suicide, or nickel platinum suicide.

Fig. 5 illustrates a modified example of the first application example.

Referring to FIG. 5, the channel region 306 including the silicon germanium layer 304 and the silicon cap layer 305 may be at the same level as the upper surface of the element isolation region 302. To this end, the surface of the semiconductor substrate 301 may be recessed before the silicon germanium layer 304 is formed.

Fig. 6 illustrates still another modification of the first application example. 6 illustrates a PMOSFET with an RMG (Replacement Metal Gate) process.

Referring to FIG. 6, an RMG-gate structure (RMG) may be formed on the channel region 306. The RMG gate structure RMG may include a gate insulating layer 308R, a work function metal layer 309R, and a low resistance metal layer 310R. The RMG-gate structure (RMG) can be formed by a known method. For example, after forming the sacrificial gate and sidewall spacers 312, the sacrificial gate is removed to form a recess. Thereafter, a gate insulating layer 308R, a work function metal layer 309R and a low resistance metal layer 310R are formed in the recess. The RMG process is also referred to as a gate-last process.

Fig. 7 illustrates a second application example of the present embodiments. A second application example describes a field effect transistor 400. A second application example describes an eSiGe (embedded SiGe) source / drain region.

As shown in FIG. 7, the semiconductor substrate 401 may include an active region 403 and an isolation region 402. A channel region (not shown) may be formed in the active region 403. A gate structure 407 may be formed on the channel region. The gate structure 407 may include a gate insulating layer 408, a gate electrode 409, and a gate cap layer 410. Sidewall spacers 412 may be formed on both side walls of the gate structure.

The hetero semiconductor layer may be formed in the active region 401 on both sides of the channel region. The hetero semiconductor layer may be formed by the above-described embodiments and modifications thereof. For example, the hetero semiconductor layer may include a silicon germanium layer 405 and a silicon cap layer 406. The silicon germanium layer 405 may be formed by a low temperature selective epitaxy process. The silicon cap layer 406 may be formed by a high temperature selective epitaxy process. The migration of the silicon germanium layer 405 is suppressed.

The hetero semiconductor layer including the silicon germanium layer 405 and the silicon cap layer 406 may be a source / drain region. The source / drain regions may be formed in a sigma (sigma) -shaped trench 404. The silicon germanium layer 405 embedded in the trench 404 is referred to as an eSiGe (Embedded SiGe) structure.

A silicide layer 407 may be formed on the silicon cap layer 406.

8 illustrates a third application example of the present embodiments. The third application example describes the CMOSFET 500. [

Referring to FIG. 8, the CMOSFET 500 includes a PMOSFET including an NMOSFET including a first channel region 306N and a second channel region 306P. The NMOSFET and the PMOSFET can be isolated from each other by the element isolation region 302 formed in the semiconductor substrate 301.

The NMOSFET may have a first gate structure 307N formed on the first channel region 306N. The first gate structure 307N may include a first gate insulating layer 308N, a first gate electrode 309N, and a first gate cap layer 310N. First sidewall spacers 312N may be formed on both sidewalls of the first gate structure 307N. An N-type source / drain region including a first N-type source / drain region 311N and a second N-type source / drain region 313N may be formed in the semiconductor substrate 301 on both sides of the first gate structure 307N . A first silicide layer 314N may be formed on the second N type source / drain region 313N.

The PMOSFET may be formed with a second gate structure 307P on the second channel region 306P. The second gate structure 307P may include a second gate insulating layer 308P, a second gate electrode 309P, and a second gate cap layer 310P. Second side wall spacers 312P may be formed on both sidewalls of the second gate structure 307P. A P-type source / drain region including a first P-type source / drain region 311P and a second P-type source / drain region 313P may be formed in the semiconductor substrate 301 on both sides of the second gate structure 307P . A second silicide layer 314P may be formed on the second P-type source / drain region 313P.

As described above, the second channel region 306P of the PMOSFET may include a silicon germanium layer 304 and a silicon cap layer 305. [ The silicon germanium layer 304 may be formed by a low temperature selective epitaxy process. The silicon cap layer 305 may be formed by a high temperature selective epitaxy process. The migration of the silicon germanium layer 304 is suppressed.

Fig. 9 illustrates a fourth application example of the present embodiments. A fourth application example describes a fin-channel field effect transistor (FINFET) 600.

As shown in FIG. 9, the semiconductor substrate 601 may include an active region 603 and an element isolation region 602. A pin region 604 may be formed in the active region 603. The pin region 604 can be formed by recessing the element isolation region 602 to be lower than the surface of the active region 603. [ The pin region 604 may be covered with the hetero semiconductor layer. That is, the silicon germanium layer 605 and the silicon cap layer 606. The silicon germanium layer 605 and the silicon cap layer 606 may be referred to as a fin channel region. A gate insulating layer 607 may be formed on the fin channel region, and a gate electrode 608 may be formed on the gate insulating layer 607.

The silicon germanium layer 605 may be formed by a low temperature selective epitaxy process. The silicon cap layer 606 may be formed by a high temperature selective epitaxy process. The migration of the silicon germanium layer 605 is suppressed.

Although not shown, the fin channel field effect transistor (FINFET) 600 may further include a source / drain region. Here, the source / drain regions and the silicon germanium layer may also be eSiGe structures.

Fig. 10 illustrates a fifth application example of the present embodiments. The fifth application example describes the memory device 700. [

The memory device 700 may include a cell region 700C and a peripheral circuit region 700P. And may include a buried word line 703, a bit line BL, and a memory element M in a cell region 700C. Embedded word line 703 may be embedded in gate trench 701. A cell gate insulating layer 702 may be formed on the surface of the gate trench 701. A sealing layer 704 may be filled on the buried word line 703. The bit line BL may be connected to the first doped region 705. The memory element M may be connected to the second doped region 705.

Peripheral transistors may be formed in the peripheral circuit region 700P. The peripheral transistor may comprise a transistor according to FIG. 4C. Accordingly, the peripheral transistor may include a channel region composed of a hetero semiconductor layer. The hetero semiconductor layer may include a silicon germanium layer 304 and a silicon cap layer 305. The hetero semiconductor layer may be formed by the method according to the above-described embodiments. For example, the silicon germanium layer 304 may be formed by high temperature selective epitaxy growth, and the silicon cap layer 305 may be formed by high temperature selective epitaxy growth. Before forming the silicon cap layer 305, the silicon germanium layer 304 may be subjected to a blocking layer and a heat treatment. Thus, migration of the silicon germanium layer 304 can be suppressed.

The semiconductor structure according to the above embodiments may be applied to a DRAM (Dynamic Random Access Memory), and the present invention is not limited thereto, and may be a static random access memory (SRAM), a flash memory, a ferroelectric random access memory (FeRAM) (Magnetic Random Access Memory), and a PRAM (Phase Change Random Access Memory). In addition, the semiconductor structure may be applied to a logic device, an embedded memory, a power device, or the like.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

101: semiconductor substrate
102: first semiconductor layer
103: blocking layer
106: second semiconductor layer
107: heterogeneous semiconductor layer

Claims (28)

Forming a low temperature growth layer on a semiconductor substrate;
Forming a blocking layer on the low-temperature grown layer;
A heating process of the semiconductor substrate on which the blocking layer and the low temperature growth layer are formed;
The blocking layer
Removing; And
Forming a high temperature growth layer on the low temperature growth layer while maintaining the temperature of the heating treatment;
≪ / RTI >
The method according to claim 1,
The heating processing step includes:
Lt; RTI ID = 0.0 > a < / RTI > growth temperature of the low temperature grown layer.
The method according to claim 1,
Wherein the blocking layer is formed of a material that is non-selective to the low temperature grown layer.
The method according to claim 1,
Wherein the blocking layer is formed at a lower temperature than the heating process.
The method according to claim 1,
Wherein the low temperature growth layer is formed of a material having selectivity with respect to the semiconductor substrate.
The method according to claim 1,
Wherein the high temperature growth layer is formed of a material having selectivity to the low temperature growth layer.
The method according to claim 1,
Wherein the low temperature growth layer and the high temperature growth layer are formed by selective epitaxial growth (SEG), respectively.
Preparing a semiconductor substrate including a first region and a second region;
Forming a first semiconductor layer by low-temperature selective epitaxial growth on the second region;
Forming a blocking layer on the first semiconductor layer and the first region;
A heating process of the semiconductor substrate on which the blocking layer and the first semiconductor layer are formed;
Removing the blocking layer; And
Forming a second semiconductor layer on the first semiconductor layer by high temperature selective epitaxial growth while maintaining the heating process temperature,
≪ / RTI >
9. The method of claim 8,
The heating processing step includes:
Temperature selective epitaxy growth to a temperature higher than a growth temperature of the low temperature selective epitaxy growth.
9. The method of claim 8,
Wherein the blocking layer is formed of a material having non-selectivity for the first semiconductor layer and the first region.
9. The method of claim 8,
Wherein the blocking layer is formed at a temperature lower than the heating processing temperature.
9. The method of claim 8,
Wherein the first semiconductor layer, the blocking layer, and the second semiconductor layer are each formed of a silicon-base layer, and the blocking layer is formed of a material that inhibits migration of the first semiconductor layer.
Forming a silicon germanium layer by low-temperature selective epitaxial growth on a semiconductor substrate comprising silicon;
Forming a silicon blocking layer on the silicon germanium layer to inhibit migration of the silicon germanium layer;
A step of heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed;
Removing the silicon blocking layer; And
Forming a silicon cap layer by high-temperature selective epitaxial growth on the silicon germanium layer while maintaining the heating treatment temperature
≪ / RTI >
14. The method of claim 13,
Wherein the silicon blocking layer is formed of a material that is non-selective to the silicon germanium layer.
14. The method of claim 13,
Wherein the silicon blocking layer is formed at a temperature that inhibits migration of the silicon germanium layer.
14. The method of claim 13,
Wherein the silicon blocking layer is formed by CVD reaction of silicon-containing gas and H ₂ gas.
14. The method of claim 13,
The step of removing the silicon blocking layer may include:
A method of forming a semiconductor structure using HCl.
14. The method of claim 13,
Wherein forming the silicon blocking layer and the silicon cap layer comprises:
Wherein the silicon cap layer is formed by adding HCl gas, and the silicon blocking layer is formed by not adding the HCl gas.
Preparing a semiconductor substrate including a silicon-base region and an insulating region;
Performing low temperature selective epitaxy growth to form a silicon germanium layer on the silicon-base region;
Forming a silicon germanium layer on the silicon germanium layer and an isolation region and a silicon blocking layer having non-selectivity for the isolation region;
Heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed;
Removing the silicon blocking layer; And
Performing high temperature selective epitaxial growth to form a silicon cap layer on the silicon germanium layer while maintaining the heating treatment temperature,
≪ / RTI >
20. The method of claim 19,
Wherein the heat treatment temperature is higher than the growth temperature of the low temperature selective epitaxy growth.
20. The method of claim 19,
The heating processing step includes:
Increasing the growth temperature of the low temperature selective epitaxy growth to the heating processing temperature.
20. The method of claim 19,
The step of removing the silicon blocking layer may include:
A method of forming a semiconductor structure using HCl.
20. The method of claim 19,
Wherein forming the silicon blocking layer and the silicon cap layer comprises:
Wherein the silicon cap layer is formed by adding HCl gas, and the silicon blocking layer is formed by not adding the HCl gas.
20. The method of claim 19,
Wherein the silicon germanium layer and the silicon cap layer are channel regions of a PMOSFET.
20. The method of claim 19,
Wherein a CMOSFET including an NMOSFET and a PMOSFET is formed on the semiconductor substrate, and the silicon germanium layer and the silicon cap layer are channel regions of the PMOSFET.
20. The method of claim 19,
Wherein the silicon germanium layer and the silicon cap layer are channel regions of a FINFET.
Preparing a semiconductor substrate including a channel forming region and a source / drain forming region;
Forming a gate structure on the channel forming region;
Etching the source / drain formation region to form a sigmal trench;
Performing low temperature selective epitaxy growth to form a silicon germanium layer filling the trench;
Forming a silicon blocking layer having non-selectivity on the silicon germanium layer on the silicon germanium layer;
Heating the semiconductor substrate on which the silicon blocking layer and the silicon germanium layer are formed;
Removing the silicon blocking layer; And
Performing high temperature selective epitaxial growth to form a silicon cap layer on the silicon germanium layer while maintaining the heating treatment temperature,
≪ / RTI >
28. The method of claim 27,
After the step of forming the silicon cap layer,
And forming a silicide layer on the silicon cap layer.

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