KR20170038126A - Electronic device power protection circuitry - Google Patents

Abstract

The host electronic device may be coupled to an accessory electronic device. In normal operation, the host device can supply power to the accessory device via the power supply line. By interposing the protection transistor in the power supply line, a back-powering event in which the accessory device delivers power to the host device can be prevented. A current mirror may be formed using a protection transistor and an additional transistor that generate a sensing current proportional to the amount of current flowing through the power supply line. The current-voltage amplifier can generate a sense voltage proportional to the sense current. A bias circuit may be used to bias the sense current through the current mirror. The control circuit may compare the sense voltage with one or more reference voltages and turn off the protection transistor when it is suitable to prevent back-powering of the host device.

Description

[0001] ELECTRONIC DEVICE POWER PROTECTION CIRCUITRY [

This application is related to U.S. Patent Application No. 13 / 629,276, filed September 27, 2012, which is incorporated herein by reference in its entirety, U.S. Patent Application No. 61 / 660,634, filed June 15, 2012, U.S. Provisional Patent Application No. 61 / 664,691, filed on May 26,

FIELD OF THE INVENTION The present invention relates generally to electronic devices, and more particularly, to a power protection circuit for electronic devices.

Electronic devices such as cellular telephones, media players, tablet computers, and other devices are often coupled to accessories. For example, the accessory device may include a display, a speaker, or other components that may be used to play media files or other content by the host electronic device for the user.

During normal operation, the host device can supply power to the accessory. If the accessory is defective or poorly designed, the accessory may provide power to the host device instead of withdrawing power from the host device. This behavior can often be referred to as back-powering, which can cause damage to the host device.

Thus, when an accessory is coupled to an electronic device, it is required to be able to provide a protection circuit to prevent damage due to back-powering.

The accessory can potentially be back-powered to the host electronic device. To prevent damage to the host electronic device, the electronic device may include a protection circuit. The protection circuit may be used to block current flow between the accessory and the host device each time a back-powered state is detected.

The host electronic device may be coupled to the accessory electronic device by a power supply path. In normal operation, the host device can supply power to the accessory device via the power supply line. In some situations, the accessory may attempt to deliver power to the host device. This type of back-powering operation is undesirable and can be prevented by interposing a protection transistor in the power supply line. A current mirror may be formed using a protection transistor and an additional transistor. By using the bias circuit to keep the drain of the additional transistor at substantially the same voltage as the drain of the protection transistor, the accuracy of the current mirror can be improved. For example, the biasing circuit may include mirror transistors formed in a cascode structure. The biasing circuit may be used to bias the current through the additional transistor to match a predetermined bias current. By biasing the current to a predetermined bias current through the additional transistor and using the cascode architecture, the variations associated with temperature can be mitigated.

The current mirror can generate a sense current proportional to the amount of current that is currently flowing through the protection transistor and the power supply line. The current-voltage amplifier can generate a sense voltage proportional to the sense current. If desired, the bias circuit may be configured to generate a sense voltage that is proportional to the value of the current-voltage amplifier subtracting the sense current at a predetermined bias current. The control circuit can use a comparator to compare the sense voltage to the reference voltage.

The control circuitry turns on the protection transistor whenever the sensing voltage is at a level that indicates that power is flowing from the host to the accessory, allowing the host device to power the accessory. The protection transistor may also be turned on as long as a small amount of reverse current within an acceptable limit exists on the power supply line. When a back-powered state is detected, the control circuitry may turn off the transistor to prevent current flow from the accessory to the host device via the power supply line.

The control circuit can detect a serious back-powering condition using the first comparator. The control circuit can detect a moderate back-powering state for an excessive period of time using a second comparator and a detection circuit. The control circuit may turn off the protection transistor in response to either a severe back-powering state or a slight back-powering state for an excessive period of time.

A sink transistor may be coupled to the power supply line to cause the back-powering current to be diverted from the power supply circuit of the device. The sink transistor can be controlled by the control circuit based on the sense voltage to sink an appropriate amount of back-current.

Further features, characteristics and various advantages of the present invention will become more apparent from the following detailed description of preferred embodiments and accompanying drawings.

≪ 1 >
1 is a diagram of a system according to an embodiment of the present invention in which a host electronic device is coupled to an accessory electronic device.
2,
2 is a graph showing signals that can be measured in an electronic device to detect a back-powered state, in accordance with an embodiment of the present invention.
3,
3 is a circuit diagram of an exemplary protection circuit according to one embodiment of the present invention.
<Fig. 4>
4 is a circuit diagram of an exemplary protection circuit having a cascode mirror structure according to an embodiment of the present invention.
5,
5 is a diagram illustrating how the sense voltage may depend on the output current for the circuit of FIG. 4 in some way.
6,
Figure 6 is a diagram illustrating how the circuit of Figure 4 may help to mitigate variations in sense voltage associated with air temperature, in accordance with one embodiment of the present invention.
7,
Figure 7 is a diagram illustrating in some ways how the circuit of Figure 4 can be adjusted to different bias settings, in accordance with one embodiment of the present invention.
8,
8 is a diagram of an exemplary control circuit capable of detecting a severe back-powering state and a slight back-powering state, in accordance with an embodiment of the present invention.
9,
Figure 9 is a timing diagram illustrating in what way the control circuitry of Figure 8 responds to a severe back-powering state, in accordance with an embodiment of the present invention.
<Fig. 10>
10 is a timing diagram illustrating in some way how the control circuitry of FIG. 8 responds to some back-powered state, in accordance with one embodiment of the present invention.
11)
11 is a diagram of an exemplary protection circuit having a sink transistor in accordance with an embodiment of the present invention.

An exemplary system including an electronic device with a protection circuit is shown in Fig. As shown in FIG. 1, system 8 may include a host device, such as electronic device 10, and an accessory device, such as electronic device 14 or other external equipment. Path 12 may be used to couple devices 10 and 14. The path 12 may include power lines such as a positive power line 16 through which a positive power supply current flows and a ground power line 17 through which a ground power supply current flows. The path 12 may also include analog and / or digital signal lines (e.g., a pair of data lines, etc.). When power is being transferred from the host 10 to the accessory 14, the current I flowing through the line 16 will be positive.

The device 10 may have an input-output port with input-output power supply terminals T1 and T2. The device 14 may have an input-output port with input-output power supply terminals T3 and T4. The terminals T1 and T3 may be positive power supply terminals. The terminals T2 and T4 may be ground power supply terminals. When the device 10 and the device 14 are coupled together, the terminal T1 can be electrically connected to the terminal T3 through the line 16 and the terminal T2 can be electrically connected to the terminal 17 T4). Conductive paths 16 and 17 may form part of the cable or may be formed by direct contact between terminals T1 and T2 and between terminals T3 and T4. Terminals T1 and T2 may be associated with contacts in a connector (e.g., an input-output connector within an input-output port on device 10) within device 10. [ Terminals T3 and T4 may be associated with contacts within a connector 14 (e.g., an input-output connector within an input-output port on device 14).

Electronic devices such as devices 10 and 14 of Figure 1 may be used in cellular telephones, media players, other handheld portable devices, rather small handheld devices such as wristwatch devices, pendant devices, or other wearable ) Or miniature devices, gaming devices, tablet computers, notebook computers, desktop computers, televisions, computer monitors, computers integrated into computer displays, embedded devices such as equipment in the car, sound and / Equipment that includes a speaker and / or monitor for presentation, or other electronic equipment. For example, the host electronic device 10 may be a cellular telephone, a media player, or a computer, and the accessory electronic device 14 may include a speaker for presenting sound to the user and / or a display for presenting the video to the user Lt; / RTI &gt; Audio and / or video content to be displayed may be provided from the device 10 to the device 14 via a data path associated with the path 12.

The host 10 may include a storage and processing circuit 30 and an input-output circuit 28. The electronic device 14 may include a storage and processing circuit 48 and an input-output circuit 50. The storage and processing circuits 30 and 48 may include one or more integrated circuits, such as memory circuits, processors, and application-specific integrated circuits. Input-output circuitry 28 and input-output circuitry 50 may include user interface components such as buttons, speakers, microphones, displays, touch sensors, and other devices for collecting input or presenting output to a user have. The input-output circuit 28 may also include wired communication circuitry, wireless communication circuitry, sensors, and other electronic device components.

Power is supplied to the devices 10 and 14 using AC line power from a wall outlet or other AC power source (e.g., AC sources 20 and 52) . Batteries such as batteries 22 and 46 may also be used to obtain power.

Power regulator circuits 18 and 44 may be used to convert AC power from an AC source or battery power to a normalized source of direct current (DC) power for use by the electrical components of devices 10 and 14 (For example, a positive voltage on the + terminal and a zero or ground voltage on the - terminal).

During normal operation, the power regulator circuit 18 of the device 10 may provide a positive power supply voltage to the node 38. The protection transistor SW (acting as a protection switch) may be normally on so that the voltage on node 38 is transferred to node 36 (i.e., the switch formed by the transistor may be closed ). The positive signal line 16 may connect the positive power supply voltage node 36 in the device 10 to the positive power supply voltage node 54 in the device 14. The power supply ground line 17 may be used to couple the ground 56 within the device 14 to the ground 58 within the device 10.

When the transistor SW is on during normal operation, the host device 10 can supply power to the accessory 14 through the path 12. As a result, a positive current I can flow along the line 16. [ In accessories without a power source, there is no risk of back-powering. However, if the device 14 is designed to be faulty or poor, the power regulator circuit 44 may attempt to deliver power to the device 10 through the path 12. In this type of situation, a negative value of current I may be generated on line 16.

To prevent damage to the device 10, the transistor SW can be turned off (i.e., the switch SW can be opened) as soon as the device 10 detects the back-powering state. For example, when the I value is below -5 mA or other suitable threshold (i.e., when the magnitude of current I exceeds a given threshold, the polarity of current I is negative) The transistor SW may be turned off to generate an open circuit between the source D1 and the source S1.

The control circuit 24 can be used to control the state of the transistor SW by applying a control signal such as the control voltage Vcnt to the gate G1 of the transistor SW through the control line 42. [ When the control circuit 24 asserts the control signal Vcnt, the transistor SW may be turned on to allow power to flow from the power regulator circuit 18 to the path 12. [ When the control circuit 24 deasserts the control Vcnt, the current flow into the device 10 from the device 14 is blocked, thereby preventing the device 10 from being damaged during the back- The transistor SW may be turned off.

The control circuit 24 may monitor the amount of current flowing through the transistor SW using a current sensing circuit such as a current mirror circuit with a bias circuit and a current-voltage amplifier circuit (i.e., circuit 26). Circuit 26 may be coupled to terminal 36 using path 32 and coupled to terminal 38 via path 34. [ The circuit 26 may be coupled to the gate of the transistor SW via path 66. In operation, the components of the circuit 26 may form a current mirror with the transistor SW. The current mirror and the associated circuitry of the circuit 26 may facilitate monitoring of the current I.

As the current I passes through the transistor SW, a proportional voltage drop Vdrop occurs across the terminals 36 and 38. Since the transistor SW is on, the value of Vdrop may be relatively small, so measuring I based on Vdrop becomes challenging and potentially vulnerable to noise on line 16. [ Thus, the device 10 preferably includes a current mirror formed using the transistor SW and the circuit 26. The current-voltage amplifier circuit associated with the current mirror circuit of the device 10 can be used to convert the sense current Isense, which is a small current proportional to the current I, to a voltage Vsense proportional to the current I. The control circuit 24 may receive the signal voltage Vsense from the circuit 26 via the path 40.

As shown by curve 60 in FIG. 2, the magnitude of Vdrop over the range of operable current (e.g., -200 mA to 500 mA in the example of FIG. 2) may be relatively small and the function of current I As shown in FIG. As indicated by the straight line 62 in FIG. 2, the magnitude of Vsense may be considerably larger (for example, 10 to 100 times greater (by example)). The voltage Vsense can also vary considerably as a function of the current I. A change in Vsense for a given change in current I (i.e., the slope of the straight line 62) is greater than a change in Vdrop for a given change in current (I) (I.e., the slope of the straight line 62), using Vsense by the control circuit 24 to make a determination as to the state of the transistor SW can improve accuracy.

FIG. 3 is a circuit diagram illustrating exemplary components that may be used to implement circuitry 26 and circuitry 24. As shown in Figure 3, the circuit 26 may comprise a transistor, such as transistor M2 and transistor M2 configured to form a current mirror. The circuit 26 may also include a bias circuit and a current-voltage amplifier circuit 68. The bias and current-voltage amplifier circuit 68 includes transistors M1 and M6 configured to drive a sense current Isense across resistor R to produce a voltage Vsense on line 40 ). &Lt; / RTI &gt;

The transistor SW may include a source terminal S1, a drain terminal D1 and a gate terminal G1. The transistor M2 may include a source terminal S2, a drain terminal D2 and a gate terminal G2. The source S1 of the transistor SW has the same voltage as the source S2 of the transistor M2 and the gate of the transistor SW is connected to the gate of the transistor SW for optimal accuracy of the current mirror formed by the transistors SW and M2. It is preferable that the gate G1 has the same voltage as the gate G2 of the transistor M2. This can be achieved by electrically connecting source S1 and source S2 using line 32 and electrically connecting gate G1 and gate G2 using line 66. [

The drains D1 and D2 must also be maintained at the same voltage to ensure correct operation of the current mirror. The drains D1 and D2 of the transistors SW and M2 are not short-circuited together. Nevertheless, the bias circuit of the circuit 68 can be used to match the voltage at the node 72 (and thus the drain D2) to the voltage at the drain D1. The current mirror formed from the transistors SW and M2 can be used to reduce the current on the line D2 by forcing the voltage level on the drain D2 to be at the voltage level on the drain Dl, I sense on the line 32 that exactly follows the value of the current I (I). In a typical configuration, transistors M2 and SW may be configured so that Isense is a small fraction of I (e.g., so that Isense is 10 ^-6 * I or another suitable part of I). Thus the current I passing through line 14 is proportional to the magnitude of the current through transistor SW and the magnitude of the current passing through transistor 12 to the extent that the current Isense drawn through path 32 is negligible and negligible. Will be substantially the same.

Transistors M1 and M6 may form a common gate amplifier used to convert current Isense to voltage Vsense on line 40. [ As shown in Figure 3, transistor M6 is diode connected (i.e., drain D6 and gate G6 are connected by path 76). The current source 78 generates a biasing current Ibias that sets the DC voltage on the drain D6 (node 74). Node 74 is lower than the voltage at node 38 by 1 Vgs (i.e., one gate-to-source voltage of transistor M6 at current Ibias). The voltage on node 74 is provided to gate G of transistor M1 to set the operating point of transistor M1. The voltage at the source terminal S (i.e., the node 72 and the drain D2 of the transistor M2) of the transistor M1 is higher than the voltage at the node 38 (i.e., the drain D1 of the transistor SW) Because the voltage at node 72 is higher than the voltage at node 74 by 1 Vgs and the voltage at node 74 is higher than the voltage at node 38 Because it is as low as 1 Vgs (of M6). As a result of this biasing circuit operation, the voltage on drain D2 substantially matches the voltage on drain D1 and helps ensure accurate current mirror operation.

Since the transistors M2 and SW form a current mirror, the current Isense of the transistor M2 is proportional to the current of the transistor SW. The current Isense flows through sense resistor R and produces a voltage drop (Vsense) on line 40. [ The control circuit 24 may comprise a comparator, such as comparator 80. The comparator 80 compares the voltage Vsense on the input 82 to the reference voltage Vref on the input 84 and determines whether the Vsense is higher or lower than Vref, An output signal can be generated. Using the state of the signal on line 86, control circuit 24 can assert or deassert control signal Vcnt on line 42. [

The value of the reference voltage Vref may be set to a value corresponding to the reverse current threshold required for the path 14. [ For example, Vref may be set to a level corresponding to the -5 mA value for current (I). The device 10 can satisfactorily sink the reverse current I without causing damage to the internal components since the amount of current flowing into the device 10 is minimal when the value of I is greater than -5 mA and less than 0 . If the value of I exceeds 0, the back-powering state does not appear and the device 10 and accessory 14 operate normally. In both cases of this situation, the control circuit 24 may assert the Vcnt signal on line 42 to ensure that the transistor SW is on. When the transistor SW is on, the nodes 38 and 36 are shorted together and the device 10 and the device 14 are connected to the device 14 via the path 12 It can be operated in a powering mode.

To help ensure correct operation, the reference voltage Vref may be calibrated. For example, the value of Vref may be set to a value that removes the internal offset from the comparator, and the control circuit may be set to the desired value of current I (e.g., -5 mA or other suitable level) Is triggered.

If the value of I is less than the threshold current value of -5 mA (in this example), the output on line 86 will toggle (invert). The control circuit 24 will respond accordingly by deasserting the control signal Vcnt to turn off the transistor SW. When the transistor SW is turned off, the back-powering current flowing from the device 14 to the device 12 is blocked, thereby preventing damage to the circuit of the device 10. [

The accuracy of a common gate amplifier formed from transistors M1 and M6 can be improved by using matched transistors. The strength (width to length values) of the transistors M2 and SW may be a ratio (K value) of about 10 ^-2 to 10 ^-4 or a suitable ratio. For example, the transistor M2 may have an intensity of about one-thousandth of the intensity of the transistor SW.

The bias circuit used to aid in the detection of the back-powering state may be provided with a cascode circuit for improved circuit biasing. 4 is an exemplary circuit diagram showing how the bias circuit and current-voltage circuit 68 can form a cascode structure. 4, the bias current Ibias may be mirrored to circuit branches 102 and 104 by transistors M8, M9, and M12 (e.g., transistors M8 and M9) Transistors M8 and M12 may form a current mirror for circuit branch 102, while transistors M8 and M12 may form a current mirror for circuit branch 102.)

Transistors M11 and M13 may function as cascode transistors that help isolate current mirror transistors M9 and M12 from variations associated with different drain voltages. For example, transistor M11 may help to match the drain-source voltage of transistor M9 to transistor M8, which tends to isolate the operation of transistor M9 from variations in current Isense (For example, the drain-source and gate-source voltages of transistor M9 match the drain-source and gate-source voltages of transistor M8). The transistors M3, M5, M4 and M7 can function as a cascode structure which helps to match the voltage at the drain D2 of the transistor M2 to the voltage at the drain D1 of the transistor SW.

A current Isense mirrored from the transistor SW by the transistor M2 can be provided to the transistors M1 and M3. The current Isense may be partitioned into currents Is2 and Is1. The current Is2 may be determined by the amount of current source current mirror transistor M12 (e.g., current Is2 may be equivalent to Ibias and current I1). The current Is1 may reflect any residual current from Isense. For example, in the case of an Isense current greater than the current Is2 (e.g., a current greater than Ibias), the current Is1 may reflect the current difference between Isense and Is2. As another example, in the case of insufficient current Isense (e.g., a current lower than Ibias), the minimum amount of current may flow through resistor R. The current Is1 may be routed through the circuit branch 106 and amplified by the resistor R to produce the voltage Vsense.

5 is an exemplary diagram illustrating how the voltage Vsense produced by the circuit of FIG. 4 varies in some way with output current I (e.g., the output current provided to the accessory device). As shown in Fig. 5, Vsense at the output current Ia may be 0 volts. The value of Ia may reflect the difference between the bias currents I1 and Is2 of the circuit branches 102 and 104. [ For example, if I1 is equal to Is2 as the transistors M9 and M12 are matched, Ia can be the minimum value (e.g., Ia can be a value between -2 mA and 0 mA, such as -1.5 mA has exist). In other words, when the current Isense is equal to the current Is2 and no current flows through the resistor R, Vsense can be 0 volts. At a device output current greater than Ia, the voltage Vsense can be maintained at zero volts.

The control circuit 24 is responsive to determining that the voltage Vsense exceeds the threshold voltage Vb (for example, when the back-power current exceeds the magnitude of the current Ib) May be configured to be disabled. The threshold voltage Vb can be selected based on the ability of the power regulator circuit 18 to withstand a back-power current having a magnitude up to the magnitude of Ib.

The biasing circuit 68 of Figure 4 helps to ensure that the voltage at the drain Dl of transistor SW and the voltage at drain D2 of transistor M2 during the back-powering threshold state are matched. The current Isense is substantially equal to the current IS2 at the output current Ia (e.g., at the minimum output current level), and the transistors M1, M3, M4, M5, M6, M7, M11, M9, M13 and M12 assist in ensuring that the voltage at the drain D1 of the transistor SW is approximately equal to the voltage at the drain D2 of the transistor M2.

By matching the voltages at D1 and D2, the biasing circuit 68 can help to protect against temperature fluctuations. FIG. 6 is an exemplary diagram illustrating how the variation in Vsense associated with a change in air temperature can be mitigated by the biasing circuit 68. FIG. As shown in FIG. 6, line 112 may correspond to Vsense generated at first temperature T1, line 114 may correspond to Vsense generated at second temperature T2, 116 may correspond to Vsense generated at the third temperature T3. The output currents in the window 118 surrounding current Ia, lines 112, 114, and 116, may have a minimum difference (e.g., Vsense may be insensitive to temperature fluctuations within window 118) has exist).

If required, the threshold current Ia at which the voltage Vsense is generated can be regulated. The threshold current Ia can be adjusted by adjusting the difference between the current I1 of the circuit branch 102 and the current Is2 of the circuit branch 104. [ For example, the width-to-length ratio (W / L) of transistor M9 to the width to length ratio (W / L) of the transistor is the difference between current I1 and current Is2 . &Lt; / RTI &gt; The width to length ratio W / L of the transistor M12 can be increased compared to the transistor M9 in order to increase the current Is2 (for example, increase the width W of the transistor M12) Or by decreasing the width W of the transistor M9). Figure 7 is an exemplary diagram illustrating how the threshold current Ia can be controlled by adjusting the size of the current mirror transistors M9 and M12.

As shown in FIG. 7, line 122 may correspond to a threshold current Ia. The threshold current of the bias circuit and the current-voltage amplifier circuit 26 can be increased to the threshold current Ia 'by reducing the width-to-length ratio W / L between the transistors M12 and M9. For example, the width to length ratio W / L of the transistor M12 can be reduced with respect to the width to length ratio W / L of the transistor M9. In this scenario, the current Is2 through transistor M12 can be reduced for current I1 through transistor M9, which is provided to sense resistor R for any given output current I (For example, the sense voltage of line 126 may be greater than the sense voltage of line 122 at any given output current I). Similarly, by increasing the width to length ratio (W / L) of M12 to the width to length ratio (W / L) of M9, the threshold current can be reduced to Ia ''.

Figure 8 is an exemplary diagram of a control circuit 24 that may be provided to generate a control signal Vcnt in response to a sense voltage Vsense generated by circuit 26. [ 8, the control circuit 24 may include comparators 132 and 134 that receive the voltage Vsense and compare Vsense with their respective reference voltages Vref1 and Vref2. Vref1 may be a voltage suitable for detecting large voltages associated with a severe back-power condition (e.g., C1 may be asserted when Vsense is greater than Vref1). Vref2 may be a voltage suitable for detecting smaller voltages associated with some back-power state (e.g., C2 may be asserted when Vsense is greater than Vref2). For example, Vref1 may be the voltage sensed by circuit 26 when Isense is approximately 200 mA, while Vref2 may be the voltage sensed by circuit 26 when Isense is approximately 5 mA. This example is merely illustrative. Vref1 and Vref2 may be any voltages required to detect the back-power state.

The detection circuitry 136 may receive the signal C2 from the comparator 134 and may determine that C2 is continuously being programmed for longer than a predetermined threshold time period (e.g., 10uS, 100uS, or any other desired threshold period) And detects when it is being thrown. For example, if the output of the comparator 134 is continuously asserted longer than 10 uS, the detection circuit 136 may assert the detection signal D1 provided to the control circuit 138. This example is merely illustrative. Detection circuit 136 may be configured with any desired threshold time value. For example, the threshold time value may be determined based on the capabilities of the regulator circuit 18 of the device 10, which can withstand a moderate amount of back-power current from the electronic device 14. [

Detection circuit 136 may comprise digital and / or analog based detection circuits. For example, the detection circuit 136 may include a clock-based counter that detects how many clock cycles the assertion has continued at the output of the comparator 134. In such a scenario, the detection circuit 136 may assert the detection signal D1 in response to determining that the counter has reached a predetermined value (e. G., A counter threshold). This example is merely illustrative. If desired, the detection circuitry 136 may comprise a state machine based detection circuit, an RC based detection circuit, or any desired circuitry that detects how long the output of the comparator 134 has been asserted.

9 is an exemplary diagram illustrating the operation of the control circuit 24 during the back-powering state. 9, the device output current I may oscillate primarily (e.g., the power supply path inductance associated with paths 16 and 17 may cause the power to flow to the host 10) Which may cause ringing when supplied to the accessory 14). The primary ringing may be of sufficient magnitude to trigger the comparator 134 to assert the signal C2 during times T1 and T2 (e.g., the corresponding Vsense voltage having a magnitude greater than Vref2 is at time T1 And T2). However, the detection circuit 136 can determine that the times T1 and T2 are not sufficient periods, and the detection signal D1 can be maintained deasserted.

During the time T3, a severe back-powering condition may occur, during which back-power sufficient to trigger the comparator 132 is received by the device 10 (e.g., current I) Is sufficiently negative for circuit 26 to generate a Vsense voltage that is greater than Vref1. In such a scenario, the control circuit 138 may disable the transistor SW to protect the device 10 from the back-powered state (e.g., by deasserting Vcnt).

10 is an exemplary diagram illustrating the operation of the control circuit 24 during some back-powering states. 10, the device output current I can be stabilized with a slight magnitude of negative current after the primary ringing (e.g., the amount of back-power current after the primary ringing causes the comparator 134 to &lt; RTI ID = May be sufficient to trigger to assert signal C2 during time T5, but may be insufficient to trigger comparator 132). 10, the detection circuit 136 detects the detection signal D1 at the end of the time period T5 (for example, because the signal C2 has been continuously asserted for longer than the predetermined threshold) Can be asserted. Control circuit 138 may deassert Vcnt in response to signal D1 being asserted.

11 is an exemplary diagram illustrating how the control circuit 24 can be used to control the sink transistor 202 by providing a control signal Vs to the gate of the sink transistor 202 . The control signal (Vs) may be determined based on the voltage (Vsense) provided by the current-voltage amplifier circuit (26). During the back-power state, the control circuit 24 uses the control signal Vs to control so that the sink current Is passing through the transistor 202 will deboost the back-power current from the power regulator circuit 18 .

According to one embodiment, in an electronic device configured to provide power to an accessory via a path including a power supply line, the provided electronic device includes: a power regulator circuit for providing a power supply voltage to the power supply line, A first transistor and a second transistor interposed in a power supply line, the first and second transistors forming a current mirror that generates a signal indicating how much current is flowing to the first transistor, Circuitry to provide a control signal to the first transistor to turn off the first transistor if the signal indicates that the current flowing through the electronic device is associated with a back-powered state in which the electronic device is receiving power from the accessory.

According to yet another embodiment, the circuit includes a control circuit for monitoring a sense voltage proportional to the signal, wherein in response to a given change in current flowing through the first transistor, the voltage drop across the first transistor is greater than a first amount And the sense voltage varies by a second amount in response to a given change in current flowing through the first transistor, the second amount being greater than the first amount.

According to yet another embodiment, the circuit includes a current-voltage amplifier that converts the signal to a sense voltage.

According to another embodiment, the current-voltage amplifier comprises a pair of transistors coupled to form a common gate amplifier.

According to yet another embodiment, the control circuit comprises a comparator for receiving the sense voltage and the reference voltage.

According to yet another embodiment, the first transistor has a first source, a first drain and a first gate, the second transistor has a second source, a second drain and a second gate, And a bias circuit for biasing the second drain to match the voltage.

According to yet another embodiment, the current mirror includes a first line coupling a first source to a second source and a second line coupling a first gate to a second gate.

According to yet another embodiment, the circuit is configured to assert a control signal to turn on the first transistor in response to determining that the current flowing through the first transistor exceeds a given threshold, To de-select the control signal to turn off the first transistor in response to determining that the current flowing through the first transistor is less than a given threshold.

According to another embodiment, a given threshold has a negative value, the control circuit has a comparator with a first input and a second input, and the second input is configured to receive a reference voltage representative of a threshold .

According to yet another embodiment, the electronic device comprises a device selected from the group comprising a cellular telephone, a tablet computer, a portable computer and a media player, wherein the electronic device further comprises a storage unit and a processing circuit.

According to yet another embodiment, a protection circuit in an electronic device that prevents power transfer from an external device to an electronic device during a back-powering state, the protection circuit being provided includes: coupling to a power supply input- A power supply current flows through the first transistor during at least part of operation of the first transistor-protection circuit; a second transistor coupled to the first transistor to form a current mirror; Generating a sense current proportional to the current, and providing a control signal to turn off the first transistor during the back-powering state in response to the sense current.

According to yet another embodiment, the circuit includes a current-voltage amplifier that converts the sense current to a sense voltage.

According to yet another embodiment, the circuit includes a control circuit that monitors the sense voltage and provides a control signal based on the sense voltage.

According to another embodiment, the control circuit comprises a comparator having a first input for receiving a sense voltage and a second voltage for receiving a reference voltage.

According to yet another embodiment, the circuit includes a biasing circuit for biasing the drain voltage in the second transistor to match the drain voltage of the first transistor.

According to another embodiment, the biasing circuit comprises a current source.

According to yet another embodiment, an electronic device is provided and comprises: a first input-output terminal, a second input-output terminal, a ground power supply line coupled to a second input-output terminal, a first input- A first transistor coupled to the positive power supply line, a second transistor coupled to the first transistor and forming a current mirror, the current mirror coupled to the first transistor and the positive power supply line, Generating a sense current proportional to the current flowing through the current sensor; and a current-voltage amplifier circuit converting the sense current into a sense voltage.

According to another embodiment, the current-voltage amplifier includes a resistor through which the sense current flows.

According to another embodiment, the electronic device includes a control circuit that receives the sense voltage and generates a corresponding control signal to control the first transistor.

According to yet another embodiment, the control circuit comprises a comparator having a first input for receiving a sense voltage and a second input for receiving a reference voltage, wherein the electronic device further comprises a signal line, To the gate of the first transistor.

According to one embodiment, the provided electronic device includes a power supply terminal, a power regulator circuit operable to supply power to the external equipment via the power supply terminal, a protection circuit coupled to the power supply terminal, Power ring state in which a current is received at the power supply terminal by the power supply terminal, and the protection circuit is further configured to electrically disconnect the power regulator circuit from the power supply terminal in response to detecting the back- .

According to one embodiment, an electronic device configured to provide power to an accessory via a path including a power supply line, the provided electronic device comprising: a power regulator circuit for providing a power supply voltage to the power supply line; Wherein the first transistor, the second transistor, the first transistor and the second transistor interposed in the supply line form a current mirror that generates a signal indicating how much current flows through the first transistor, Bias circuit coupled to the transistor and providing a current bias for the second transistor comprises an additional current mirror formed from at least one cascode transistor and a second current mirror coupled to the first current mirror based on the signal generated by the current mirror, Controls that can be operated to control transistors .

According to yet another embodiment, the bias circuit includes a first branch and a second branch, wherein a first portion of the current bias for the second transistor flows through the first branch and a second portion of the current bias flows through the second branch Lt; / RTI &gt;

According to another embodiment, the first branch includes a resistor, and the signal is generated by a voltage drop across a resistor associated with the first portion of the current bias.

According to another embodiment, the additional current mirror includes a fourth transistor for mirroring the third transistor and the third transistor, and the cascode transistor is coupled to the fourth transistor.

According to another embodiment, the current mirror includes a first current mirror, the additional current mirror includes a second current mirror, and the first branch includes a fifth transistor through which a second portion of the current bias flows The fifth transistor forms a third current mirror with the third transistor and the fifth transistor of the third current mirror has a width to length ratio different from the width to length ratio of the fourth transistor of the second current mirror .

According to yet another embodiment, the provided electronic device includes a power supply terminal, a power regulator circuit operable to supply power to the external equipment through the power supply terminal, and a protection circuit coupled to the power supply terminal, Wherein the protection circuit is configured to detect a back-powering state in which current is received by the electronic device at a power supply terminal for a continuous period exceeding a threshold, And is further configured to be electrically disconnected from the supply terminal.

According to yet another embodiment, the protection circuit comprises a current mirror for generating a signal indicating how much current is received by the electronic device at the power supply terminal, a current mirror for comparing the signal with a first reference voltage to generate a first control signal, 1 comparator, and a second comparator for comparing the signal with a second reference voltage to generate a second control signal, wherein the first reference voltage is greater than the second reference voltage.

According to yet another embodiment, the protection circuit further comprises a detection circuit for receiving the second control signal and for generating a detection signal for identifying the second control signal when it is continuously asserted for a period of time exceeding the threshold value .

According to yet another embodiment, the electronic device includes a control circuit for receiving a first control signal and a detection signal, wherein the control circuit electrically couples the power regulator circuit from the power supply terminal in response to the first control signal being asserted And disconnected.

According to yet another embodiment, the detection circuit is configured to assert a detection signal in response to identifying that the second control signal is continuously asserted for a period of time exceeding a threshold, The power regulator circuit is electrically disconnected from the power supply terminal.

The foregoing is merely illustrative of the principles of the invention, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the invention. The embodiments may be implemented individually or in any combination.

Claims (1)

The apparatus of claim 1,

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